IR3629A

Data Sheet No. PD94726 IR3629/IR3629A MPbF HIGH FREQUENCY SYNCHRONOUS PWM BUCK CONTROLLER WITH POWER GOOD OUTPUT Features • • • • • • • • • • • • • • • • • Internal 600kHz Oscillator (300kHz “A version”) Operates with Single 5V or 12V Supply Programmable Over Current Protection Hiccup Current Limit Using MOSFET RDS(on) sensing Precision Reference Voltage (0.6V) Programmable Soft-Start Programmable PGood output Pre-Bias Start-up Thermal Protection 12-Lead MLP Package Distributed Point-of-Loads Embedded Systems Storage Systems DDR Applications Graphics Cards Computing Peripheral Voltage Regulators General DC-DC Converters Description The IR3629/IR3629A is a PWM controller designed for high performance synchronous Buck DC/DC applications. The IR3629/IR3629A drives a pair of external N-MOSFETs using a fixed 600kHz (300kHz “A version”) switching frequency allowing the use of small external components. The output voltage can be precisely regulated using the internal 0.6V reference voltage for low voltage applications. Protection such as Pre-Bias startup, hiccup current limit and thermal shutdown provide the required system level security in the event of fault conditions. Applications Fig. 1: Typical application Circuit ORDERING INFORMATION PKG DESIG M M PACKAGE PIN DESCRIPTION COUNT IR3629/IR3629AMPBF 12 IR3629/IR3629AMTRPBF 12 PARTS PARTS T&R PER TUBE PER REEL ORIENTATION 122 -------------3000 Figure A 11/26/2007 IR3629/IR3629A MPbF ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND) • • • • • • • • • • Vcc Supply Voltage ................................................… -0.5V to 16V Vc Supply Voltage …………………………………….. -0.5V to 30V PGood ………………………………………………… -0.5V to 16V Fb, Comp, SS ……………………..………………….. -0.3V to 3.5V OCset ………………………………………………… 10mA AGnd to PGnd ………………………………….…….. -0.3V to +0.3V Storage Temperature Range ..................................... -65°C To 150°C Operating Junction Temperature Range ................... -40°C To 150°C ESD Classification …………………………………..… JEDEC, JESD22-A114 Moisture Sensitivity Level ……………………………. JEDEC Level 2 @ 260oC Caution: Stresses beyond those listed under “Absolute Maximum Rating” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to “Absolute Maximum Rating” conditions for extended periods may affect device reliability. Package Information PGood VCC LDrv PGnd HDrv VC 12 11 10 9 8 7 1 2 3 4 5 6 OCSet SS/SD Gnd Comp Fb Vsns Exposed Pad 12-Lead MLPD, 3x4mm ΘJA = 30o C/W * ΘJC = 2o C/W *Exposed pad on underside is connected to a copper pad through vias for 4-layer PCB board design 11/26/2007 2 IR3629/IR3629A MPbF Block Diagram Fig. 2: Simplified block diagram of the IR3629/IR3629A 11/26/2007 3 IR3629/IR3629A MPbF Pin Description Pin Name 1 2 3 4 5 6 7 8 9 10 11 PGood Vcc LDrv PGnd HDrv Vc Vsns Fb Comp Gnd SS/SD Description Power Good status pin. Output is open collector. Connect a pull up resistor from this pin to Vcc. This pin provides biasing voltage for the internal blocks of the IC. It also biases the low side driver. A minimum of 0.1uF, high frequency capacitor must be connected from this pin to power ground. Output driver for the low side MOSFET Power Ground. This pin serves as a separate ground for the MOSFET drivers and should be connected to the system’s power ground plane. Output driver for the high side MOSFET This pin powers the high side driver and must be connected to a voltage higher than bus voltage. A minimum of 0.1uF, high frequency capacitor must be connected from this pin to power ground. PGood sense pin Inverting input to the error amplifier. This pin is connected directly to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier. Output of the error amplifier. Signal ground for internal reference and control circuitry. Soft start / shutdown. This pin provides user programmable soft-start function. Connect an external capacitor from this pin to ground to set the start up time of the output voltage. The converter can be shutdown by pulling this pin below 0.3V. Current limit set point. A resistor from this pin to drain of the low side MOSFET will set the current limit threshold. 12 OCSet 11/26/2007 4 IR3629/IR3629A MPbF Recommended Operating Conditions Symbol Vcc Vc Tj (Note1) Definition Supply Voltage Supply Voltage Junction Temperature Min 4.5 Converter voltage + 5V -40 Max 14 28 125 Units V V o C Note1: The junction temperature for 5V application is 0oC-125oC Electrical Specifications Unless otherwise specified, these specification apply over Vcc=Vc=12V, 0oC 1 - - - (17) Cross over frequency is expressed as: By replacing Zin and Zf according to figure 15, the transfer function can be expressed as: (1 + sR3C4 ) * [1 + sC7 (R8 + R10 )] 1 * sR8 (C4 + C3 ) ⎡ ⎛ C4 * C3 ⎞⎤ ⎢1 + sR3 ⎜ ⎟ ⎜ C + C ⎟⎥ * (1 + sR10C7 ) 3 ⎠⎦ ⎝4 ⎣ Fo = R3 * C7 * Vin 1 * Vosc 2π * Lo * Co H (s ) = 11/26/2007 15 IR3629/IR3629A MPbF Based on the frequency of the zero generated by the output capacitor and its ESR versus crossover frequency, the compensation type can be different. The table below shows the compensation types and location of the crossover frequency. Compensator type TypII(PI) TypeIII(PID) Method A TypeIII(PID) Method B FESR vs. Fo Output capacitor Electrolytic , Tantalum Tantalum, ceramic Ceramic The following design rules will give a crossover frequency approximately one-tenth of the switching frequency. The higher the band width, the potentially faster the load transient response. The DC gain will be large enough to provide high DC-regulation accuracy (typically -5dB to -12dB). The phase margin should be greater than 45o for overall stability. Desired Phase Margin: 1 SinΘ FZ 2 = Fo * 1 + SinΘ FZ 2 = 16kHz 1 + SinΘ 1 SinΘ FP 2 = 224kHz FP 2 = Fo * Select : FZ1 = 0.5 * FZ 2 and FP3 = 0.5 * Fs R3 ≥ 2 ; R ≥ 2KΩ; Select : R3 = 10KΩ gm 3 FLC