IRDC3640

IRDC3640 USER GUIDE FOR IR3640 EVALUATION BOARD DESCRIPTION An output over-current protection function is implemented by sensing the voltage developed across the on-resistance of the synchronous rectifier MOSFET for optimum cost and performance. This user guide contains the schematic and bill of materials for the IR3640 evaluation board. The guide describes operation and use of the evaluation board itself. Detailed application information for IR3640 is available in the IR3640 data sheet. The IR3640 is a PWM controller for use in high performance synchronous Buck DC/DC applications. This is designed to drive a pair of external NFETs using a programmable switching frequency up to 1.5MHz in voltage mode. It is housed in a in 20 Lead 3x4 MLPQ package. Key features offered by the IR3640 include programmable soft-start ramp, Power Good, thermal protection, over voltage and over current protection, programmable switching frequency, tracking input, enable input, input under-voltage lockout for proper start-up, and pre-bias start-up. BOARD FEATURES • Vin = +12V (13.2V Max) • Vcc= +5V (5.5V Max) • Vout = +1.8V @ 0- 25A • Fs = 600kHz • L = 0.33uH • Cin= 4x10uF (ceramic 1210) + 2x330uF (electrolytic) • Cout= 10x47uF (ceramic 0805) 1 IRDC3640 CONNECTIONS and OPERATING INSTRUCTIONS A well regulated +12V input supply should be connected to VIN+ and VIN-. A maximum 25A load should be connected to VOUT+ and VOUT-. The connection diagram is shown in Fig. 1 and inputs and outputs of the board are listed in Table I. IR3640 has two input supplies, one for biasing (Vcc) and the other as input voltage (Vin). Separate supplies should be applied to these inputs. Vcc input should be a well regulated 4.5V-5.5V supply and it would be connected to Vcc+ and Vcc-. Table I. Connections Connection VIN+ VINVcc+ VccVOUT+ VOUTSync PGood Signal Name Vin (+12V) Ground of Vin Vcc input Ground for Vcc input Vout (+1.8V) Ground of Vout Synchronous input Power Good Signal LAYOUT The PCB is a 6-layer board. All of layers are 2 Oz. copper. The IR3640 and other components are mounted on the top and bottom side of the board. Power supply decoupling capacitors, the Bootstrap capacitor and feedback components are located close to IR3640. The feedback resistors are connected to the output voltage at the point of regulation and are located close to IR3640. To improve efficiency, the circuit board is designed to minimize the length of the on-board power ground current path. 2 IRDC3640 Connection Diagram Vin = +12V VOUT = +1.8V GROUND GROUND GROUND Vcc = +5V Fig. 1: Connection diagram of IR3640 evaluation board (top and bottom) 3 IRDC3640 Fig. 2: Board layout, top layer Fig. 3: Board layout, bottom layer 4 IRDC3640 Single point connection between AGND and PGND. Fig. 4: Board layout, mid-layer I Fig. 5: Board layout, mid-layer II 5 IRDC3640 Fig. 6: Board layout, mid-layer III Fig. 7: Board layout, mid-layer IV 6 Vin Vin+ 1 Enable R3 Vin+ 1 4.99K 1 C6 N/S 0.1uF 1 C1 N/S C2 10uF C3 10uF C4 10uF C5 10uF C27 + + C26 330uF C25 330uF Vin1 PVcc PGND 1 AGND 1 2 6 7 Vcc C17 1.0uF R4 681 1 Vin- R21 0 20 6 1 U1 8 7 Q1 5 IRF6710SPbF 3 4 5 1 2 6 7 4 16 Q2 5 47uF 47uF 3 4 IRF6795MPbF L1 0.33uH C9 C10 47uF C11 2 3 11 R8 2.26K N 3065200 NC6 NC1 PVcc Vcc HDrv PGood SW 9 Vp LDrv Rt PGnd 15 LGnd Sync Fb SS/SD 13 18 12 10 Vsns C20 0.1uF R11 2.55K C21 5600pF C22 160pF R13 3.24K R17 1 4.02K R19 2.55K 1 R14 130 C23 2200pF R18 20 1 C30 N/S R12 4.12K Comp Boot 19 17 R22 0 C7 0.1uF PGood 1 1 Vp 1 C8 Enable Vout 1 Vout+ 1 R5 0.1uF R6 4.99K R7 N/S 0 Vout+ 1 C12 47uF C13 47uF C14 47uF C15 47uF C16 47uF C28 0.1uF Vout1 Vout1 IR3640 OCset R10 N/S C19 N/S R9 23.7K 14 SS 1 C31 47uF C32 + C35 47uF N/S + C36 N/S R20 0 Sy nc A B IRDC3640 Fig.8: Schematic of the IR3640 evaluation board 7 IRDC3640 Bill of Materials Item Quantity Reference 1 10 VOUT-,VOUT+,VIN-,VIN+, Sync,PVcc,PGood,PGND,B,A 2 4 C2,C3,C4,C5 3 5 C7,C8,C20,C27,C28 4 10 C9,C10,C11,C12,C13, C14,C15,C16,C31,C32 5 1 C17 6 1 C21 7 1 C22 8 1 C23 9 2 C25,C26 10 1 L1 11 1 Q1 12 1 Q2 13 3 R5,R21,R22 14 2 R3,R6 15 1 R4 16 1 R8 17 1 R9 18 2 R11,R19 19 1 R12 20 1 R13 21 1 R14 22 1 R17 23 1 R18 24 4 TP11,TP12,TP13,TP14 25 1 U1 Value 0.075" SQ_SMT _TestPoint 10uF 0.1uF 47uF 1.0uF 5.6nF 160pF 2200pF 330uF 0.33uH IRF6710S2TRPbF IRF6795MPbF 0 4.99K 681 2.26K 23.7K 2.55K 4.12K 3.24K 130 4.02K 20 Label TP IR3640 Description SMT 0.075" Test Point Ceramic,25V,1210,X5R,10% Ceramic,50V,0603,X7R,10% Ceramic,4V,0805,X5R,10% Ceramic,25V,0603,X5R,10% Ceramic,25V,0603,C0G,5% Ceramic,50V,0603,C0G,5% Ceramic,50V,0603,C0G,5% SMD Elecrolytic, 25V,F-size,20% SMT-Inductor,1.5mOhms,10x11mm,20% IRF6710 SQ 25V IRF6795 MX 25V Thick-film,0603,1/10 W,5% Thick-film,0603,1/10W,1% Thick-film,0603,1/10 W,1% Thick-film,0603,1/10W,1% Thick-film,0603,1/10W,1% Thick-film,0603,1/10 W,1% Thick-film,0603,1/10 W,1% Thick-film,0603,1/10W,1% Thick-film,0603,1/10 W,1% Thick-film,0603,1/10 W,1% Thick-film,0603,1/10 W,1% 0.250" x 0.300" test pad area IR3640,Controller,MLPQ,3x4mm Manufacturer Part Number Taiyo-Yuden Panasonic Murata Electronics Murata Electronics Panasonic-ECG Murata Electronics TDK Corporation Panasonic Delta International Rectifier International Rectifier Vishay/Dale Rohm Vishey/Dale Rohm Rohm Rohm Rohm Rohm Rohm Rohm Vishey/Dale International Rectifier TMK325BJ106MN-T ECJ-1VB1H104K GRM21BR60G476ME15L GRM188R61E105KA12D C1608C0G1E562J GRM1885C1H161JA01D C1608C0G1H222J EEE-FK1E331P MPL104-R33IR IRF6710S2TRPbF IRF6795MPbF CRCW06030000Z0EA MCR03EZPFX4991 CRCW0603681RFKEA MCR03EZPFX2261 MCR03EZPFX2372 MCR03EZPFX2551 MCR03EZPFX4121 MCR03EZPFX3241 MCR03EZPFX1300 MCR03EZPFX4021 CRCW060320R0FKEA IR3640 8 IRDC3640 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=5V, Vo=1.8V, Io=0- 25A, Room Temperature, No Air Flow Fig. 9: Start up at 0A Load (Note 1) Ch1:Vo, Ch2:PGood Ch3:VSS Ch4: Vin Fig. 10: Start up at 25A Load (Note 1) Ch1:Vo, Ch2:PGood Ch3:VSS Ch4: Vin Fig. 11: Start up with 1.5V Prebias, 0A Load, Ch2:Vout Ch3:VSS Ch4: PGood Fig. 12: Output Voltage Ripple, 25A load Ch3: Vout Fig. 13: Inductor node at 25A load Ch2:SW Fig. 14: Short (Hiccup) Recovery Ch2:Vout, Ch3:VSS , Ch4:Io 9 IRDC3640 TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=1.8V, Room Temperature, No Air Flow Fig. 15: Transient Response 0A-12.5A load Ch2:Vout, Ch4:Io Note1: Enable is tied to Vin via a resistor divider and triggered when Vin is exceeding above 10V. 10 IRDC3640 TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=1.8V, Io=0-25A, Room Temperature, No Air Flow Fig.16: Bode Plot at 25A load shows a bandwidth of 113.6kHz and phase margin of 50.4 degrees 11 IRDC3640 TYPICAL OPERATING WAVEFORMS Vin=12V, Vo=1.8V, Io=0-25A, Room Temperature, No Air Flow IR3640_IRF6710_IRF6795_0.33uH Efficiency vs. Io 95 90 Efficiency(%) 85 80 75 70 1 3 5 7 9 11 13 Io(A) 15 17 19 21 23 25 IR3640_IRF6710_IRF6795_0.33uH Power Loss vs. Io 7 6 5 Ploss(W) 4 3 2 1 0 1 3 5 7 9 11 13 Io(A) 15 17 19 21 23 25 Fig.17: Efficiency and power loss vs. load current 12 IRDC3640 THERMAL IMAGES Vin=12V, Vo=1.8V, Io=25A, Room Temperature, No Air Flow 2 Fig.18: Thermal Image at 25A load Test Point 1: Ctrl FET IRF6710, Test Point 2: Sync FET IRF6795 Test Point 3: Inductor 13 IRDC3640 PCB Metal and Components Placement Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension +0.05mm inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. Center pad land length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be ≥ 0.17mm for 2 oz. Copper (≥ 0.1mm for 1 oz. Copper and ≥ 0.23mm for 3 oz. Copper). Four 0.30mm diameter via shall be placed in the center of the pad land and connected to ground to minimize the noise effect on the IC. IRDC3640 Solder Resist The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads. The minimum solder resist width is 0.13mm. At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of ≥ 0.17mm remains. The land pad should be Non Solder Mask Defined (NSMD), with a minimum pullback of the solder resist off the copper of 0.06mm to accommodate solder resist mis-alignment. Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. Each via in the land pad should be tented or plugged from bottom boardside with solder resist. IRDC3640 Stencil Design • The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mmpitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land. The land pad aperture should deposit approximately 50% area of solder on the center pad. If too much solder is deposited on the center pad the part will float and the lead lands will be open. The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. • • • IRDC3640 IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Consumer market. Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 11/07