IRF3707ZCLPBF

IRF3707ZCSPbF IRF3707ZCLPbF Applications l High Frequency Synchronous Buck Converters for Computer Processor Power l Lead-Free PD - 95464 HEXFET® Power MOSFET VDSS RDS(on) max 30V 9.5m: Qg 9.7nC Benefits l Low RDS(on) at 4.5V VGS l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage and Current D2Pak IRF3707ZCS TO-262 IRF3707ZCL Absolute Maximum Ratings Parameter VDS VGS ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C PD @TC = 100°C TJ TSTG Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Max. 30 ± 20 59 42 Units V A c h h 230 57 28 0.38 -55 to + 175 300 (1.6mm from case) 10 lbf in (1.1 N m) W/°C °C W Maximum Power Dissipation Maximum Power Dissipation Linear Derating Factor Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 screw x x Thermal Resistance Parameter RθJC RθJA Junction-to-Case Junction-to-Ambient (PCB Mount) Typ. Max. 2.653 40 Units °C/W g ––– ––– Notes  through † are on page 11 www.irf.com 1 6/29/04 IRF3707ZCS/LPbF Static @ TJ = 25°C (unless otherwise specified) Parameter BVDSS ∆ΒVDSS/∆TJ RDS(on) VGS(th) ∆VGS(th)/∆TJ IDSS IGSS gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw Qoss td(on) tr td(off) tf Ciss Coss Crss Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) Output Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. Typ. Max. Units 30 ––– ––– ––– 1.35 ––– ––– ––– ––– ––– 81 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 0.023 7.5 10 1.80 -5.3 ––– ––– ––– ––– ––– 9.7 2.8 1.0 3.4 2.5 4.4 6.2 9.8 41 12 3.6 1210 260 130 ––– ––– 9.5 12.5 2.25 ––– 1.0 150 100 -100 ––– 15 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– pF VGS = 0V VDS = 15V ns nC nC VDS = 15V VGS = 4.5V ID = 17A S nA V mV/°C µA V Conditions VGS = 0V, ID = 250µA mV/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 21A VGS = 4.5V, ID = 17A e e VDS = VGS, ID = 250µA VDS = 24V, VGS = 0V VDS = 24V, VGS = 0V, TJ = 125°C VGS = 20V VGS = -20V VDS = 15V, ID = 17A See Fig. 16 VDS = 16V, VGS = 0V VDD = 15V, VGS = 4.5V ID = 17A Clamped Inductive Load e ƒ = 1.0MHz Avalanche Characteristics EAS IAR EAR Parameter Single Pulse Avalanche Energy Avalanche Current Ù d Typ. ––– ––– ––– Max. 40 23 5.7 Units mJ A mJ Repetitive Avalanche Energy ™ ––– ––– ––– ––– ––– ––– ––– ––– 14 5.2 Diode Characteristics Parameter IS ISM VSD trr Qrr Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Min. Typ. Max. Units 59 h Conditions MOSFET symbol D A 230 1.0 21 7.8 V ns nC Ù showing the integral reverse G S p-n junction diode. TJ = 25°C, IS = 17A, VGS = 0V TJ = 25°C, IF = 17A, VDD = 15V di/dt = 100A/µs e e 2 www.irf.com IRF3707ZCS/LPbF 1000 TOP VGS 10V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V 3.0V 1000 TOP VGS 10V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V 3.0V ID, Drain-to-Source Current (A) 100 BOTTOM ID, Drain-to-Source Current (A) 100 BOTTOM 30V 10 10 3.0V 1 0.1 1 30µs PULSE WIDTH Tj = 25°C 10 1 0.1 1 30µs PULSE WIDTH Tj = 175°C 10 V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 1000 RDS(on) , Drain-to-Source On Resistance (Normalized) 2.0 ID, Drain-to-Source Current (Α) ID = 42A VGS = 10V 1.5 T J = 25°C 100 T J = 175°C 1.0 10.0 2 3 4 VDS = 10V 30µs PULSE WIDTH 5 6 7 8 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 VGS, Gate-to-Source Voltage (V) T J , Junction Temperature (°C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature www.irf.com 3 IRF3707ZCS/LPbF 100000 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd 6.0 ID= 17A VGS, Gate-to-Source Voltage (V) 5.0 4.0 3.0 2.0 1.0 0.0 10000 C, Capacitance(pF) VDS= 24V VDS= 15V 1000 Ciss Coss 100 Crss 10 1 10 100 0 2 4 6 8 10 12 VDS, Drain-to-Source Voltage (V) QG Total Gate Charge (nC) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 1000.00 1000 OPERATION IN THIS AREA LIMITED BY R DS(on) ISD, Reverse Drain Current (A) 100.00 T J = 175°C T J = 25°C 10.00 ID, Drain-to-Source Current (A) 100 10 100µsec 1.00 1msec 1 Tc = 25°C Tj = 175°C Single Pulse 0.1 0 1 10 100 1000 VDS, Drain-to-Source Voltage (V) 10msec 0.10 VGS = 0V 0.0 0.5 1.0 1.5 2.0 0.01 VSD, Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRF3707ZCS/LPbF 60 50 ID, Drain Current (A) 2.5 Limited By Package VGS(th) Gate threshold Voltage (V) 2.0 40 30 20 10 0 25 50 75 100 125 150 175 T C , Case Temperature (°C) 1.5 ID = 250µA 1.0 0.5 -75 -50 -25 0 25 50 75 100 125 150 175 200 T J , Temperature ( °C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Threshold Voltage vs. Temperature 10 Thermal Response ( Z thJC ) 1 D = 0.50 0.20 0.10 0.05 0.02 0.01 SINGLE PULSE ( THERMAL RESPONSE ) τJ τJ τ1 R1 R1 τ2 R2 R2 R3 R3 τ3 τC τ τ3 0.1 Ri (°C/W) τi (sec) 1.163 0.000257 1.073 0.419 0.001040 0.003089 τ1 τ2 0.01 Ci= τi/Ri Ci= τi/Ri Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.0001 0.001 0.01 0.1 0.001 1E-006 1E-005 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRF3707ZCS/LPbF 15V 175 EAS , Single Pulse Avalanche Energy (mJ) VDS L DRIVER 150 125 100 75 50 25 0 25 50 75 100 ID 4.5A 6.8A BOTTOM 23A TOP RG VGS 20V D.U.T IAS tp + V - DD A 0.01Ω Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp 125 150 175 Starting T J , Junction Temperature (°C) Fig 12c. Maximum Avalanche Energy vs. Drain Current I AS LD VDS Fig 12b. Unclamped Inductive Waveforms + VDD D.U.T VGS Pulse Width < 1µs Duty Factor < 0.1% Current Regulator Same Type as D.U.T. 50KΩ 12V .2µF .3µF Fig 14a. Switching Time Test Circuit D.U.T. + V - DS 90% VGS 3mA VDS IG ID 10% Current Sampling Resistors VGS td(on) tr td(off) tf Fig 13. Gate Charge Test Circuit Fig 14b. Switching Time Waveforms 6 www.irf.com IRF3707ZCS/LPbF D.U.T Driver Gate Drive + P.W. Period D= P.W. Period VGS=10V ƒ + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt ‚ - - „ +  RG • • • • dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD VDD + - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs Id Vds Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Waveform www.irf.com 7 IRF3707ZCS/LPbF Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; Synchronous FET The power loss equation for Q2 is approximated by; * P =P loss conduction + P drive + P output P = Irms × Rds(on) loss + (Qg × Vg × f ) ( 2 ) Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput This can be expanded and approximated by; ⎛Q ⎞ + ⎜ oss × Vin × f + (Qrr × Vin × f ) ⎠ ⎝2 *dissipated primarily in Q1. Ploss = (Irms × Rds(on ) ) 2 ⎛ ⎞⎛ Qgs 2 Qgd +⎜I× × Vin × f ⎟ + ⎜ I × × Vin × ig ig ⎝ ⎠⎝ + (Qg × Vg × f ) + ⎛ Qoss × Vin × f ⎞ ⎝2 ⎠ ⎞ f⎟ ⎠ This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by the power supply input buss voltage. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Qoss Characteristic 8 www.irf.com IRF3707ZCS/LPbF D2Pak Package Outline Dimensions are shown in millimeters (inches) D2Pak Part Marking Information (Lead-Free) T H IS IS AN IR F 5 3 0 S W IT H L OT COD E 8 0 24 AS S E M B L E D O N W W 0 2 , 2 0 0 0 IN T H E AS S E M B L Y L IN E "L " N ote: "P " in as s em bly line pos ition in dicates "L ead-F ree" IN T E R N AT IO N AL R E C T IF IE R L O GO AS S E M B L Y L O T CO D E P AR T N U M B E R F 530S D AT E C O D E Y E AR 0 = 2 0 0 0 WE E K 02 L IN E L OR IN T E R N AT IO N AL R E C T IF IE R L OGO AS S E M B L Y L O T COD E P AR T N U M B E R F 530S D AT E C O D E P = D E S IG N AT E S L E AD -F R E E P R O D U CT (O P T IO N AL ) Y E AR 0 = 2 0 0 0 WE E K 02 A = AS S E M B L Y S IT E C O D E www.irf.com 9 IRF3707ZCS/LPbF TO-262 Package Outline IGBT 1- GATE 2- COLLECTOR 3- EMITTER TO-262 Part Marking Information EXAMPLE: T HIS IS AN IRL3103L LOT CODE 1789 AS S EMBLED ON WW 19, 1997 IN THE AS S EMBLY LINE "C" Note: "P" in ass embly line pos ition indicates "Lead-Free" INTERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER DAT E CODE YEAR 7 = 1997 WEEK 19 LINE C OR INTERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER DAT E CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) YEAR 7 = 1997 WEEK 19 A = AS S EMBLY S IT E CODE 10 www.irf.com IRF3707ZCS/LPbF D2Pak Tape & Reel Infomation Dimensions are shown in millimeters (inches) TRR 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135) FEED DIRECTION 1.85 (.073) 1.65 (.065) 11.60 (.457) 11.40 (.449) 15.42 (.609) 15.22 (.601) 24.30 (.957) 23.90 (.941) TRL 10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 16.10 (.634) 15.90 (.626) 4.72 (.136) 4.52 (.178) FEED DIRECTION 13.50 (.532) 12.80 (.504) 27.40 (1.079) 23.90 (.941) 4 330.00 (14.173) MAX. 60.00 (2.362) MIN. NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. 26.40 (1.039) 24.40 (.961) 3 30.40 (1.197) MAX. 4 Notes:  Repetitive rating; pulse width limited by … This is applied to D2Pak, when mounted on 1" square PCB (FR4 or G-10 Material). For recommended footprint and soldering max. junction temperature. techniques refer to application note #AN-994. ‚ Starting TJ = 25°C, L = 0.15mH, RG = 25Ω, † Calculated continuous current based on maximum allowable IAS = 23A. junction temperature. Package limitation current is 42A. ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%. „ Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 6/04 www.irf.com 11