IRF6665

PD - 96900 DIGITAL AUDIO MOSFET IRF6665 Key Parameters 100 53 8.7 1.9 V m: nC Features • Latest MOSFET Silicon technology • Key parameters optimized for Class-D audio amplifier applications • Low RDS(on) for improved efficiency • Low Qg for better THD and improved efficiency • Low Qrr for better THD and lower EMI • Low package stray inductance for reduced ringing and lower EMI • Can deliver up to 100W per channel into 8 Ω with no heatsink Š • Dual sided cooling compatible · Compatible with existing surface mount technologies · Lead and Bromide Free Applicable DirectFET Outline and Substrate Outline (see p. 6, 7 for details) VDS RDS(on) typ. @ VGS = 10V Qg typ. RG(int) typ. SH ST SH MQ MX MT MN DirectFET™ ISOMETRIC SQ SX Description This Digital Audio MOSFET is specifically designed for Class-D audio amplifier applications. This MOSFET utilizes the latest processing techniques to achieve low on-resistance per silicon area. Furthermore, gate charge, body-diode reverse recovery and internal gate resistance are optimized to improve key Class-D audio amplifier performance factors such as efficiency, THD, and EMI. The IRF6665 device utilizes DirectFET TM packaging technology. DirectFET TM packaging technology offers lower parasitic inductance and resistance when compared to conventional wirebonded SOIC packaging. Lower inductance improves EMI performance by reducing the voltage ringing that accompanies fast current transients. The DirectFET TM package is compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering techniques, when application note AN-1035 is followed regarding the manufacturing method and processes. The DirectFET TM package also allows dual sided cooling to maximize thermal transfer in power systems, improving thermal resistance and power dissipation. These features combine to make this MOSFET a highly efficient, robust and reliable device for Class-D audio amplifier applications. Absolute Maximum Ratings Parameter VDS VGS ID @ TC = 25°C ID @ TA = 25°C ID @ TA = 70°C IDM PD @TC = 25°C PD @TA = 25°C PD @TA = 70°C TJ TSTG Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Maximum Power Dissipation Max. 100 ± 20 19 4.2 3.4 34 42 2.2 1.4 0.017 -40 to + 150 Units V A c e Power Dissipation e Power Dissipation W Linear Derating Factor Operating Junction and Storage Temperature Range W/°C °C Thermal Resistance RθJA RθJA RθJA RθJC RθJ-PCB ek Junction-to-Ambient hk Junction-to-Ambient ik Junction-to-Case jk Junction-to-Ambient Parameter Typ. ––– 12.5 20 ––– 1.4 Max. 58 ––– ––– 3.0 ––– Units °C/W Junction-to-PCB Mounted Notes  through Š are on page 2 www.irf.com 1 10/11/04 IRF6665 Static @ TJ = 25°C (unless otherwise specified) Parameter V(BR)DSS ∆V(BR)DSS/∆TJ RDS(on) VGS(th) IDSS IGSS RG(int) Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance Min. 100 ––– ––– 3.0 ––– ––– ––– ––– ––– Typ. ––– 0.12 53 ––– ––– ––– ––– ––– 1.9 Max. ––– ––– 62 5.0 20 250 100 -100 2.9 Units V V/°C mΩ V µA nA Ω Conditions VGS = 0V, ID = 250µA Reference to 25°C, ID = 1mA VGS = 10V, ID = 5.0A VDS = VGS, ID = 250µA VDS = 100V, VGS = 0V VDS = 80V, VGS = 0V, TJ = 125°C VGS = 20V VGS = -20V f Dynamic @ TJ = 25°C (unless otherwise specified) Parameter gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw td(on) tr td(off) tf Ciss Coss Crss Coss Coss Coss eff. Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance Parameter EAS IAR Single Pulse Avalanche Energy Avalanche Current Min. 6.6 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– Typ. ––– 8.7 2.1 0.58 2.8 3.2 3.38 7.4 2.8 14 4.3 530 110 29 510 67 130 Max. ––– 11.7 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– Typ. ––– ––– Units S VDS = 50V VGS = 10V ID = 5.0A nC Conditions VDS = 10V, ID = 5.0A See Fig.6 and 16 VDD = 50V ID = 5.0A ns RG = 6.0Ω VGS = 10V VGS = 0V VDS = 25V pF ƒ = 1.0MHz VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz VGS = 0V, VDS = 80V, ƒ = 1.0MHz VGS = 0V, VDS = 0V to 80V Max. 11 5.0 f g Avalanche Characteristics Ù d Min. ––– ––– ––– ––– ––– Units mJ A Diode Characteristics Parameter IS ISM VSD trr Qrr Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Typ. ––– ––– ––– 31 37 Max. 4.2 Units A Conditions MOSFET symbol showing the integral reverse p-n junction diode. G S D Ù 34 1.3 ––– ––– V ns nC TJ = 25°C, IS = 5.0A, VGS = 0V TJ = 25°C, IF = 5.0A, VDD = 25V di/dt = 100A/µs f f Notes:  Repetitive rating; pulse width limited by max. junction temperature. ‚ Starting TJ = 25°C, L = 0.89mH, RG = 25Ω, IAS = 5.0A. ƒ Surface mounted on 1 in. square Cu board. „ Pulse width ≤ 400µs; duty cycle ≤ 2%. … Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. † Used double sided cooling , mounting pad. ‡ Mounted on minimum footprint full size board with metalized back and with small clip heatsink. (Drain) of part. ˆ TC measured with thermal couple mounted to top ‰ Rθ is measured at TJ of approximately 90°C. Š Based on testing done using a typical device & evaluation board at Vbus=±45V, fSW=400KHz, and TA=25°C. The delta case temperature ∆TC is 55°C. 2 www.irf.com IRF6665 100 TOP VGS 15V 10V 9.0V 8.0V 7.0V 6.0V 100 TOP VGS 15V 10V 9.0V 8.0V 7.0V 6.0V ID, Drain-to-Source Current (A) 10 BOTTOM ID, Drain-to-Source Current (A) 10 6.0V BOTTOM 6.0V 1 1 ≤60µs PULSE WIDTH Tj = 25°C 0.1 0.1 1 10 100 1000 V DS, Drain-to-Source Voltage (V) 0.1 0.1 1 ≤60µs PULSE WIDTH Tj = 150°C 10 100 1000 V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics 100 Fig 2. Typical Output Characteristics 2.0 RDS(on) , Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (Α) ID = 5.0A VGS = 10V 10 1.5 T J = -40°C T J = 25°C 1 T J = 150°C VDS = 25V ≤60µs PULSE WIDTH 0.1 2 4 6 8 10 12 1.0 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 T J , Junction Temperature (°C) VGS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics 10000 Fig 4. Normalized On-Resistance vs. Temperature 12.0 ID= 5.0A VGS, Gate-to-Source Voltage (V) VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd 10.0 8.0 6.0 4.0 2.0 0.0 C, Capacitance(pF) VDS= 80V VDS= 50V VDS= 20V 1000 Ciss Coss 100 Crss 10 1 10 VDS, Drain-to-Source Voltage (V) 100 0 2 4 6 8 10 Fig 5. Typical Capacitance vs.Drain-to-Source Voltage Fig 6. Typical Gate Charge vs.Gate-to-Source Voltage QG Total Gate Charge (nC) www.irf.com 3 IRF6665 100 1000 Tc = 25°C Tj = 150°C Single Pulse OPERATION IN THIS AREA LIMITED BY R DS(on) ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 100 10 100µsec 10 T J = -40°C T J = 25°C T J = 150°C VGS = 0V 1 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VSD, Source-to-Drain Voltage (V) 1 DC 1msec 10msec 0.1 0.01 0 1 10 100 1000 VDS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 5 VGS(th) Gate threshold Voltage (V) 5.5 Fig 8. Maximum Safe Operating Area 4 ID, Drain Current (A) 5.0 4.5 3 4.0 2 3.5 ID = 250µA ID = 1.0A 1 3.0 ID = 1.0mA 0 25 50 75 100 125 150 T C , Case Temperature (°C) 2.5 -75 -50 -25 0 25 50 75 100 125 150 T J , Temperature ( °C ) Fig 9. Maximum Drain Current vs. Case Temperature 100 Fig 10. Threshold Voltage vs. Temperature D = 0.50 Thermal Response ( Z thJA ) 10 0.20 0.10 0.05 1 0.02 0.01 τJ R1 R1 τJ τ1 τ2 R2 R2 R3 R3 τ3 R4 R4 τ4 R5 R5 τC τ τ5 Ri (°C/W) 1.6195 2.1406 22.2887 20.0457 11.9144 τi (sec) 0.000126 0.001354 0.375850 7.410000 99 τ1 τ2 τ3 τ4 τ5 Ci= τi/Ri Ci= τi/Ri 0.1 SINGLE PULSE ( THERMAL RESPONSE ) Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthja + Tc 0.01 0.1 1 10 100 0.01 1E-006 1E-005 0.0001 0.001 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient ƒ 4 www.irf.com IRF6665 RDS(on) , Drain-to -Source On Resistance ( mΩ) 200 180 160 140 120 100 80 60 40 20 0 4 6 8 10 12 14 16 18 T J = 25°C T J = 125°C ID = 5.0A RDS(on), Drain-to -Source On Resistance ( mΩ) 120 100 T J = 125°C 80 60 T J = 25°C Vgs = 10V 40 0 2 4 6 8 10 ID, Drain Current (A) VGS, Gate -to -Source Voltage (V) Fig 12. On-Resistance vs. Gate Voltage Fig 13. On-Resistance vs. Drain Current 15V 50 EAS , Single Pulse Avalanche Energy (mJ) VDS L DRIVER 40 ID TOP 0.86A 1.3A BOTTOM 5.0A RG VGS 20V D.U.T IAS tp + V - DD 30 A 0.01Ω 20 Fig 14a. Unclamped Inductive Test Circuit V(BR)DSS tp 10 0 25 50 75 100 125 150 Starting T J , Junction Temperature (°C) Fig 14c. Maximum Avalanche Energy vs. Drain Current I AS Fig 14b. Unclamped Inductive Waveforms VDS VGS RG RD D.U.T. + 90% - VDD VDS 10% 10V Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % VGS td(on) tr td(off) tf www.irf.com Fig 15a. Switching Time Test Circuit Fig 15b. Switching Time Waveforms 5 IRF6665 Current Regulator Same Type as D.U.T. Id Vds Vgs 50KΩ 12V .2µF .3µF D.U.T. VGS 3mA + V - DS Vgs(th) IG ID Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr Fig 16a. Gate Charge Test Circuit D.U.T Fig 16b. Gate Charge Waveform Driver Gate Drive P.W. Period D= P.W. Period VGS=10V + ƒ + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt ‚ - - „ +  RG • • • • di/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD VDD + - Re-Applied Voltage Body Diode Forward Drop Inductor Curent Inductor Current Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 17. Diode Reverse Recovery Test Circuit for N-Channel HEXFET® Power MOSFETs DirectFET™ Substrate and PCB Layout, SH Outline (Small Size Can, H-Designation). Please see DirectFET application note AN-1035 for all details regarding PCB assembly using DirectFET. This includes all recommendations for stencil and substrate designs. 1- Drain 2- Drain 3- Gate 4- Source 5- Drain 6- Drain 1 3 2 4 5 6 6 www.irf.com IRF6665 DirectFET™ Outline Dimension, SH Outline (Small Size Can, H-Designation). Please see DirectFET application note AN-1035 for all details regarding PCB assembly using DirectFET. This includes all recommendations for stencil and substrate designs. Note: Controlling dimensions are in mm. DIMENSIONS IMPERIAL METRIC MAX MIN CODE MIN ÃMAX 4.85 0.187 A 0.191 4.75 3.95 0.146 B 3.70 0.156 2.85 0.108 C 2.75 0.112 0.45 0.014 D 0.35 0.018 0.62 0.023 E 0.58 0.024 0.62 0.023 F 0.024 0.58 0.67 0.025 G 0.026 0.63 0.87 0.033 H 0.83 0.034 K 0.99 1.03 0.039 0.041 2.33 0.090 L 0.092 2.29 0.58 0.019 M 0.023 0.48 0.08 0.001 N 0.003 0.03 0.17 0.003 P 0.08 0.007 DirectFET™ Part Marking www.irf.com 7 IRF6665 DirectFET™ Tape & Reel Dimension (Showing component orientation). NOTE: Controlling dimensions in mm Std reel quantity is 4800 parts. (ordered as IRF6665). For 1000 parts on 7" reel, order IRF6665TR1 REEL DIMENSIONS TR1 OPTION (QTY 1000) STANDARD OPTION (QTY 4800) IMPERIAL IMPERIAL METRIC METRIC CODE MIN MIN MAX MAX MIN MIN MAX MAX 12.992 6.9 A N.C N.C 330.0 177.77 N.C N.C B 0.795 0.75 N.C 20.2 19.06 N.C N.C N.C 0.504 0.53 C 0.50 0.520 12.8 13.5 12.8 13.2 D 0.059 0.059 N.C 1.5 1.5 N.C N.C N.C E 3.937 2.31 N.C 100.0 58.72 N.C N.C N.C F N.C N.C 0.53 N.C N.C 0.724 13.50 18.4 G 0.488 0.47 12.4 11.9 N.C 0.567 12.01 14.4 H 0.469 0.47 11.9 11.9 N.C 0.606 12.01 15.4 Loaded Tape Feed Direction NOTE: CONTROLLING DIMENSIONS IN MM CODE A B C D E F G H DIMENSIONS IMPERIAL METRIC MIN MAX MAX MIN 0.311 0.319 8.10 7.90 0.154 0.161 4.10 3.90 0.469 0.484 12.30 11.90 0.215 0.219 5.45 5.55 0.201 0.209 5.10 5.30 0.256 0.264 6.50 6.70 0.059 N.C 1.50 N.C 0.059 1.50 1.60 0.063 Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.09/04 8 www.irf.com