PD - 96104
IRF7304QPbF
HEXFET® Power MOSFET
l l l l l l l l
Advanced Process Technology Ultra Low On-Resistance Dual P Channel MOSFET Surface Mount Available in Tape & Reel 150°C Operating Temperature Automotive [Q101] Qualified Lead-Free
S1 G1 S2 G2
1 2 3 4
8 7
D1 D1 D2 D2
VDSS = -20V RDS(on) = 0.090Ω
6 5
Top View
Description
Specifically designed for Automotive applications, these HEXFET® Power MOSFET's in a Dual SO-8 package utilize the lastest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of these Automotive qualified HEXFET Power MOSFET's are a 150°C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These benefits combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications. The efficient SO-8 package provides enhanced thermal characteristics and dual MOSFET die capability making it ideal in a variety of power applications. This dual, surface mount SO-8 can dramatically reduce board space and is also available in Tape & Reel.
SO-8
Absolute Maximum Ratings
Parameter
I D @ TA = 25°C I D @ TA = 25°C ID @ TA = 70°C IDM PD @TA = 25°C VGS dv/dt TJ, TSTG 10 Sec. Pulsed Drain Current, VGS @ -4.5V Continuous Drain Current, VGS @ -4.5V Continuous Drain Current, VGS @ -4.5V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt Junction and Storage Temperature Range
Max.
-4.7 -4.3 -3.4 -17 2.0 0.016 ±12 -5.0 -55 to + 150
Units
A W W/°C V V/ns °C
Thermal Resistance Ratings
Parameter
RθJA Maximum Junction-to-Ambient
Typ.
Max.
62.5
Units
°C/W
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1
07/23/07
IRF7304QPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Drain-to-Source Breakdown Voltage ∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient V(BR)DSS RDS(ON) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. Typ. Max. Units Conditions -20 V VGS = 0V, ID = -250µA -0.012 V/°C Reference to 25°C, ID = -1mA 0.090 VGS = -4.5V, ID = -2.2A Ω 0.140 VGS = -2.7V, ID = -1.8A -0.70 V VDS = VGS, ID = -250µA 4.0 S VDS = -16V, ID = -2.2A -1.0 VDS = -16V, VGS = 0V µA -25 VDS = -16V, VGS = 0V, TJ = 125°C -100 VGS = -12V nA 100 VGS = 12V 22 ID = -2.2A 3.3 nC VDS = -16V 9.0 VGS = -4.5V, See Fig. 6 and 12 8.4 VDD = -10V 26 ID = -2.2A ns 51 RG = 6.0Ω 33 RD = 4.5Ω, See Fig. 10 4.0 6.0 610 310 170 nH pF
D
Between lead tip and center of die contact VGS = 0V VDS = -15V = 1.0MHz, See Fig. 5
G S
Source-Drain Ratings and Characteristics
IS
I SM
VSD trr Qrr ton
P arameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
Min. Typ. Max. Units 56 71 -2.5 A -17 -1.0 84 110 V ns nC
Conditions D MOSFET symbol showing the G integral reverse p-n junction diode. S TJ = 25°C, IS = -1.8A, VGS = 0V TJ = 25°C, IF = -2.2A di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Pulse width ≤ 300µs; duty cycle ≤ 2%.
ISD ≤ -2.2A, di/dt ≤− 50A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C
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IRF7304QPbF
100
-I D , Drain-to-Source Current (A)
10
-ID , Drain-to-Source Current (A)
VGS - 7.5V - 5.0V - 4.0V - 3.5V - 3.0V - 2.5V - 2.0V BOTTOM - 1.5V TOP
100
VGS - 7.5V - 5.0V - 4.0V - 3.5V - 3.0V - 2.5V - 2.0V BOTTOM - 1.5V TOP
10
1
1
-1.5V
-1.5V 20µs PULSE WIDTH TJ = 25°C A
0.1 1 10 100
0.1 0.01
0.1 0.01
20µs PULSE WIDTH TJ = 150°C
0.1 1 10
100
A
-VDS , Drain-to-Source Voltage (V)
-VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
2.0
R DS(on) , Drain-to-Source On Resistance (Normalized)
I D = -3.6A
-ID , Drain-to-Source Current (A)
TJ = 25°C
10
TJ = 150°C
1.5
1.0
1
0.5
0.1 1.5 2.0 2.5 3.0
VDS = -15V 20µs PULSE WIDTH
3.5 4.0 4.5 5.0
A
0.0 -60 -40 -20 0 20 40 60 80
VGS = -4.5V
100 120 140 160
A
-VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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IRF7304QPbF
1500
-VGS , Gate-to-Source Voltage (V)
V GS = 0V, f = 1MHz C iss = Cgs + C gd , Cds SHORTED C rss = C gd C oss = C ds + C gd
10
I D = -2.2A VDS = -16V
8
C, Capacitance (pF)
Ciss
1000
Coss Crss
500
6
4
2
0 1 10 100
A
0 0 5 10
FOR TEST CIRCUIT SEE FIGURE 12
15 20 25
A
-VDS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
100
100
-ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY RDS(on)
10
TJ = 150°C TJ = 25°C
-ID , Drain Current (A) I
10 1ms
1
0.1 0.3 0.6 0.9 1.2
VGS = 0V
A
1.5
1
TA = 25 °C TJ = 150 °C Single Pulse
1 10
10ms
100
-VSD , Source-to-Drain Voltage (V)
-VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
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IRF7304QPbF
V DS
5.0
RD
V GS RG
D.U.T.
+
4.0
-ID , Drain Current (A)
-4.5 V
Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %
3.0
Fig 10a. Switching Time Test Circuit
2.0
VDS 90%
1.0
0.0
25
50
TC , Case Temperature ( °C)
75
100
125
150
10% VGS
td(on) tr t d(off) tf
Fig 9. Maximum Drain Current Vs. Ambient Temperature
Fig 10b. Switching Time Waveforms
100
Thermal Response (Z thJA )
D = 0.50 0.20 10 0.10 0.05 0.02 1 0.01 SINGLE PULSE (THERMAL RESPONSE) PDM t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJA + TA 0.001 0.01 0.1 1 10 100
0.1 0.0001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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-
V DD
5
IRF7304QPbF
Current Regulator Same Type as D.U.T.
50KΩ
QG
12V
.2µF
.3µF
QGS
QGD
VGS
-3mA
VG
IG
ID
Charge
Current Sampling Resistors
Fig 12a. Basic Gate Charge Waveform
Fig 12b. Gate Charge Test Circuit
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+
-4.5 V
D.U.T.
-
VDS
6
IRF7304QPbF
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer
-
+
RG VGS*
**
• dv/dt controlled by R G • ISD controlled by Duty Factor "D" • D.U.T. - Device Under Test
+ -
V DD
*
*
Reverse Polarity for P-Channel ** Use P-Channel Driver for P-Channel Measurements
Driver Gate Drive P.W. Period D=
P.W. Period
[VGS=10V ] ***
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
[VDD]
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple ≤ 5%
[ ISD ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices Fig 13. For P-Channel HEXFETS
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IRF7304QPbF
SO-8 Package Outline
Dimensions are shown in millimeters (inches)
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8
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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IRF7304QPbF
SO-8 Tape and Reel
Dimensions are shown in millimeters (inches)
TERMINAL NUMBER 1
12.3 ( .484 ) 11.7 ( .461 )
8.1 ( .318 ) 7.9 ( .312 )
FEED DIRECTION
NOTES: 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
330.00 (12.992) MAX.
14.40 ( .566 ) 12.40 ( .488 ) NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q101] market. Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.07/2007
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