IRF7831UPBF

PD - 96083A IRF7831UPbF HEXFET® Power MOSFET Applications l High Frequency Point-of-Load Synchronous Buck Converter for Applications in Networking & Computing Systems. Benefits l Very Low RDS(on) at 4.5V VGS l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage and Current l 100% Tested for R G l Lead-Free VDSS RDS(on) max 30V 3.6m @VGS = 10V : Qg (typ.) 40nC S S S G 1 2 3 4 8 7 A A D D D D 6 5 Top View SO-8 Absolute Maximum Ratings Parameter VDS VGS ID @ TA = 25°C ID @ TA = 70°C IDM PD @TA = 25°C PD @TA = 70°C TJ TSTG Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Power Dissipation Max. 30 ± 12 21 17 170 2.5 1.6 0.02 -55 to + 150 Units V f f c A W W/°C °C Linear Derating Factor Operating Junction and Storage Temperature Range Thermal Resistance Parameter RθJL RθJA Junction-to-Drain Lead Junction-to-Ambient Typ. ––– ––– Max. 20 50 Units °C/W f Notes  through „ are on page 10 www.irf.com 09/19/06 1 IRF7831UPbF Static @ TJ = 25°C (unless otherwise specified) Parameter BVDSS ∆Β VDSS/∆T J RDS(on) V GS(th) ∆V GS(th) IDSS IGSS gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw Qoss RG td(on) tr td(off) tf Ciss Coss Crss Drain-to-Source Breakdown Voltage B reakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) Output Charge Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. Typ. Max. Units 30 ––– 2.5 3.0 1.35 ––– ––– ––– ––– ––– 97 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 0.025 3.1 3.7 ––– - 5.7 ––– ––– ––– ––– ––– 40 12 3.1 11 14 14 22 1.4 18 10 17 5.3 6240 980 390 ––– ––– 3.6 4.4 2.35 ––– 1.0 150 100 -100 ––– 60 ––– ––– ––– ––– ––– ––– 2.5 ––– ––– ––– ––– ––– ––– ––– pF VGS = 0 V VDS = 15V ns nC Ω nC VDS = 15V VGS = 4.5V ID = 16A S nA V mV/°C µA V mΩ Conditions VGS = 0 V, ID = 250µA VGS = 1 0V, ID = 20A VGS = 4.5V, ID = 1 6A V/°C Reference to 25°C, ID = 1 mA e e VDS = VGS, ID = 250µA VDS = 24V, V GS = 0V VDS = 24V, V GS = 0V, TJ = 125°C VGS = 1 2V VGS = -12V VDS = 15V, ID = 1 6A See Fig. 16 VDS = 16V, V GS = 0V VDD = 15V, V GS = 4.5V ID = 16A Clamped Inductive Load e ƒ = 1.0MHz Avalanche Characteristics E AS IAR Parameter Single Pulse Avalanche Energy Avalanche Current ™ d Typ. ––– ––– Max. 100 16 Units mJ A Diode Characteristics Parameter IS ISM V SD trr Qrr ton Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time Min. Typ. Max. Units ––– ––– ––– ––– ––– ––– ––– ––– 42 31 2.5 A 170 1.2 62 47 V ns nC Conditions MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25°C, IS = 1 6A, VGS = 0V TJ = 25°C, IF = 16A, V DD = 2 5V di/dt = 100A/µs Ù e e Intrinsic turn-on time is negligible (turn-on is dominated by LS+L D) 2 www.irf.com IRF7831UPbF 1000 VGS 10V 5.0V 4.5V 3.5V 3.0V 2.7V 2.5V BOTTOM 2.25V TOP 1000 ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) 100 100 10 VGS 10V 5.0V 4.5V 3.5V 3.0V 2.7V 2.5V BOTTOM 2.25V TOP 10 1 2.25V 1 0.1 0.01 0.1 1 20µs PULSE WIDTH 2.25V Tj = 25°C 0.1 10 100 0.1 1 20µs PULSE WIDTH Tj = 150°C 10 100 VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 1000.0 2.0 100.0 RDS(on) , Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (Α) ID = 20A VGS = 10V 1.5 T J = 150°C 10.0 1.0 1.0 T J = 25°C VDS = 15V 20µs PULSE WIDTH 2.0 2.5 3.0 3.5 4.0 0.1 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 VGS, Gate-to-Source Voltage (V) T J , Junction Temperature (°C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3 IRF7831UPbF 100000 VGS, Gate-to-Source Voltage (V) VGS = 0V, f = 1 MHZ C iss = C gs + Cgd, C ds SHORTED C rss = C gd C oss = C ds + Cgd 12 ID= 12A 10 8 6 4 2 0 VDS= 24V VDS= 15V C, Capacitance (pF) 10000 Ciss 1000 Coss Crss 100 1 10 100 0 20 40 60 80 100 VDS, Drain-to-Source Voltage (V) QG Total Gate Charge (nC) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 1000.0 1000 OPERATION IN THIS AREA LIMITED BY R DS(on) 100.0 T J = 150°C 10.0 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 100 100µsec 10 1msec Tc = 25°C Tj = 150°C Single Pulse 0.1 1.0 10.0 1.0 T J = 25°C VGS = 0V 0.1 0.2 0.4 0.6 0.8 1.0 1.2 VSD, Source-toDrain Voltage (V) 1 10msec 100.0 1000.0 VDS , Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRF7831UPbF 24 2.4 VGS(th) Gate threshold Voltage (V) 20 2.2 2.0 1.8 1.6 1.4 1.2 1.0 ID , Drain Current (A) 16 ID = 250µA 12 8 4 0 25 50 75 100 125 150 -75 -50 -25 0 25 50 75 100 125 150 T J , Junction Temperature (°C) T J , Temperature ( °C ) Fig 9. Maximum Drain Current Vs. Case Temperature Fig 10. Threshold Voltage Vs. Temperature 100 Thermal Response ( Z thJA ) 10 D = 0.50 0.20 0.10 0.05 1 0.02 0.01 τJ τJ τ1 R1 R1 τ2 R2 R2 R3 R3 τ3 R4 R4 τ4 R5 R5 τC τ5 Ri (°C/W) τi (sec) 0.1 τ1 τ2 τ3 τ4 τ5 0.01 Ci= τi /Ri C 0.514 2.445 20.64 17.80 8.604 0.000182 0.030949 0.36354 6.99 109 SINGLE PULSE ( THERMAL RESPONSE ) Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthja + Tc 0.1 1 10 100 0.001 1E-006 1E-005 0.0001 0.001 0.01 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient www.irf.com 5 IRF7831UPbF EAS, Single Pulse Avalanche Energy (mJ) 15V 500 VDS L DRIVER 400 ID 11A 13A BOTTOM 16A TOP RG VGS 20V D.U.T IAS tp + V - DD 300 A 0.01Ω 200 Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp 100 0 25 50 75 100 125 150 Starting T J, Junction Temperature (°C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS LD VDS Fig 12b. Unclamped Inductive Waveforms + VDD D.U.T Current Regulator Same Type as D.U.T. VGS Pulse Width < 1µs Duty Factor < 0.1% 50KΩ 12V .2µF .3µF Fig 14a. Switching Time Test Circuit D.U.T. + V - DS 90% VDS VGS 3mA 10% IG ID VGS td(on) tr td(off) tf Current Sampling Resistors Fig 13. Gate Charge Test Circuit Fig 14b. Switching Time Waveforms 6 www.irf.com IRF7831UPbF D.U.T Driver Gate Drive + P.W. Period D= P.W. Period VGS=10V ƒ + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt ‚ - - „ +  RG • • • • dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD VDD + - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs Id Vds Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Waveform www.irf.com 7 IRF7831UPbF Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; Synchronous FET The power loss equation for Q2 is approximated by; * Ploss = Pconduction + P + Poutput drive Ploss = Irms × Rds(on) + ( g × Vg × f ) Q ( 2 ) Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput This can be expanded and approximated by; ⎛Q ⎞ + ⎜ oss × Vin × f + (Qrr × Vin × f ) ⎝2 ⎠ *dissipated primarily in Q1. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Ploss = (Irms 2 × Rds(on ) ) ⎛ Qgs 2 Qgd ⎞⎛ ⎞ +⎜I × × Vin × f ⎟ + ⎜ I × × Vin × f ⎟ ig ig ⎝ ⎠⎝ ⎠ + (Qg × Vg × f ) + ⎛ Qoss × Vin × f ⎞ ⎝2 ⎠ This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by the power supply input buss voltage. 8 Figure A: Qoss Characteristic www.irf.com IRF7831UPbF SO-8 Package Outline Dimensions are shown in millimeters (inches) D A 5 B DIM A b INCHES MIN .0532 .013 .0075 .189 .1497 MAX .0688 .0098 .020 .0098 .1968 .1574 MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 A1 .0040 6 E 8 7 6 5 H 0.25 [.010] A c D E e e1 H 1 2 3 4 .050 BASIC .025 BASIC .2284 .0099 .016 0° .2440 .0196 .050 8° 1.27 BASIC 0.635 BASIC 5.80 0.25 0.40 0° 6.20 0.50 1.27 8° 6X e K L y e1 A K x 45° C 0.10 [.004] y 8X c 8X b 0.25 [.010] A1 CAB 8X L 7 NOT ES : 1. DIMENS IONING & TOLERANCING PER ASME Y14.5M-1994. 2. CONT ROLLING DIMENS ION: MILLIMET ER 3. DIMENS IONS ARE SHOWN IN MILLIMETERS [INCHES]. 4. OUTLINE CONFORMS TO JEDEC OUTLINE MS -012AA. 5 DIMENS ION DOES NOT INCLUDE MOLD PROT RUSIONS . MOLD PROTRUS IONS NOT TO EXCEED 0.15 [.006]. 6 DIMENS ION DOES NOT INCLUDE MOLD PROT RUSIONS . MOLD PROTRUS IONS NOT TO EXCEED 0.25 [.010]. 7 DIMENS ION IS T HE LENGT H OF LEAD FOR SOLDERING TO A S UBST RAT E. 3X 1.27 [.050] 6.46 [.255] F OOTPRINT 8X 0.72 [.028] 8X 1.78 [.070] SO-8 Part Marking www.irf.com 9 IRF7831UPbF SO-8 Tape and Reel Dimensions are shown in milimeters (inches) TERMINAL NUMBER 1 12.3 ( .484 ) 11.7 ( .461 ) 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES: 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 330.00 (12.992) MAX. 14.40 ( .566 ) 12.40 ( .488 ) NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. OUTLINE CONFORMS TO EIA-481 & EIA-541. Notes:  Repetitive rating; pulse width limited by max. junction temperature. ‚ Starting TJ = 25°C, L = 0.76mH RG = 25Ω, IAS = 16A. ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%. „ When mounted on 1 inch square copper board Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualifications Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 09/2006 10 www.irf.com