IRF9530NS

PD - 91523A IRF9530NS/L HEXFET® Power MOSFET Advanced Process Technology Surface Mount (IRF9530NS) l Low-profile through-hole (IRF9530NL) l 175°C Operating Temperature l Fast Switching l P-Channel l Fully Avalanche Rated Description l l D VDSS = -100V RDS(on) = 0.20Ω G ID = -14A S Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The D2Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible onresistance in any existing surface mount package. The D2Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRF9530NL) is available for lowprofile applications. D 2 P ak T O -26 2 Absolute Maximum Ratings Parameter ID @ TC = 25°C ID @ TC = 100°C IDM PD @TA = 25°C PD @TC = 25°C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ -10V… Continuous Drain Current, VGS @ -10V… Pulsed Drain Current  … Power Dissipation Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy‚… Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt ƒ … Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Max. -14 -10 -56 3.8 79 0.53 ± 20 250 -8.4 7.9 -5.0 -55 to + 175 300 (1.6mm from case ) Units A W W W/°C V mJ A mJ V/ns °C Thermal Resistance Parameter RθJC RθJA Junction-to-Case Junction-to-Ambient ( PCB Mounted,steady-state)** Typ. ––– ––– Max. 1.9 40 Units °C/W 5/13/98 IRF9530NS/L Electrical Characteristics @ TJ = 25°C (unless otherwise specified) Parameter Drain-to-Source Breakdown Voltage ∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) Gate Threshold Voltage gfs Forward Transconductance V(BR)DSS IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LS Ciss Coss Crss Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. -100 ––– ––– -2.0 3.2 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– Typ. ––– -0.11 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 15 58 45 46 7.5 760 260 170 Max. Units Conditions ––– V VGS = 0V, ID = -250µA ––– V/°C Reference to 25°C, ID = -1mA … 0.20 Ω VGS = -10V, ID = -8.4A „ -4.0 V VDS = VGS, ID = -250µA ––– S VDS = -50V, ID = -8.4A… -25 VDS = -100V, VGS = 0V µA -250 VDS = -80V, VGS = 0V, TJ = 150°C 100 VGS = 20V nA -100 VGS = -20V 58 ID = -8.4A 8.3 nC VDS = -80V 32 VGS = -10V, See Fig. 6 and 13 „ … ––– VDD = -50V ––– ID = -8.4A ns ––– RG = 9.1Ω ––– RD = 6.2Ω, See Fig. 10 „ Between lead, nH ––– and center of die contact ––– VGS = 0V ––– pF VDS = -25V ––– ƒ = 1.0MHz, See Fig. 5… Source-Drain Ratings and Characteristics IS I SM V SD t rr Q rr ton Notes: P arameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) … Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time Min. Typ. Max. Units Conditions D MOSFET symbol ––– ––– -14 showing the A G integral reverse ––– ––– -56 p-n junction diode. S ––– ––– -1.6 V TJ = 25°C, IS = -8.4A, VGS = 0V „ ––– 130 190 ns TJ = 25°C, IF = -8.4A ––– 650 970 nC di/dt = -100A/µs „… Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)  Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 ) „ Pulse width ≤ 300µs; duty cycle ≤ 2%. … Uses IRF9530N data and test conditions ‚ Starting TJ = 25°C, L =7.0mH RG = 25Ω, IAS = -8.4A. (See Figure 12) TJ ≤ 175°C ** When mounted on 1" square PCB (FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994. ƒ ISD ≤ -8.4A, di/dt ≤ -490A/µs, VDD ≤ V(BR)DSS, IRF9530NS/L 100 TOP VGS - 15V - 10V - 8.0V - 7.0V - 6.0V - 5.5V - 5.0V BOTTOM - 4.5V 100 -ID , D rain-to-S ource C urrent (A ) 10 -ID , Drain-to-Source Current (A ) VGS - 15V - 10V - 8.0V - 7.0V - 6.0V - 5.5V - 5.0V BOTTOM - 4.5V TOP 10 -4.5V 1 1 - 4 .5V 0.1 0.1 1 2 0 µ s P U L S E W ID TH TJ = 25°C c = 25 °C A 10 100 0.1 0.1 1 2 0 µ s P U LS E W ID TH TJ = 1 75 °C T C = 175°C 10 100 A -VD S , D rain-to-S ource V oltage (V ) -VD S , D rain-to-S ource V olta g e ( V ) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 100 2.5 R DS(on) , Drain-to-Source On Resistance (Normalized) ID = -14A -I D , D rain-to -So urc e C urre nt (A ) 2.0 T J = 2 5 °C 10 TJ = 1 7 5 °C 1.5 1.0 1 0.5 0.1 4 5 6 7 V DS = - 5 0 V 2 0µ s P U L S E W ID TH 8 9 10 A 0.0 -60 -40 -20 VGS = -10V 0 20 40 60 80 100 120 140 160 180 -VG S , Ga te -to-Source Volta ge (V) TJ , Junction Temperature ( °C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature IRF9530NS/L 2000 1600 -VGS , Gate-to-Source Voltage (V) V GS C iss C rs s C o ss = = = = 0V , f = 1MHz C g s + C g d , C d s S H O R TE D C gd C ds + C g d 20 ID = -8.4A VDS = -80V VDS = -50V VDS = -20V C , Capacitance (pF) 15 1200 C i ss 10 800 C o ss C r ss 5 400 0 1 10 100 A 0 0 10 20 30 FOR TEST CIRCUIT SEE FIGURE 13 40 50 60 -VD S , D rain-to-S ourc e V olta g e ( V ) QG , Total Gate Charge (nC) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 100 1000 -I SD , Reverse D rain Current (A ) OPERATION IN THIS AREA LIMITED BY RDS(on) T J = 15 0°C 10 -ID , Drain Current (A) I 100 10us T J = 2 5°C 100us 10 1ms 1 0.1 0.4 0.6 0.8 1.0 1.2 VG S = 0 V 1.4 A 1 1 TC = 25 °C TJ = 175 ° C Single Pulse 10 10ms 100 1000 1.6 -VS D , S ourc e-to-D rain V oltage (V ) -VDS , Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area IRF9530NS/L 14 VDS 12 RD VGS RG D.U.T. + -I D , Drain Current (A) 8 -10V Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % 6 4 Fig 10a. Switching Time Test Circuit td(on) tr t d(off) tf 2 VGS 10% 0 25 50 75 100 125 150 175 TC , Case Temperature ( ° C) 90% Fig 9. Maximum Drain Current Vs. Case Temperature VDS Fig 10b. Switching Time Waveforms 10 T herm al R es pons e (Z th J C ) 1 D = 0 .5 0 0 .2 0 0 .1 0 0 .0 5 0.1 0 .0 2 0 .0 1 S IN G L E P U L S E (T H E R M A L R E S P O N S E ) N o te s: 1 . D u ty fa c to r D = t PD M t 1 t 2 1 /t 2 0.01 0.00001 2. P e a k TJ = P D M x Z th JC + T C 0.0001 0.001 0.01 0.1 t 1 , R e c ta n g ula r P u lse D u ratio n (s e c ) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case - 10 V DD A 1 IRF9530NS/L 700 EAS , Single Pulse Avalanche Energy (mJ) VDS L 600 RG D .U .T IA S D R IV E R 0 .0 1 Ω VD D A ID -3.4A -5.9A BOTTOM -8.4A TOP 500 -2 0 V tp 400 300 15V 200 100 Fig 12a. Unclamped Inductive Test Circuit 0 25 50 75 100 125 150 175 IAS Starting TJ , Junction Temperature ( °C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current tp V ( BR ) DSS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ QG 12V .2µF VG VGS -3mA Charge IG ID Current Sampling Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit + QGS QGD D.U.T. - -10V .3µF VDS IRF9530NS/L Peak Diode Recovery dv/dt Test Circuit D.U.T* + ƒ + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer ‚ - „ +  RG VGS • dv/dt controlled by RG • ISD controlled by Duty Factor "D" • D.U.T. - Device Under Test + VDD * Reverse Polarity of D.U.T for P-Channel Driver Gate Drive P.W. Period D= P.W. Period [VGS=10V ] *** D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt [VDD] Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple ≤ 5% [ ISD ] *** VGS = 5.0V for Logic Level and 3V Drive Devices Fig 14. For P-Channel HEXFETS IRF9530NS/L D2Pak Package Outline 1 0.54 (.4 15) 1 0.29 (.4 05) 1.4 0 (.055 ) M AX. -A2 4.69 (.1 85) 4.20 (.1 65) -B 1.3 2 (.05 2) 1.2 2 (.04 8) 1 0.16 (.4 00 ) RE F. 6.47 (.2 55 ) 6.18 (.2 43 ) 15 .4 9 (.6 10) 14 .7 3 (.5 80) 5 .28 (.20 8) 4 .78 (.18 8) 2.7 9 (.110 ) 2.2 9 (.090 ) 2.61 (.1 03 ) 2.32 (.0 91 ) 1.3 9 (.0 5 5) 1.1 4 (.0 4 5) 8.8 9 (.3 50 ) R E F. 1.7 8 (.07 0) 1.2 7 (.05 0) 1 3 3X 1.40 (.0 55) 1.14 (.0 45) 5 .08 (.20 0) 0 .93 (.03 7 ) 3X 0 .69 (.02 7 ) 0 .25 (.01 0 ) M BAM 0.5 5 (.022 ) 0.4 6 (.018 ) M IN IM U M R E CO M M E ND E D F O O TP R IN T 1 1.43 (.4 50 ) NO TE S: 1 D IM EN S IO N S A FTER SO L D ER D IP. 2 D IM EN S IO N IN G & TO LE RA N C IN G PE R A N S I Y1 4.5M , 198 2. 3 C O N TRO L LIN G D IM EN SIO N : IN C H . 4 H E ATSINK & L EA D D IM EN S IO N S D O N O T IN C LU D E B UR R S. LE A D A SS IG N M E N TS 1 - G A TE 2 - D R AIN 3 - S O U RC E 8.89 (.3 50 ) 17 .78 (.70 0) 3 .8 1 (.15 0) 2 .08 (.08 2) 2X 2.5 4 (.100 ) 2X Part Marking Information D2Pak IN TE R N A TIO N A L R E C T IF IE R LO G O A S S E M B LY LO T C O D E PART NUM BER F530S 9 24 6 9B 1M A DATE CODE (Y YW W ) YY = Y E A R W W = W EEK IRF9530NS/L Package Outline TO-262 Outline Part Marking Information TO-262 IRF9530NS/L Tape & Reel Information D2Pak TR R 1 .6 0 (.0 6 3 ) 1 .5 0 (.0 5 9 ) 4 .1 0 (.1 6 1 ) 3 .9 0 (.1 5 3 ) 1 .60 (.06 3) 1 .50 (.05 9) 0 .3 68 (.0 1 4 5 ) 0 .3 42 (.0 1 3 5 ) F E E D D IRE CTIO N 1 .8 5 (.0 7 3 ) 1 .6 5 (.0 6 5 ) 1 1 .6 0 (.4 5 7 ) 1 1 .4 0 (.4 4 9 ) 1 5 .4 2 (.6 0 9 ) 1 5 .2 2 (.6 0 1 ) 2 4 .3 0 (.9 5 7 ) 2 3 .9 0 (.9 4 1 ) TR L 10 .9 0 (.42 9) 10 .7 0 (.42 1) 1 .75 (.06 9 ) 1 .25 (.04 9 ) 16 .10 (.63 4 ) 15 .90 (.62 6 ) 4 .7 2 (.1 3 6) 4 .5 2 (.1 7 8) F E E D D IRE C TIO N 13.50 (.532 ) 12.80 (.504 ) 2 7.4 0 (1.079) 2 3.9 0 (.9 41) 4 33 0.00 (1 4.1 73) MA X. 60.00 (2.3 62) MIN . NO TES : 1. C O M F O R M S TO E IA -4 18. 2. C O N TR O LLIN G D IM E N S IO N : M ILL IM ET ER . 3. D IM E N S IO N ME A S U R E D @ H U B . 4. IN C LU D E S F LA N G E D IS TO R T IO N @ O U T E R E D G E . 26 .40 (1.03 9) 24 .40 (.961 ) 3 3 0.40 (1.1 97) MAX. 4 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020 IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111 IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086 IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371 http://www.irf.com/ Data and specifications subject to change without notice. 5/98