IRFB20N50K

PD - 94418 IRFB20N50K SMPS MOSFET Applications l Switch Mode Power Supply (SMPS) l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits l HEXFET® Power MOSFET VDSS 500V RDS(on) typ. 0.21 Ω ID 20A Benefits Low Gate Charge Qg results in Simple Drive Requirement l Improved Gate, Avalanche and Dynamicdv/dt Ruggedness l Fully Characterized Capacitance and Avalanche Voltage and Current l Low RDS(on) Absolute Maximum Ratings Parameter ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current  Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt ƒ Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case ) Mounting Torque, 6-32 or M3 screw TO-220AB Max. 20 12 80 280 2.2 ± 30 6.9 -55 to + 150 300 10 Units A W W/°C V V/ns °C N Avalanche Characteristics Symbol EAS IAR EAR Parameter Single Pulse Avalanche Energy‚ Avalanche Current Repetitive Avalanche Energy Typ. ––– ––– ––– Max. 330 20 28 Units mJ A mJ Thermal Resistance Symbol RθJC RθCS RθJA Parameter Junction-to-Case Case-to-Sink, Flat, Greased Surface Junction-to-Ambient Typ. ––– 0.50 ––– Max. 0.45 ––– 58 Units °C/W www.irf.com 1 4/2/02 IRFB20N50K Static @ TJ = 25°C (unless otherwise specified) Symbol V(BR)DSS Parameter Drain-to-Source Breakdown Voltage ∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) Gate Threshold Voltage IDSS IGSS Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Min. 500 ––– ––– 3.0 ––– ––– ––– ––– Typ. ––– 0.61 0.21 ––– ––– ––– ––– ––– Max. Units Conditions ––– V VGS = 0V, ID = 250µA ––– V/°C Reference to 25°C, ID = 1mA 0.25 Ω VGS = 10V, ID = 12A „ 5.0 V VDS = VGS, ID = 250µA 50 µA VDS = 500V, VGS = 0V 250 µA VDS = 400V, VGS = 0V, TJ = 125°C 100 VGS = 30V nA -100 VGS = -30V Dynamic @ TJ = 25°C (unless otherwise specified) Symbol gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Coss Coss Coss eff. Parameter Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance Min. 11 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– Typ. ––– ––– ––– ––– 22 74 45 33 2870 320 34 3480 85 160 Max. Units Conditions ––– S VDS = 50V, ID = 12A 110 ID = 20A 33 nC VDS = 400V 54 VGS = 10V, See Fig. 6 and 13 „ ––– VDD = 250V ––– ID = 20A ns ––– RG = 7.5Ω ––– VGS = 10V,See Fig. 10 „ ––– VGS = 0V ––– VDS = 25V ––– pF ƒ = 1.0MHz, See Fig. 5 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz ––– VGS = 0V, VDS = 400V, ƒ = 1.0MHz ––– VGS = 0V, VDS = 0V to 400V … Diode Characteristics Symbol IS I SM VSD t rr Q rr ton Notes: Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)  Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time Min. Typ. Max. Units Conditions D MOSFET symbol 20 ––– ––– showing the A G integral reverse ––– ––– 80 S p-n junction diode. ––– ––– 1.5 V TJ = 25°C, IS = 20A, VGS = 0V „ ––– 520 780 ns TJ = 25°C, IF = 20A ––– 5.3 8.0 µC di/dt = 100A/µs „ Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)  Repetitive rating; pulse width limited by max. junction temperature. ƒ ISD ≤ 20A, di/dt ≤ 350A/µs, VDD ≤ V(BR)DSS, TJ ≤ 150°C ‚ Starting TJ = 25°C, L = 1.6mH, RG = 25Ω, IAS = 20A, „ Pulse width ≤ 400µs; duty cycle ≤ 2%. 2 www.irf.com IRFB20N50K 100 VGS 15V 12V 10V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V TOP 100 ID, Drain-to-Source Current (A) 10 ID, Drain-to-Source Current (A) 10 VGS 15V 12V 10V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V TOP 1 5.0V 1 0.1 5.0V 20µs PULSE WIDTH Tj = 25°C 20µs PULSE WIDTH Tj = 150°C 0.1 0.01 0.1 1 10 100 0.1 1 10 100 VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 100.0 3.5 I D = 20A ID, Drain-to-Source Current (Α) T J = 150°C R DS(on) , Drain-to-Source On Resistance 3.0 10.0 2.5 (Normalized) 1.0 T J = 25° C 2.0 1.5 0.1 1.0 0.0 5.0 6.0 7.0 VDS = 50V 20µs PULSE WIDTH 8.0 9.0 10.0 0.5 V GS = 10V 0.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature (° C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3 IRFB20N50K 100000 20 VGS = 0V, f = 1 MHZ C iss = C gs + C gd , C ds SHORTED VGS , Gate-to-Source Voltage (V) I 20A I DD==21A VDS = 400V VDS = 250V VDS = 100V 10000 C, Capacitance (pF) Crss Coss =C gd =C +C ds gd 16 Ciss 1000 12 Coss 100 8 4 Crss 10 1 10 100 1000 FOR TEST CIRCUIT SEE FIGURE13 0 0 20 40 60 80 100 120 VDS, Drain-to-Source Voltage (V) QG, Total Gate Charge (nC) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 100.0 1000 OPERATION IN THIS AREA LIMITED BY RDS (on) ISD, Reverse Drain Current (A) 10.0 T J = 150°C ID, Drain-to-Source Current (A) 100 10 100µsec 1msec 1.0 T J = 25° C 0.1 0.2 0.4 0.6 0.8 VGS = 0V 1.0 1.2 1 Tc = 25°C Tj = 150°C Single Pulse 1 10 100 10msec 0.1 1000 10000 VSD, Source-toDrain Voltage (V) VDS , Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRFB20N50K 20 V DS VGS RD 16 RG 10V Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % D.U.T. + -VDD ID , Drain Current (A) 12 8 Fig 10a. Switching Time Test Circuit 4 VDS 90% 0 25 50 75 100 125 150 T C, Case Temperature (°C) 10% VGS td(on) tr t d(off) tf Fig 9. Maximum Drain Current Vs. Case Temperature Fig 10b. Switching Time Waveforms 1 (Z thJC ) D = 0.50 0.1 0.20 0.10 Thermal Response 0.05 0.02 0.01 0.01 SINGLE PULSE (THERMAL RESPONSE) P DM t1 t2 Notes: 1. Duty factor D = 2. Peak T t1 / t 2 +TC 1 J = P DM x Z thJC 0.001 0.00001 0.0001 0.001 0.01 0.1 t1, Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRFB20N50K 15V 600 ID TOP 500 EAS , Single Pulse Avalanche Energy (mJ) VDS L DRIVER BOTTOM 9.4A 17A 20A 400 RG VGS 20V D.U.T IAS tp + V - DD A 0.01Ω 300 Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp 200 100 0 25 50 75 100 125 150 Starting TJ, Junction Temperature (°C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ QG 12V .2µF .3µF VGS QGS VG QGD VGS 3mA D.U.T. + V - DS IG ID Charge Current Sampling Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit 6 www.irf.com IRFB20N50K Peak Diode Recovery dv/dt Test Circuit D.U.T + ƒ + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer ‚ - „ +  RG • • • • dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test + VDD Driver Gate Drive P.W. Period D= P.W. Period VGS=10V * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt VDD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS www.irf.com 7 IRFB20N50K TO-220 Package Outline Dimensions are shown in millimeters (inches) 10.54 (.415) 10.29 (.405) 3.78 (.149) 3.54 (.139) -A6.47 (.255) 6.10 (.240) -B4.69 (.185) 4.20 (.165) 1.32 (.052) 1.22 (.048) 2.87 (.113) 2.62 (.103) 4 15.24 (.600) 14.84 (.584) 1.15 (.045) MIN 1 2 3 LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN 14.09 (.555) 13.47 (.530) 4.06 (.160) 3.55 (.140) 3X 3X 1.40 (.055) 1.15 (.045) 0.93 (.037) 0.69 (.027) M BAM 3X 0.55 (.022) 0.46 (.018) 0.36 (.014) 2.54 (.100) 2X NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH 2.92 (.115) 2.64 (.104) 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. TO-220 Part Marking Information EXAMPLE: T HIS IS AN IRF1010 L OT CODE 1789 AS S EMBLED ON WW 19, 1997 IN THE ASS EMBLY LINE "C" INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER DAT E CODE YEAR 7 = 1997 WEEK 19 LINE C Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.4/02 8 www.irf.com