PD - 95935B
IRFB3507PbF IRFS3507PbF IRFSL3507PbF
Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits l Lead-Free
HEXFET® Power MOSFET
D
G S
VDSS RDS(on) typ. max. ID
75V 7.0m: 8.8m: 97A
Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability
S D G
TO-220AB IRFB3507PbF
S GD
D2Pak IRFS3507PbF
S D G
TO-262 IRFSL3507PbF
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS dv/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw
Max.
97 69 390 190 1.3 ± 20 5.0 -55 to + 175 300 10lb in (1.1N m) 280 See Fig. 14, 15, 16a, 16b
d
Units
A
W W/°C V V/ns °C
f
x
x
Avalanche Characteristics
EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy
Ã
e
g
mJ A mJ
Thermal Resistance
Symbol
RθJC RθCS RθJA RθJA Junction-to-Case Case-to-Sink, Flat Greased Surface , TO-220 Junction-to-Ambient, TO-220 Junction-to-Ambient (PCB Mount) , D2Pak
k
Parameter
Typ.
––– 0.50 ––– –––
Max.
0.77 ––– 62 40
Units
°C/W
k
jk
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1
01/20/06
IRFB/S/SL3507PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS ∆V(BR)DSS/∆TJ RDS(on) VGS(th) IDSS IGSS RG
Parameter
Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Gate Input Resistance
Min. Typ. Max. Units
75 ––– ––– 2.0 ––– ––– ––– ––– ––– ––– ––– 0.070 ––– 7.0 8.8 ––– 4.0 ––– 20 ––– 250 ––– 200 ––– -200 1.3 –––
Conditions
V VGS = 0V, ID = 250µA V/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 58A V VDS = VGS, ID = 100µA µA VDS = 75V, VGS = 0V VDS = 75V, VGS = 0V, TJ = 125°C nA VGS = 20V VGS = -20V Ω f = 1MHz, open drain
g
d
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
––– 88 24 36 20 81 52 49 3540 340 210 460 520 ––– 130 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– S nC
Conditions
VDS = 50V, ID = 58A ID = 58A VDS = 60V VGS = 10V VDD = 48V ID = 58A RG = 5.6Ω VGS = 10V VGS = 0V VDS = 50V ƒ = 1.0MHz VGS = 0V, VDS = 0V to 60V VGS = 0V, VDS = 0V to 60V
86 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– Effective Output Capacitance (Energy Related) ––– ––– Effective Output Capacitance (Time Related)
ns
g g
pF
h
i, See Fig.11 h, See Fig. 5
D
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time
Min. Typ. Max. Units
––– ––– ––– ––– 97
Conditions
MOSFET symbol showing the integral reverse
G S
A A
Ãd
390
Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
––– ––– 1.3 V ––– 37 56 ns ––– 45 68 ––– 32 48 nC TJ = 125°C ––– 51 77 ––– 1.7 ––– A TJ = 25°C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
p-n junction diode. TJ = 25°C, IS = 58A, VGS = 0V TJ = 25°C VR = 64V, TJ = 125°C IF = 58A di/dt = 100A/µs TJ = 25°C
g
g
Notes: Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25°C, L = 0.17mH, RG = 25Ω, IAS = 58A, VGS =10V. Part not recommended for use above this value. ISD ≤ 58A, di/dt ≤ 390A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Coss eff. (ER) is a fixed capacitance that gives the same energy as When mounted on 1" square PCB (FR-4 or G-10 Material). For recom Rθ is measured at TJ approximately 90°C.
Coss while VDS is rising from 0 to 80% VDSS . mended footprint and soldering techniques refer to application note #AN-994.
2
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IRFB/S/SL3507PbF
1000
TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V
1000
TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
100
BOTTOM
10
4.5V 10
4.5V 1
≤60µs PULSE WIDTH
Tj = 25°C 0.1 0.1 1 10 100 1000 V DS, Drain-to-Source Voltage (V)
≤60µs PULSE WIDTH
Tj = 175°C 1 0.1 1 10 100 1000 V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
Fig 2. Typical Output Characteristics
2.5
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID = 97A 2.0
ID, Drain-to-Source Current (Α)
VGS = 10V
100 T J = 175°C 10 T J = 25°C 1 VDS = 25V ≤60µs PULSE WIDTH 0.1 2 4 6 8 10
1.5
1.0
0.5 -60 -40 -20 0 20 40 60 80 100 120140160 180 T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
100000
VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd
Fig 4. Normalized On-Resistance vs. Temperature
12.0 ID= 58A
VGS, Gate-to-Source Voltage (V)
10.0 8.0 6.0 4.0 2.0 0.0
VDS= 60V VDS= 38V VDS= 15V
C, Capacitance(pF)
10000 Ciss
1000
Coss Crss
100 1 10 VDS, Drain-to-Source Voltage (V) 100
0
20
40
60
80
100
QG Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFB/S/SL3507PbF
1000 10000 1000 100 1msec 10 10msec 1 DC 0.1 0.01 0.0 0.4 0.8 1.2 1.6 2.0 1 10 100 1000 VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V) Tc = 25°C Tj = 175°C Single Pulse OPERATION IN THIS AREA LIMITED BY R DS(on) 100µsec
ISD, Reverse Drain Current (A)
100
T J = 175°C
10 T J = 25°C 1 VGS = 0V 0.1
ID, Drain-to-Source Current (A)
Fig 7. Typical Source-Drain Diode Forward Voltage
100 Limited By Package 80
ID, Drain Current (A)
Fig 8. Maximum Safe Operating Area
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
95
90
60
85
40
80
20
75
0 25 50 75 100 125 150 175 T C , Case Temperature (°C)
70 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs. Case Temperature
1.6
Fig 10. Drain-to-Source Breakdown Voltage
1200
EAS , Single Pulse Avalanche Energy (mJ)
1.4 1.2
1000
ID 8.9A 12A BOTTOM 58A TOP
Energy (µJ)
1.0 0.8 0.6 0.4 0.2 0.0 0 10 20 30 40 50 60 70 80
800
600
400
200
0 25 50 75 100 125 150 175
VDS, Drain-to-Source Voltage (V)
Starting T J , Junction Temperature (°C)
4
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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IRFB/S/SL3507PbF
10
Thermal Response ( Z thJC )
1
D = 0.50
0.1
0.20 0.10 0.05 0.02 0.01 SINGLE PULSE ( THERMAL RESPONSE )
τJ
R1 R1 τJ τ1 τ2
R2 R2 τC τ
Ri (°C/W) τi (sec) 0.2963 0.000504 0.4738 0.013890
0.01
τ1
τ2
Ci= τi/Ri Ci i/Ri
0.001
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
0.001 0.01 0.1 1
0.0001 1E-006 1E-005 0.0001
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
Avalanche Current (A)
100
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆ Tj = 150°C and Tstart =25°C (Single Pulse)
0.01
10
0.05 0.10
1
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Τ j = 25°C and Tstart = 150°C.
1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
0.1 1.0E-06
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
300
EAR , Avalanche Energy (mJ)
250
TOP Single Pulse BOTTOM 1% Duty Cycle ID = 58A
200
150
100
50
0 25 50 75 100 125 150 175
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long as neither Tjmax nor Iav (max) is exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav
Starting T J , Junction Temperature (°C)
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFB/S/SL3507PbF
4.5
14 12 10
IRRM (A)
VGS(th) Gate threshold Voltage (V)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 200
8 6 4 2 0 100 200 300 400 500 600 700 800 900 1000 dif/dt (A/µs)
IF = 19A VR = 64V T = 25°C _____ J T = 125°C ---------J
ID = 100µA ID = 250µA ID = 1.0mA ID = 1.0A
T J , Temperature ( °C )
Fig 16. Threshold Voltage vs. Temperature
14 12 10
IRRM (A)
Fig. 17 - Typical Recovery Current vs. dif/dt
350 300 250
Qrr (nC)
8 6 4 2 0 100 200 300 400 500 600 700 800 900 1000 dif/dt (A/µs)
IF = 39A VR = 64V T = 25°C _____ J T = 125°C ---------J
200 150 100 50 0 100 200 300 400 500 600 700 800 900 1000 dif/dt (A/µs)
I = 19A F V = 64V R TJ = 25°C _____ TJ = 125°C ----------
Fig. 18 - Typical Recovery Current vs. dif/dt
300 250 200
Qrr (nC)
Fig. 19 - Typical Stored Charge vs. dif/dt
150 100 50 0 100 200 300 400 500 600 700 800 900 1000 dif/dt (A/µs)
I = 39A F V = 64V R TJ = 25°C _____ TJ = 125°C ----------
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFB/S/SL3507PbF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
• • • • dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple ≤ 5% ISD
* VGS = 5V for Logic Level Devices Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01Ω
I AS
Fig 21a. Unclamped Inductive Test Circuit
LD VDS
Fig 21b. Unclamped Inductive Waveforms
+
VDD D.U.T VGS Pulse Width < 1µs Duty Factor < 0.1%
90%
VDS
10%
VGS
td(on) tr td(off) tf
Fig 22a. Switching Time Test Circuit
Fig 22b. Switching Time Waveforms
Id Vds Vgs
L
0
DUT 1K
VCC
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
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Fig 23a. Gate Charge Test Circuit
Fig 23b. Gate Charge Waveform
7
IRFB/S/SL3507PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
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rrÅ
DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@
Q6SUÃIVH7@S
96U@Ã8P9@ `@6SÃÃ2Ã! X@@FÃ ( GDI@Ã8
TO-220AB packages are not recommended for Surface Mount Application.
8
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IRFB/S/SL3507PbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
@Y6HQG@) UCDTÃDTÃ6IÃDSG" "G GPUÃ8P9@Ã &'( 6TT@H7G@9ÃPIÃXXÃ (Ã ((& DIÃUC@Ã6TT@H7G`ÃGDI@ÃÅ8Å DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@ Q6SUÃIVH7@S
96U@Ã8P9@ `@6SÃ&Ã2Ã ((& X@@FÃ ( GDI@Ã8
25
DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@ Q6SUÃIVH7@S
96U@Ã8P9@ QÃ2Ã9@TDBI6U@TÃG@69AS@@ QSP9V8UÃPQUDPI6G `@6SÃ&Ã2Ã ((& X@@FÃ ( 6Ã2Ã6TT@H7G`ÃTDU@Ã8P9@
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9
IRFB/S/SL3507PbF
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D2Pak (TO-263AB) Part Marking Information
UCDTÃDTÃ6IÃDSA$"TÃXDUC GPUÃ8P9@Ã'!# 6TT@H7G@9ÃPIÃXXÃ!Ã! DIÃUC@Ã6TT@H7G`ÃGDI@ÃÅGÅ DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@ Q6SUÃIVH7@S A$"T 96U@Ã8P9@ `@6SÃÃ2Ã! X@@FÃ! GDI@ÃG
25
DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@
10
Q6SUÃIVH7@S A$"T 96U@Ã8P9@ QÃ2Ã9@TDBI6U@TÃG@69ÃÃAS@@ QSP9V8UÃPQUDPI6G `@6SÃÃ2Ã! X@@FÃ! 6Ã2Ã6TT@H7G`ÃTDU@Ã8P9@
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IRFB/S/SL3507PbF
D2Pak (TO-263AB) Tape & Reel Information
TRR
1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153)
1.60 (.063) 1.50 (.059)
0.368 (.0145) 0.342 (.0135)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
11.60 (.457) 11.40 (.449)
15.42 (.609) 15.22 (.601)
24.30 (.957) 23.90 (.941)
TRL
10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 16.10 (.634) 15.90 (.626) 4.72 (.136) 4.52 (.178)
FEED DIRECTION
13.50 (.532) 12.80 (.504)
27.40 (1.079) 23.90 (.941)
4
330.00 (14.173) MAX.
60.00 (2.362) MIN.
NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039) 24.40 (.961) 3
30.40 (1.197) MAX. 4
Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 01/06
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11
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/
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