IRFS4010PBF

PD - 96186 IRFS4010PbF IRFSL4010PbF HEXFET® Power MOSFET Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free D G S VDSS RDS(on) typ. max. ID D 100V 3.9m: 4.7m: 180A D S G G D S D2Pak IRFS4010PbF TO-262 IRFSL4010PbF G D S Gate Drain Source Absolute Maximum Ratings Symbol ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS dv/dt TJ TSTG Parameter Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw Max. 180 127 720 375 2.5 ± 20 31 -55 to + 175 300 10lb in (1.1N m) 318 See Fig. 14, 15, 22a, 22b, Units A W W/°C V V/ns c e °C x x Avalanche Characteristics EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy c d f ij mJ A mJ Thermal Resistance Symbol RθJC RθJA Junction-to-Case Junction-to-Ambient (PCB Mount) jk Parameter Typ. ––– ––– Max. 0.40 40 Units °C/W www.irf.com 1 10/06/08 IRFS/SL4010PbF Static @ TJ = 25°C (unless otherwise specified) Symbol V(BR)DSS ∆V(BR)DSS/∆TJ RDS(on) VGS(th) IDSS IGSS RG(int) Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance Min. Typ. Max. Units 100 ––– ––– 2.0 ––– ––– ––– ––– ––– Conditions ––– 0.10 3.9 ––– ––– ––– ––– ––– 2.0 ––– ––– 4.7 4.0 20 250 100 -100 ––– V VGS = 0V, ID = 250µA V/°C Reference to 25°C, ID = 5mA mΩ VGS = 10V, ID = 106A V VDS = VGS, ID = 250µA VDS = 100V, VGS = 0V µA VDS = 100V, VGS = 0V, TJ = 125°C VGS = 20V nA VGS = -20V f ™ Ω Dynamic @ TJ = 25°C (unless otherwise specified) Symbol gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR) Parameter Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. Typ. Max. Units 189 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 143 38 50 93 21 86 100 77 9575 660 270 757 1112 ––– 215 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– S nC Conditions VDS = 25V, ID = 106A ID = 106A VDS = 50V VGS = 10V ID = 106A, VDS =0V, VGS = 10V VDD = 65V ID = 106A RG = 2.7Ω VGS = 10V VGS = 0V VDS = 50V ƒ = 1.0MHz See Fig.5 VGS = 0V, VDS = 0V to 80V See Fig.11 VGS = 0V, VDS = 0V to 80V f ns f Effective Output Capacitance (Energy Related) Effective Output Capacitance (Time Related) g h pF h g Diode Characteristics Symbol IS ISM VSD trr Qrr IRRM ton Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Min. Typ. Max. Units ––– ––– ––– ––– 180 A 720 Conditions MOSFET symbol showing the integral reverse G S D Ù Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time ––– ––– 1.3 V ––– 72 ––– ns ––– 81 ––– ––– 210 ––– nC TJ = 125°C ––– 268 ––– ––– 5.3 ––– A TJ = 25°C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) p-n junction diode. TJ = 25°C, IS = 106A, VGS = 0V VR = 85V, TJ = 25°C TJ = 125°C IF = 106A di/dt = 100A/µs TJ = 25°C f f Notes:  Repetitive rating; pulse width limited by max. junction temperature. ‚ Limited by TJmax, starting TJ = 25°C, L = 0.057mH RG = 25 Ω, IAS = 106A, VGS =10V. Part not recommended for use above this value . ƒ ISD ≤ 106A, di/dt ≤ 1319A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. „ Pulse width ≤ 400µs; duty cycle ≤ 2%. … Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS . † Coss eff. (ER) is a fixed capacitance that gives the same energy as ‡ When mounted on 1" square PCB (FR-4 or G-10 Material). For recom ‰ RθJC value shown is at time zero Coss while VDS is rising from 0 to 80% VDSS. mended footprint and soldering techniques refer to application note #AN-994. ˆ Rθ is measured at TJ approximately 90°C 2 www.irf.com IRFS/SL4010PbF 1000 TOP VGS 15V 10V 8.0V 7.0V 5.0V 4.5V 4.3V 4.0V 1000 TOP VGS 15V 10V 8.0V 7.0V 5.0V 4.5V 4.3V 4.0V ID, Drain-to-Source Current (A) 100 BOTTOM ID, Drain-to-Source Current (A) BOTTOM 10 100 1 ≤60µs PULSE WIDTH Tj = 25°C 0.1 0.1 4.0V 1 10 100 4.0V 10 0.1 1 ≤60µs PULSE WIDTH Tj = 175°C 10 100 V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics 1000 Fig 2. Typical Output Characteristics 2.5 RDS(on) , Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (A) ID = 106A VGS = 10V 2.0 100 TJ = 175°C 10 T J = 25°C 1.5 1 VDS = 50V ≤60µs PULSE WIDTH 0.1 2 3 4 5 6 7 1.0 0.5 -60 -40 -20 0 20 40 60 80 100 120140160 180 T J , Junction Temperature (°C) VGS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics 100000 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd Fig 4. Normalized On-Resistance vs. Temperature 14.0 VGS, Gate-to-Source Voltage (V) 12.0 10.0 8.0 6.0 4.0 2.0 0.0 ID= 106A C, Capacitance (pF) VDS= 80V VDS= 50V 10000 Ciss 1000 Coss Crss 100 1 10 100 1000 VDS, Drain-to-Source Voltage (V) 0 25 50 75 100 125 150 175 200 225 QG, Total Gate Charge (nC) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage www.irf.com 3 IRFS/SL4010PbF 1000 10000 OPERATION IN THIS AREA LIMITED BY R DS(on) 1000 1msec ISD, Reverse Drain Current (A) 100 T J = 175°C ID, Drain-to-Source Current (A) 100 10 T J = 25°C 10 DC 10msec 100µsec 1 VGS = 0V 1.0 0.2 0.6 1.0 1.4 1.8 VSD, Source-to-Drain Voltage (V) 0.1 1 Tc = 25°C Tj = 175°C Single Pulse 10 100 1000 VDS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 200 180 160 ID, Drain Current (A) Fig 8. Maximum Safe Operating Area V(BR)DSS , Drain-to-Source Breakdown Voltage (V) 130 Id = 5mA 125 120 115 110 105 100 95 -60 -40 -20 0 20 40 60 80 100 120140 160180 T J , Temperature ( °C ) 140 120 100 80 60 40 20 0 25 50 75 100 125 150 175 T C , Case Temperature (°C) Fig 9. Maximum Drain Current vs. Case Temperature 4.0 3.5 3.0 Fig 10. Drain-to-Source Breakdown Voltage 1400 EAS , Single Pulse Avalanche Energy (mJ) 1200 1000 800 600 400 200 0 ID 12.5A 17A BOTTOM 106A TOP Energy (µJ) 2.5 2.0 1.5 1.0 0.5 0.0 0 20 40 60 80 100 120 25 50 75 100 125 150 175 Fig 11. Typical COSS Stored Energy VDS, Drain-to-Source Voltage (V) Starting T J , Junction Temperature (°C) Fig 12. Maximum Avalanche Energy vs. DrainCurrent 4 www.irf.com IRFS/SL4010PbF 1 Thermal Response ( Z thJC ) °C/W D = 0.50 0.1 0.20 0.10 0.05 0.01 0.02 0.01 R1 R1 τJ τ1 τ2 R2 R2 τC τ1 τ2 τ τJ Ri (°C/W) 0.17537 0.22547 τi (sec) 0.000343 0.006073 0.001 SINGLE PULSE ( THERMAL RESPONSE ) Ci= τi/Ri Ci i/Ri Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.01 0.1 0.0001 1E-006 1E-005 0.0001 0.001 t1 , Rectangular Pulse Duration (sec) Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case 1000 Duty Cycle = Single Pulse Avalanche Current (A) 100 0.01 0.05 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆ Tj = 150°C and Tstart =25°C (Single Pulse) 10 0.10 1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Τ j = 25°C and Tstart = 150°C. 0.1 1.0E-06 1.0E-05 1.0E-04 tav (sec) 1.0E-03 1.0E-02 1.0E-01 Fig 14. Typical Avalanche Current vs.Pulsewidth 350 300 EAR , Avalanche Energy (mJ) TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 106A 250 200 150 100 50 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav Fig 15. Maximum Avalanche Energy vs. Temperature www.irf.com 5 IRFS/SL4010PbF 4.5 VGS(th) , Gate threshold Voltage (V) 35 30 25 IRR (A) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 T J , Temperature ( °C ) ID = 250µA ID = 1.0mA ID = 1.0A IF = 70A V R = 85V TJ = 25°C TJ = 125°C 20 15 10 5 0 0 200 400 600 800 1000 diF /dt (A/µs) Fig 16. Threshold Voltage vs. Temperature 35 30 25 IRR (A) Fig. 17 - Typical Recovery Current vs. dif/dt 1100 IF = 106A V R = 85V TJ = 25°C TJ = 125°C 1000 900 800 QRR (A) IF = 70A V R = 85V TJ = 25°C TJ = 125°C 20 15 10 5 0 0 200 400 600 800 1000 diF /dt (A/µs) 700 600 500 400 300 200 100 0 200 400 600 800 1000 diF /dt (A/µs) Fig. 18 - Typical Recovery Current vs. dif/dt 1100 1000 900 800 QRR (A) Fig. 19 - Typical Stored Charge vs. dif/dt IF = 106A V R = 85V TJ = 25°C TJ = 125°C 700 600 500 400 300 200 0 200 400 600 800 1000 diF /dt (A/µs) 6 Fig. 20 - Typical Stored Charge vs. dif/dt www.irf.com IRFS/SL4010PbF D.U.T Driver Gate Drive + P.W. Period D= P.W. Period VGS=10V ƒ + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt ‚ - - „ +  RG • • • • dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD VDD + - Re-Applied Voltage Body Diode Forward Drop Inductor Curent Inductor Current Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs V(BR)DSS 15V tp DRIVER VDS L RG VGS 20V D.U.T IAS tp + V - DD A 0.01Ω I AS Fig 22a. Unclamped Inductive Test Circuit VDS VGS RG RD Fig 22b. Unclamped Inductive Waveforms VDS 90% D.U.T. + - VDD V10V GS Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % 10% VGS td(on) tr t d(off) tf Fig 23a. Switching Time Test Circuit Current Regulator Same Type as D.U.T. Fig 23b. Switching Time Waveforms Id Vds Vgs 50KΩ 12V .2µF .3µF D.U.T. VGS 3mA + V - DS Vgs(th) IG ID Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr www.irf.com Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform 7 IRFS/SL4010PbF TO-262 Package Outline Dimensions are shown in millimeters (inches) TO-262 Part Marking Information @Y6HQG@) UCDTÃDTÃ6IÃDSG" "G GPUÃ8P9@à &'( 6TT@H7G@9ÃPIÃXXà (à ((& DIÃUC@Ã6TT@H7G`ÃGDI@ÃÅ8Å DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@ Q6SUÃIVH7@S 96U@Ã8P9@ `@6SÃ&Ã2à ((& X@@Fà ( GDI@Ã8 25 DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@ Q6SUÃIVH7@S 96U@Ã8P9@ QÃ2Ã9@TDBI6U@TÃG@69AS@@ QSP9V8UÃPQUDPI6G `@6SÃ&Ã2à ((& X@@Fà ( 6Ã2Ã6TT@H7G`ÃTDU@Ã8P9@ Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ 8 www.irf.com IRFS/SL4010PbF Dimensions are shown in millimeters (inches) D2Pak (TO-263AB) Package Outline D2Pak (TO-263AB) Part Marking Information UCDTÃDTÃ6IÃDSA$"TÃXDUC GPUÃ8P9@Ã'!# 6TT@H7G@9ÃPIÃXXÃ!Ã! DIÃUC@Ã6TT@H7G`ÃGDI@ÃÅGÅ DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@ Q6SUÃIVH7@S A$"T 96U@Ã8P9@ `@6SÃÃ2Ã! X@@FÃ! GDI@ÃG 25 DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@ A$"T Q6SUÃIVH7@S 96U@Ã8P9@ QÃ2Ã9@TDBI6U@TÃG@69ÃÃAS@@ QSP9V8UÃPQUDPI6G `@6SÃÃ2Ã! X@@FÃ! 6Ã2Ã6TT@H7G`ÃTDU@Ã8P9@ 9 www.irf.com Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ IRFS/SL4010PbF D2Pak (TO-263AB) Tape & Reel Information Dimensions are shown in millimeters (inches) TRR 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135) FEED DIRECTION 1.85 (.073) 1.65 (.065) 11.60 (.457) 11.40 (.449) 15.42 (.609) 15.22 (.601) 24.30 (.957) 23.90 (.941) TRL 10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 16.10 (.634) 15.90 (.626) 4.72 (.136) 4.52 (.178) FEED DIRECTION 13.50 (.532) 12.80 (.504) 27.40 (1.079) 23.90 (.941) 4 330.00 (14.173) MAX. 60.00 (2.362) MIN. NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. 26.40 (1.039) 24.40 (.961) 3 30.40 (1.197) MAX. 4 Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. 10 IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 10/2008 www.irf.com