PD - 14275D
IRFB4310PbF IRFS4310PbF IRFSL4310PbF
Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits
G
HEXFET® Power MOSFET
D
Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free
S
VDSS RDS(on) typ. max. ID
100V 5.6m: 7.0m: 130A
S D G
TO-220AB IRFB4310PbF
S D G
D2Pak IRFS4310PbF
S D G
TO-262 IRFSL4310PbF
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS dV/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current
Max.
130 92
d
Units
A
550 300 2.0 ± 20 14 -55 to + 175 300 10lb in (1.1N m) W W/°C V V/ns °C
Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw
f
x
x
Avalanche Characteristics
EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy Avalanche Current
Ã
e
980 See Fig. 14, 15, 22a, 22b,
mJ A mJ
Repetitive Avalanche Energy
g
Thermal Resistance
Symbol
RθJC RθCS RθJA RθJA Junction-to-Case
k
Parameter
Typ.
––– 0.50 ––– –––
Max.
0.50 ––– 62 40
Units
°C/W
Case-to-Sink, Flat Greased Surface , TO-220 Junction-to-Ambient, TO-220
k
Junction-to-Ambient (PCB Mount) , D Pak
2
jk
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1
01/31/06
IRF/B/S/SL4310PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS ∆V(BR)DSS/∆TJ RDS(on) VGS(th) IDSS IGSS RG
Parameter
Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Gate Input Resistance
Min. Typ. Max. Units
100 ––– ––– ––– 0.064 ––– ––– 5.6 7.0 2.0 ––– 4.0 ––– ––– 20 ––– ––– 250 ––– ––– 200 ––– ––– -200 ––– 1.4 –––
Conditions
V VGS = 0V, ID = 250µA V/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 75A V VDS = VGS, ID = 250µA µA VDS = 100V, VGS = 0V VDS = 100V, VGS = 0V, TJ = 125°C nA VGS = 20V VGS = -20V Ω f = 1MHz, open drain
g
d
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Effective Output Capacitance (Energy Related) Effective Output Capacitance (Time Related)
Min. Typ. Max. Units
160 ––– ––– 170 ––– 46 ––– 62 ––– 26 ––– 110 ––– 68 ––– 78 ––– 7670 ––– 540 ––– 280 ––– 650 ––– 720.1 ––– 250 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– S nC
Conditions
VDS = 50V, ID = 75A ID = 75A VDS = 80V VGS = 10V VDD = 65V ID = 75A RG = 2.6Ω VGS = 10V VGS = 0V VDS = 50V ƒ = 1.0MHz VGS = 0V, VDS = 0V to 80V VGS = 0V, VDS = 0V to 80V
g g
ns
pF
h
i
j, See Fig.11 h, See Fig. 5
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
––– ––– ––– 130 –––
Conditions
MOSFET symbol showing the integral reverse
G S D
A
Ãdi
550
p-n junction diode. ––– ––– 1.3 V TJ = 25°C, IS = 75A, VGS = 0V VR = 85V, ––– 45 68 ns TJ = 25°C TJ = 125°C IF = 75A ––– 55 83 di/dt = 100A/µs ––– 82 120 nC TJ = 25°C TJ = 125°C ––– 120 180 ––– 3.3 ––– A TJ = 25°C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
g
g
Notes: Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25°C, L = 0.35mH RG = 25Ω, IAS = 75A, VGS =10V. Part not recommended for use above this value. ISD ≤ 75A, di/dt ≤ 550A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended
footprint and soldering techniques refer to application note #AN-994. Coss while VDS is rising from 0 to 80% VDSS.
Rθ is measured at TJ approximately 90°C.
2
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IRF/B/S/SL4310PbF
1000
TOP
1000
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V
TOP
BOTTOM
VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V
100
10
4.5V
1 0.1 1
≤ 60µs PULSE WIDTH Tj = 25°C
10 10 100 0.1 1
4.5V
≤ 60µs PULSE WIDTH Tj = 175°C
10 100
VDS , Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
Fig 2. Typical Output Characteristics
3.0
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID, Drain-to-Source Current(Α)
ID = 75A VGS = 10V
2.5
100
TJ = 175°C
2.0
1.5
10
TJ = 25°C VDS = 50V
1.0
≤ 60µs PULSE WIDTH
1 3.0 4.0 5.0 6.0 7.0 8.0
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
12000 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds + Cgd 8000
Fig 4. Normalized On-Resistance vs. Temperature
20
VGS, Gate-to-Source Voltage (V)
ID= 75A VDS = 80V VDS= 50V VDS= 20V
10000
16
C, Capacitance (pF)
Ciss
12
6000
8
4000
4
2000
Coss Crss
1 10 100
0
0 0 40 80 120 160 200 240 280 QG Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRF/B/S/SL4310PbF
1000.0
10000
TJ = 175°C
ID, Drain-to-Source Current (A)
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY R DS (on) 1000
100.0
100
100µsec
10.0
TJ = 25°C
1.0
10
1
VGS = 0V
0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Tc = 25°C Tj = 175°C Single Pulse 1 10
1msec 10msec DC 100 1000
0.1
VSD , Source-to-Drain Voltage (V)
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
V(BR)DSS , Drain-to-Source Breakdown Voltage
140 120
ID, Drain Current (A)
120
Fig 8. Maximum Safe Operating Area
Limited By Package
115
100 80 60 40 20 0 25 50 75 100 125 150 175 T C , Case Temperature (°C)
110
105
100 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 9. Maximum Drain Current vs. Case Temperature
EAS, Single Pulse Avalanche Energy (mJ)
4.0 3.5 3.0
Fig 10. Drain-to-Source Breakdown Voltage
2400
2000
ID 12A 17A BOTTOM 75A
TOP
1600
Energy (µJ)
2.5 2.0 1.5 1.0 0.5 0.0 0 20 40 60 80 100 120
1200
800
400
0 25 50 75 100 125 150 175
VDS, Drain-to-Source Voltage (V)
Starting TJ, Junction Temperature (°C)
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
4
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IRF/B/S/SL4310PbF
1
D = 0.50
Thermal Response ( ZthJC )
0.1
0.20 0.10 0.05
τJ R1 R1 τJ τ1 τ2 R2 R2 τC τ1 τ2 τ
0.01
0.02 0.01
Ri (°C/W) τi (sec) 0.1962 0.00117 0.2542 0.016569
0.001
Ci= τi/Ri Ci= i/Ri
SINGLE PULSE ( THERMAL RESPONSE )
0.0001 1E-006 1E-005 0.0001 0.001
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
0.01 0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Duty Cycle = Single Pulse 0.01
Avalanche Current (A)
10
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆ Tj = 150°C and Tstart =25°C (Single Pulse) 0.05 0.10
1
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Τ j = 25°C and Tstart = 150°C.
0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
1000
EAR , Avalanche Energy (mJ)
800
TOP Single Pulse BOTTOM 1% Duty Cycle ID = 75A
600
400
200
0 25 50 75 100 125 150 175
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long as neither Tjmax nor Iav (max) is exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav
Starting TJ , Junction Temperature (°C)
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRF/B/S/SL4310PbF
5.0
20
VGS(th) Gate threshold Voltage (V)
4.0
ID = 1.0A ID = 1.0mA ID = 250µA
16
IRRM - (A)
12
3.0
8 IF = 30A VR = 85V TJ = 125°C TJ = 25°C
2.0
4
1.0 -75 -50 -25 0 25 50 75 100 125 150 175
0 100 200 300 400 500 600 700 800 900 1000
TJ , Temperature ( °C )
dif / dt - (A / µs)
Fig 16. Threshold Voltage Vs. Temperature
20
Fig. 17 - Typical Recovery Current vs. dif/dt
500
16
400
QRR - (nC)
IRRM - (A)
12
300
8 IF = 45A VR = 85V TJ = 125°C TJ = 25°C 0 100 200 300 400 500 600 700 800 900 1000
200 IF = 30A VR = 85V TJ = 125°C TJ = 25°C 0 100 200 300 400 500 600 700 800 900 1000
4
100
dif / dt - (A / µs)
dif / dt - (A / µs)
Fig. 18 - Typical Recovery Current vs. dif/dt
500
Fig. 19 - Typical Stored Charge vs. dif/dt
400
QRR - (nC)
300
200 IF = 45A VR = 85V TJ = 125°C TJ = 25°C 0 100 200 300 400 500 600 700 800 900 1000
100
dif / dt - (A / µs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRF/B/S/SL4310PbF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
+
RG
• • • • dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple ≤ 5% ISD
* VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01Ω
I AS
Fig 22a. Unclamped Inductive Test Circuit
LD VDS
Fig 22b. Unclamped Inductive Waveforms
VDS
90%
+
VDD D.U.T
10%
VGS Pulse Width < 1µs Duty Factor < 0.1%
VGS
td(on) tr td(off) tf
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id Vds Vgs
L VCC
0
DUT 1K
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
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IRF/B/S/SL4310PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
@Y6HQG@) UCDTÃDTÃ6IÃDSA Ã GPUÃ8P9@Ã &'( 6TT@H7G@9ÃPIÃXXÃ (Ã! DIÃUC@Ã6TT@H7G`ÃGDI@ÃÅ8Å Ir)ÃÅQÅÃvÃhriyÃyvrÃvv vqvphrÃÅGrhqÃÃA
rrÅ
DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@
Q6SUÃIVH7@S
96U@Ã8P9@ `@6SÃÃ2Ã! X@@FÃ ( GDI@Ã8
TO-220AB packages are not recommended for Surface Mount Application.
8
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IRF/B/S/SL4310PbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
@Y6HQG@) UCDTÃDTÃ6IÃDSG" "G GPUÃ8P9@Ã &'( 6TT@H7G@9ÃPIÃXXÃ (Ã ((& DIÃUC@Ã6TT@H7G`ÃGDI@ÃÅ8Å DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@ Q6SUÃIVH7@S
96U@Ã8P9@ `@6SÃ&Ã2Ã ((& X@@FÃ ( GDI@Ã8
25
DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@ Q6SUÃIVH7@S
96U@Ã8P9@ QÃ2Ã9@TDBI6U@TÃG@69AS@@ QSP9V8UÃPQUDPI6G `@6SÃ&Ã2Ã ((& X@@FÃ ( 6Ã2Ã6TT@H7G`ÃTDU@Ã8P9@
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IRF/B/S/SL4310PbF
Dimensions are shown in millimeters (inches)
D2Pak (TO-263AB) Package Outline
D2Pak (TO-263AB) Part Marking Information
UCDTÃDTÃ6IÃDSA$"TÃXDUC GPUÃ8P9@Ã'!# 6TT@H7G@9ÃPIÃXXÃ!Ã! DIÃUC@Ã6TT@H7G`ÃGDI@ÃÅGÅ DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@ Q6SUÃIVH7@S A$"T 96U@Ã8P9@ `@6SÃÃ2Ã! X@@FÃ! GDI@ÃG
25
DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@
10
Q6SUÃIVH7@S A$"T 96U@Ã8P9@ QÃ2Ã9@TDBI6U@TÃG@69ÃÃAS@@ QSP9V8UÃPQUDPI6G `@6SÃÃ2Ã! X@@FÃ! 6Ã2Ã6TT@H7G`ÃTDU@Ã8P9@
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IRF/B/S/SL4310PbF
D2Pak (TO-263AB) Tape & Reel Information
TRR
1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153)
1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
11.60 (.457) 11.40 (.449)
15.42 (.609) 15.22 (.601)
24.30 (.957) 23.90 (.941)
TRL
10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 16.10 (.634) 15.90 (.626) 4.72 (.136) 4.52 (.178)
FEED DIRECTION
13.50 (.532) 12.80 (.504)
27.40 (1.079) 23.90 (.941)
4
330.00 (14.173) MAX.
60.00 (2.362) MIN.
NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039) 24.40 (.961) 3
30.40 (1.197) MAX. 4
Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 01/06
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Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/
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