IRFS4410ZPBF

PD - 97278B IRFB4410ZPbF IRFS4410ZPbF IRFSL4410ZPbF HEXFET® Power MOSFET Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free D G S V DSS R DS(on ) typ. m ax. ID (Silicon Limited ) ID (Package Limited) D D 100V 7.2m : 9.0m : 97 c 75A D G D S G D S G D S TO-220AB IRFB4410ZPbF G D2Pak IRFS4410ZPbF D TO-262 IRFSL4410ZPbF S Gate Drain Source Absolute Maximum Ratings Symbol ID @ TC = 25°C ID @ TC = 100°C ID @ TC = 25°C IDM PD @TC = 25°C VGS dv/dt TJ TSTG Parameter Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Package Limited) Pulsed Drain Current d Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery f Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw Single Pulse Avalanche Energy e Avalanche Current c Repetitive Avalanche Energy g Max. 97c 69c 75 390 230 1.5 ± 20 16 -55 to + 175 300 10lbxin (1.1Nxm) 242 See Fig. 14, 15, 22a, 22b, Units A W W/°C V V/ns °C Avalanche Characteristics EAS (Thermally limited) IAR EAR mJ A mJ Thermal Resistance Symbol RθJC RθCS RθJA RθJA Parameter Junction-to-Case k Case-to-Sink, Flat Greased Surface , TO-220 Junction-to-Ambient, TO-220 k Junction-to-Ambient (PCB Mount) , D Pak jk 2 Typ. ––– 0.50 ––– ––– Max. 0.65 ––– 62 40 Units °C/W www.irf.com 1 06/01/07 IRF/B/S/SL4410ZPbF Static @ TJ = 25°C (unless otherwise specified) Symbol V(BR)DSS ∆V(BR)DSS/∆TJ RDS(on) VGS(th) IDSS IGSS RG Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance Min. Typ. Max. Units 100 ––– ––– 2.0 ––– ––– ––– ––– ––– ––– 0.12 7.2 ––– ––– ––– ––– ––– 0.70 ––– ––– 9.0 4.0 20 250 100 -100 ––– Conditions V VGS = 0V, ID = 250µA V/°C Reference to 25°C, ID = 5mAd mΩ VGS = 10V, ID = 58A g V VDS = VGS, ID = 150µA µA VDS = 100V, VGS = 0V VDS = 80V, VGS = 0V, TJ = 125°C nA VGS = 20V VGS = -20V Ω Dynamic @ TJ = 25°C (unless otherwise specified) Symbol gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR) Parameter Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. Typ. Max. Units ––– 83 19 27 56 16 52 43 57 4820 340 170 420 690 ––– 120 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– S nC Conditions VDS = 10V, ID = 58A ID = 58A VDS =50V VGS = 10V g ID = 58A, VDS =0V, VGS = 10V g VDD = 65V ID = 58A RG =2.7Ω VGS = 10V g VGS = 0V VDS = 50V ƒ = 1.0MHz, See Fig.5 VGS = 0V, VDS = 0V to 80V i, See Fig.11 VGS = 0V, VDS = 0V to 80V h 140 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– Effective Output Capacitance (Energy Related) i ––– ––– Effective Output Capacitance (Time Related)h ns pF Diode Characteristics Symbol IS ISM VSD trr Qrr IRRM ton Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) d Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time Min. Typ. Max. Units ––– ––– ––– ––– 97c 390 A A Conditions MOSFET symbol showing the integral reverse G S D ––– ––– 1.3 V ––– 38 57 ns ––– 46 69 ––– 53 80 nC TJ = 125°C ––– 82 120 ––– 2.5 ––– A TJ = 25°C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) p-n junction diode. TJ = 25°C, IS = 58A, VGS = 0V g TJ = 25°C VR = 85V, TJ = 125°C IF = 58A di/dt = 100A/µs g TJ = 25°C Notes:  Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. ‚ Repetitive rating; pulse width limited by max. junction temperature. ƒ Limited by TJmax, starting TJ = 25°C, L = 0.143mH RG = 25Ω, IAS = 58A, VGS =10V. Part not recommended for use above this value. „ ISD ≤ 58A, di/dt ≤ 610A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. … Pulse width ≤ 400µs; duty cycle ≤ 2%. † Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. ‡ Coss eff. (ER) is a fixed capacitance that gives the same energy as ˆ When mounted on 1" square PCB (FR-4 or G-10 Material). For recom ‰ Rθ is measured at TJ approximately 90°C. Coss while VDS is rising from 0 to 80% VDSS. mended footprint and soldering techniques refer to application note #AN-994. 2 www.irf.com IRF/B/S/SL4410ZPbF 1000 TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V 1000 TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V ID, Drain-to-Source Current (A) 100 ID, Drain-to-Source Current (A) BOTTOM 100 BOTTOM 4.5V 4.5V 10 10 ≤60µs PULSE WIDTH Tj = 25°C 1 0.1 1 10 100 V DS, Drain-to-Source Voltage (V) ≤60µs PULSE WIDTH Tj = 175°C 1 0.1 1 10 100 V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics 1000 RDS(on) , Drain-to-Source On Resistance (Normalized) Fig 2. Typical Output Characteristics 2.5 ID = 58A 2.0 ID, Drain-to-Source Current (A) VDS = 50V ≤60µs PULSE WIDTH 100 VGS = 10V 10 T J = 175°C 1 T J = 25°C 1.5 1.0 0.1 2 3 4 5 6 7 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 T J , Junction Temperature (°C) VGS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics 100000 VGS = 0V, f = 1 MHZ Ciss = C gs + Cgd, C ds SHORTED Crss = C gd Coss = Cds + Cgd Fig 4. Normalized On-Resistance vs. Temperature 12.0 ID= 58A VGS, Gate-to-Source Voltage (V) 10.0 8.0 6.0 4.0 2.0 0.0 VDS= 80V VDS= 40V VDS= 20V C, Capacitance (pF) 10000 Ciss Coss 1000 Crss 100 1 10 VDS, Drain-to-Source Voltage (V) 100 0 20 40 60 80 100 QG, Total Gate Charge (nC) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage www.irf.com 3 IRF/B/S/SL4410ZPbF 1000 1000 OPERATION IN THIS AREA LIMITED BY R DS(on) 100µsec 1msec 100 T J = 175°C 10 T J = 25°C 1 VGS = 0V 0.1 0.0 0.5 1.0 1.5 2.0 2.5 VSD, Source-to-Drain Voltage (V) ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 100 10msec DC 10 Tc = 25°C Tj = 175°C Single Pulse 1 0 1 10 100 VDS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 100 Limited By Package 80 ID, Drain Current (A) V(BR)DSS , Drain-to-Source Breakdown Voltage (V) Fig 8. Maximum Safe Operating Area 125 Id = 5mA 120 115 110 105 100 95 90 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 T J , Temperature ( °C ) 60 40 20 0 25 50 75 100 125 150 175 T C , Case Temperature (°C) Fig 9. Maximum Drain Current vs. Case Temperature 2.0 1.8 1.6 1.4 Energy (µJ) Fig 10. Drain-to-Source Breakdown Voltage 1000 EAS , Single Pulse Avalanche Energy (mJ) 900 800 700 600 500 400 300 200 100 0 25 50 75 100 ID TOP 6.4A 9.4A BOTTOM 58A 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -10 0 10 20 30 40 50 60 70 80 90 100 VDS, Drain-to-Source Voltage (V) 125 150 175 Starting T J , Junction Temperature (°C) Fig 11. Typical COSS Stored Energy Fig 12. Maximum Avalanche Energy vs. DrainCurrent 4 www.irf.com IRF/B/S/SL4410ZPbF 1 Thermal Response ( Z thJC ) °C/W D = 0.50 0.1 0.20 0.10 0.05 0.02 0.01 SINGLE PULSE ( THERMAL RESPONSE ) τJ τJ τ1 R1 R1 τ2 R2 R2 τC τ τ2 Ri (°C/W) τi (sec) 0.237 0.000178 0.413 0.003772 τ1 0.01 Ci= τi/Ri Ci i/Ri Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.001 0.01 0.1 0.001 1E-006 1E-005 0.0001 t1 , Rectangular Pulse Duration (sec) Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case 100 Duty Cycle = Single Pulse 0.01 Avalanche Current (A) Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆ Tj = 150°C and Tstart =25°C (Single Pulse) 10 0.05 0.10 1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Τ j = 25°C and Tstart = 150°C. 0.1 1.0E-06 1.0E-05 1.0E-04 tav (sec) 1.0E-03 1.0E-02 1.0E-01 Fig 14. Typical Avalanche Current vs.Pulsewidth 150 TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 58A Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) EAR , Avalanche Energy (mJ) 100 50 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav Fig 15. Maximum Avalanche Energy vs. Temperature www.irf.com 5 IRF/B/S/SL4410ZPbF 4.5 VGS(th) , Gate threshold Voltage (V) 20 IF = 39A VR = 85V TJ = 25°C _____ 4.0 3.5 3.0 2.5 2.0 1.5 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 200 T J , Temperature ( °C ) ID = 150µA ID = 250µA ID = 1.0mA ID = 1.0A 15 TJ = 125°C ---------- IRRM (A) 10 5 0 100 200 300 400 dif/dt (A/µs) 500 600 700 Fig 16. Threshold Voltage vs. Temperature 20 I = 58A F V = 85V R T = 25°C _____ J T = 125°C ---------J Fig. 17 - Typical Recovery Current vs. dif/dt 400 350 300 250 IF = 39A VR = 85V TJ = 25°C _____ TJ = 125°C ---------- 15 IRRM (A) Qrr (nC) 10 200 150 5 100 50 0 100 200 300 400 dif/dt (A/µs) 500 600 700 0 100 200 300 400 dif/dt (A/µs) 500 600 700 Fig. 18 - Typical Recovery Current vs. dif/dt 450 400 350 300 Qrr (nC) I = 58A F V = 85V R T = 25°C _____ J T = 125°C J ---------- Fig. 19 - Typical Stored Charge vs. dif/dt 250 200 150 100 50 0 100 200 300 400 dif/dt (A/µs) 500 600 700 6 Fig. 20 - Typical Stored Charge vs. dif/dt www.irf.com IRF/B/S/SL4410ZPbF D.U.T Driver Gate Drive + P.W. Period D= P.W. Period VGS=10V ƒ + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt ‚ - - „ +  RG • • • • dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD VDD + - Re-Applied Voltage Body Diode Forward Drop Inductor Curent Inductor Current Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs V(BR)DSS 15V tp VDS L DRIVER RG 20V D.U.T IAS tp + V - DD A 0.01Ω I AS Fig 22a. Unclamped Inductive Test Circuit LD VDS Fig 22b. Unclamped Inductive Waveforms VGS + VDD D.U.T 90% VGS Second Pulse Width < 1µs Duty Factor < 0.1% 10% VDS td(off) tf td(on) tr Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms Id Vds Vgs L 0 DUT 20K 1K S VCC Vgs(th) Qgodr Qgd Qgs2 Qgs1 www.irf.com Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform 7 IRF/B/S/SL4410ZPbF TO-220AB Package Outline Dimensions are shown in millimeters (inches) TO-220AB Part Marking Information (;$03/( 7+,6 ,6 $1 ,5) /27 &2'(  $66(0%/(' 21 ::   ,1 7+( $66(0%/< /,1( & 1RWH 3 LQ DVVHPEO\ OLQH SRVLWLRQ LQGLFDWHV /HDG  )UHH ,17(51$7,21$/ 5(&7,),(5 /2*2 $66(0%/< /27 &2'( 3$57 180%(5 '$7( &2'(