IRFSL4127PbF

PD - 96177 IRFS4127PbF IRFSL4127PbF Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free HEXFET® Power MOSFET D G S VDSS RDS(on) typ. max. ID 200V 18.6m: 22m: 72A D D S G G D S D2Pak IRFS4127PbF TO-262 IRFSL4127PbF G D S Gate Drain Source Absolute Maximum Ratings Symbol ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS dv/dt TJ TSTG Parameter Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw Max. 72 51 300 375 2.5 ± 20 57 -55 to + 175 300 10lb in (1.1N m) 250 See Fig. 14, 15, 22a, 22b, Units A W W/°C V V/ns °C c e x x Avalanche Characteristics EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy c d f mJ A mJ Thermal Resistance Symbol RθJC RθJA Junction-to-Case Junction-to-Ambient www.irf.com jk ij Parameter Typ. ––– ––– Max. 0.4 40 Units °C/W 1 09/16/08 IRFS/SL4127PbF Static @ TJ = 25°C (unless otherwise specified) Symbol V(BR)DSS ∆V(BR)DSS/∆TJ RDS(on) VGS(th) IDSS IGSS RG(int) Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance Min. Typ. Max. Units 200 ––– ––– 3.0 ––– ––– ––– ––– ––– Conditions ––– 0.23 18.6 ––– ––– ––– ––– ––– 3.0 ––– V VGS = 0V, ID = 250µA ––– V/°C Reference to 25°C, ID = 5mA 22 mΩ VGS = 10V, ID = 44A 5.0 V VDS = VGS, ID = 250µA VDS = 200V, VGS = 0V 20 µA 250 VDS = 200V, VGS = 0V, TJ = 125°C 100 VGS = 20V nA VGS = -20V -100 f ™ ––– Ω Dynamic @ TJ = 25°C (unless otherwise specified) Symbol gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR) Parameter Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. Typ. Max. Units 79 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 100 30 31 69 17 18 56 22 5380 410 86 360 590 ––– 150 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– S Conditions Effective Output Capacitance (Energy Related) Effective Output Capacitance (Time Related) g h VDS = 50V, ID = 44A ID = 44A VDS = 100V nC VGS = 10V ID = 44A, VDS =0V, VGS = 10V VDD = 130V ID = 44A ns RG = 2.7Ω VGS = 10V VGS = 0V VDS = 50V pF ƒ = 1.0MHz (See Fig.5) VGS = 0V, VDS = 0V to 160V (See Fig.11) VGS = 0V, VDS = 0V to 160V f f h g Diode Characteristics Symbol IS ISM VSD trr Qrr IRRM ton Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Min. Typ. Max. Units ––– ––– ––– ––– 76 300 A Conditions MOSFET symbol showing the integral reverse G D Ù Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time p-n junction diode. S ––– ––– 1.3 V TJ = 25°C, IS = 44A, VGS = 0V TJ = 25°C VR = 100V, ––– 136 ––– ns TJ = 125°C IF = 44A ––– 139 ––– di/dt = 100A/µs TJ = 25°C ––– 458 ––– nC TJ = 125°C ––– 688 ––– ––– 8.3 ––– A TJ = 25°C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) f f Notes:  Repetitive rating; pulse width limited by max. junction temperature. ‚ Limited by TJmax, starting TJ = 25°C, L = 0.26mH RG = 25 Ω, IAS = 44A, VGS =10V. Part not recommended for use above this value . ƒ ISD ≤ 44A, di/dt ≤ 760A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. „ Pulse width ≤ 400µs; duty cycle ≤ 2%. … Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS . † Coss eff. (ER) is a fixed capacitance that gives the same energy as ‡ When mounted on 1" square PCB (FR-4 or G-10 Material). For recom ‰ RθJC value shown is at time zero Coss while VDS is rising from 0 to 80% VDSS. mended footprint and soldering techniques refer to application note #AN-994. ˆ Rθ is measured at TJ approximately 90°C 2 www.irf.com IRFS/SL4127PbF 1000 TOP 1000 ID, Drain-to-Source Current (A) 100 ID, Drain-to-Source Current (A) 10 BOTTOM VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V TOP 100 BOTTOM VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V 10 1 4.5V 1 0.1 4.5V 0.01 0.1 1 ≤ 60µs PULSE WIDTH Tj = 25°C 0.1 10 100 0.1 1 ≤ 60µs PULSE WIDTH Tj = 175°C 10 100 VDS , Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics VDS = 50V RDS(on) , Drain-to-Source On Resistance (Normalized) 1000 3.5 Fig 2. Typical Output Characteristics ID = 44A 3.0 ID, Drain-to-Source Current(Α) ≤ 60µs PULSE WIDTH 100 VGS = 10V TJ = 175°C 10 2.5 2.0 TJ = 25°C 1 1.5 1.0 0.1 3.0 4.0 5.0 6.0 7.0 8.0 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 VGS, Gate-to-Source Voltage (V) TJ , Junction Temperature (°C) Fig 3. Typical Transfer Characteristics 8000 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds + Cgd Fig 4. Normalized On-Resistance vs. Temperature 16 VGS, Gate-to-Source Voltage (V) ID= 44A 12 6000 C, Capacitance (pF) Ciss 4000 VDS = 160V VDS = 100V VDS = 40V 8 2000 Coss 0 1 Crss 10 VDS, Drain-to-Source Voltage (V) 100 4 0 0 20 40 60 80 100 120 QG Total Gate Charge (nC) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage www.irf.com 3 IRFS/SL4127PbF 1000 1000 OPERATION IN THIS AREA LIMITED BY R DS(on) 100µsec 100 TJ = 175°C ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 100 1msec 10 10msec 1 Tc = 25°C Tj = 175°C Single Pulse 0.1 1 10 10 TJ = 25°C 1 VGS = 0V 0.1 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 DC 100 1000 VSD , Source-to-Drain Voltage (V) VDS , Drain-toSource Voltage (V) V(BR)DSS, Drain-to-Source Breakdown Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 80 Fig 8. Maximum Safe Operating Area 260 Id = 5mA ID, Drain Current (A) 60 240 40 220 20 200 0 25 50 75 100 125 150 175 T C , Case Temperature (°C) 180 -60 -40 -20 0 20 40 60 80 100120 140160 180 TJ , Temperature ( °C ) Fig 9. Maximum Drain Current vs. Case Temperature EAS, Single Pulse Avalanche Energy (mJ) 8.0 Fig 10. Drain-to-Source Breakdown Voltage 1000 800 6.0 ID 8.2A 13A BOTTOM 44A TOP Energy (µJ) 600 4.0 400 2.0 200 0.0 0 40 80 120 160 200 0 25 50 75 100 125 150 175 VDS, Drain-to-Source Voltage (V) Starting TJ, Junction Temperature (°C) Fig 11. Typical COSS Stored Energy Fig 12. Maximum Avalanche Energy Vs. DrainCurrent 4 www.irf.com IRFS/SL4127PbF 1 Thermal Response ( ZthJC ) D = 0.50 0.1 0.20 0.10 0.05 τJ τJ τ1 R1 R1 τ2 R2 R2 R3 R3 τ3 R4 R4 τC τ τ2 τ3 τ4 τ4 0.01 0.02 0.01 SINGLE PULSE ( THERMAL RESPONSE ) τ1 Ci= τi/Ri Ci i/Ri Ri (°C/W) 0.02 0.083333 0.181667 0.113333 τι (sec) 0.000019 0.000078 0.001716 0.008764 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.0001 0.001 0.01 0.1 0.001 1E-006 1E-005 t1 , Rectangular Pulse Duration (sec) Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case 100 Duty Cycle = Single Pulse 0.01 10 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Tj = 150°C and Tstart =25°C (Single Pulse) Avalanche Current (A) 0.05 0.10 1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Τ j = 25°C and Tstart = 150°C. 0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 14. Typical Avalanche Current vs.Pulsewidth 250 EAR , Avalanche Energy (mJ) 200 TOP Single Pulse BOTTOM 1% Duty Cycle ID = 44A 150 100 50 Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) 175 0 25 50 75 100 125 150 Starting TJ , Junction Temperature (°C) PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav Fig 15. Maximum Avalanche Energy vs. Temperature www.irf.com 5 IRFS/SL4127PbF 6.0 50 VGS(th) Gate threshold Voltage (V) ID = 1.0A 5.0 ID = 1.0mA ID = 250µA 40 3.0 IRRM - (A) 4.0 30 20 IF = 29A VR = 100V TJ = 125°C TJ = 25°C 100 200 300 400 500 600 700 800 900 1000 2.0 10 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 0 TJ , Temperature ( °C ) dif / dt - (A / µs) Fig 16. Threshold Voltage Vs. Temperature 60 Fig. 17 - Typical Recovery Current vs. dif/dt 3000 50 2500 40 2000 30 QRR - (nC) IF = 44A VR = 100V TJ = 125°C TJ = 25°C IRRM - (A) 1500 20 1000 10 500 IF = 29A VR = 100V TJ = 125°C TJ = 25°C 100 200 300 400 500 600 700 800 900 1000 0 0 100 200 300 400 500 600 700 800 900 1000 dif / dt - (A / µs) dif / dt - (A / µs) Fig. 18 - Typical Recovery Current vs. dif/dt 3000 Fig. 19 - Typical Stored Charge vs. dif/dt 2500 2000 QRR - (nC) 1500 1000 500 IF = 44A VR = 100V TJ = 125°C TJ = 25°C 100 200 300 400 500 600 700 800 900 1000 0 dif / dt - (A / µs) 6 Fig. 20 - Typical Stored Charge vs. dif/dt www.irf.com IRFS/SL4127PbF D.U.T Driver Gate Drive + P.W. Period D= P.W. Period VGS=10V ƒ + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt ‚ - - „ +  RG • • • • dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD VDD + - Re-Applied Voltage Body Diode Forward Drop Inductor Curent Inductor Current Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs V(BR)DSS 15V tp DRIVER VDS L RG VGS 20V D.U.T IAS tp + V - DD A 0.01Ω I AS Fig 22a. Unclamped Inductive Test Circuit VDS VGS RG RD Fig 22b. Unclamped Inductive Waveforms VDS 90% D.U.T. + - VDD V10V GS Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % 10% VGS td(on) tr t d(off) tf Fig 23a. Switching Time Test Circuit Current Regulator Same Type as D.U.T. Fig 23b. Switching Time Waveforms Id Vds Vgs 50KΩ 12V .2µF .3µF D.U.T. VGS 3mA + V - DS Vgs(th) IG ID Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr www.irf.com Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform 7 IRFS/SL4127PbF Dimensions are shown in millimeters (inches) D2Pak (TO-263AB) Package Outline D2Pak (TO-263AB) Part Marking Information UCDTÃDTÃ6IÃDSA$"TÃXDUC GPUÃ8P9@Ã'!# 6TT@H7G@9ÃPIÃXXÃ!Ã! DIÃUC@Ã6TT@H7G`ÃGDI@ÃÅGÅ DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@ Q6SUÃIVH7@S A$"T 96U@Ã8P9@ `@6SÃÃ2Ã! X@@FÃ! GDI@ÃG 25 DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@ A$"T Q6SUÃIVH7@S 96U@Ã8P9@ QÃ2Ã9@TDBI6U@TÃG@69ÃÃAS@@ QSP9V8UÃPQUDPI6G `@6SÃÃ2Ã! X@@FÃ! 6Ã2Ã6TT@H7G`ÃTDU@Ã8P9@ www.irf.com Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ 8 IRFS/SL4127PbF TO-262 Package Outline Dimensions are shown in millimeters (inches) TO-262 Part Marking Information @Y6HQG@) UCDTÃDTÃ6IÃDSG" "G GPUÃ8P9@à &'( 6TT@H7G@9ÃPIÃXXà (à ((& DIÃUC@Ã6TT@H7G`ÃGDI@ÃÅ8Å DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@ Q6SUÃIVH7@S 96U@Ã8P9@ `@6SÃ&Ã2à ((& X@@Fà ( GDI@Ã8 25 DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@ Q6SUÃIVH7@S 96U@Ã8P9@ QÃ2Ã9@TDBI6U@TÃG@69AS@@ QSP9V8UÃPQUDPI6G `@6SÃ&Ã2à ((& X@@Fà ( 6Ã2Ã6TT@H7G`ÃTDU@Ã8P9@ Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ www.irf.com 9 IRFS/SL4127PbF D2Pak (TO-263AB) Tape & Reel Information Dimensions are shown in millimeters (inches) TRR 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135) FEED DIRECTION 1.85 (.073) 1.65 (.065) 11.60 (.457) 11.40 (.449) 15.42 (.609) 15.22 (.601) 24.30 (.957) 23.90 (.941) TRL 10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 16.10 (.634) 15.90 (.626) 4.72 (.136) 4.52 (.178) FEED DIRECTION 13.50 (.532) 12.80 (.504) 27.40 (1.079) 23.90 (.941) 4 330.00 (14.173) MAX. 60.00 (2.362) MIN. NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. 26.40 (1.039) 24.40 (.961) 3 30.40 (1.197) MAX. 4 Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 09/2008 10 www.irf.com