PD - 95707E
IRFB4410PbF IRFS4410PbF IRFSL4410PbF
Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits
G S
HEXFET® Power MOSFET
D
Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free
VDSS RDS(on) typ. max. ID
100V 8.0m: 10m: 88A
S D G
TO-220AB IRFB4410PbF
S D G
D2Pak IRFS4410PbF
S D G
TO-262 IRFSL4410PbF
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS dv/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current
d
l 63l
88 380 200 1.3
Max.
Units
A
Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw
l l
W W/°C V V/ns °C
f
± 20 19 -55 to + 175 300 10lb in (1.1N m) 220 See Fig. 14, 15, 16a, 16b
x
x
Avalanche Characteristics
EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy Avalanche Current
Ã
e
mJ A mJ
Repetitive Avalanche Energy
g
Thermal Resistance
Symbol
RθJC RθCS RθJA RθJA Junction-to-Case
Case-to-Sink, Flat Greased Surface , TO-220 Junction-to-Ambient, TO-220 Junction-to-Ambient (PCB Mount) , D2Pak
k
Parameter
Typ.
––– 0.50 ––– –––
Max.
0.61 ––– 62 40
l
Units
°C/W
k
jk
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1
05/02/07
IRFB/S/SL4410PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS ∆V(BR)DSS/∆TJ RDS(on) VGS(th) IDSS IGSS RG
Parameter
Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Gate Input Resistance
Min. Typ. Max. Units
100 ––– ––– 2.0 ––– ––– ––– ––– ––– ––– ––– 0.094 ––– 8.0 10 ––– 4.0 ––– 20 ––– 250 ––– 200 ––– -200 1.5 –––
Conditions
V VGS = 0V, ID = 250µA V/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 58A V VDS = VGS, ID = 150µA µA VDS = 100V, VGS = 0V VDS = 100V, VGS = 0V, TJ = 125°C nA VGS = 20V VGS = -20V Ω f = 1MHz, open drain
g
d
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Effective Output Capacitance (Energy Related) Effective Output Capacitance (Time Related)
Min. Typ. Max. Units
120 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 120 31 44 24 80 55 50 5150 360 190 420 500 ––– 180 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– S nC
Conditions
VDS = 50V, ID = 58A ID = 58A VDS = 80V VGS = 10V VDD = 65V ID = 58A RG = 4.1Ω VGS = 10V VGS = 0V VDS = 50V ƒ = 1.0MHz VGS = 0V, VDS = 0V to 80V VGS = 0V, VDS = 0V to 80V
ns
g g
pF
h
i, See Fig.11 h, See Fig. 5
D
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
––– ––– ––– ––– 88
Conditions
MOSFET symbol showing the integral reverse
G S
A A
Ãd
380
––– ––– 1.3 V ––– 38 56 ns ––– 51 77 ––– 61 92 nC TJ = 125°C ––– 110 170 ––– 2.8 ––– A TJ = 25°C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
p-n junction diode. TJ = 25°C, IS = 58A, VGS = 0V VR = 85V, TJ = 25°C IF = 58A TJ = 125°C di/dt = 100A/µs TJ = 25°C
g
g
Notes: Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25°C, L = 0.14mH RG = 25Ω, IAS = 58A, VGS =10V. Part not recommended for use above this value. ISD ≤ 58A, di/dt ≤ 650A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Coss eff. (ER) is a fixed capacitance that gives the same energy as When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended
footprint and soldering techniques refer to application note #AN-994. Coss while VDS is rising from 0 to 80% VDSS .
Rθ is measured at TJ approximately 90°C. RθJC (end of life) for D2Pak and TO-262 = 0.75°C/W. Note: This is the maximum
measured value after 1000 temperature cycles from -55 to 150°C and is accounted for by the physical wearout of the die attach medium.
2
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IRFB/S/SL4410PbF
1000
TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V
1000
TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
100
BOTTOM
10
10
4.5V
1 4.5V
≤60µs PULSE WIDTH
0.1 0.1 1 Tj = 25°C 10 1 100 1000 0.1 1
≤60µs PULSE WIDTH
Tj = 175°C 10
100
1000
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
3.0
Fig 2. Typical Output Characteristics
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID, Drain-to-Source Current (Α)
100 T J = 175°C 10 T J = 25°C 1 VDS = 25V ≤60µs PULSE WIDTH 0.1 2 3 4 5 6 7 8 9 10
2.5
ID = 58A VGS = 10V
2.0
1.5
1.0
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
T J , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
100000
VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd
Fig 4. Normalized On-Resistance vs. Temperature
12.0 ID= 58A
VGS, Gate-to-Source Voltage (V)
10.0 8.0 6.0 4.0 2.0 0.0
C, Capacitance(pF)
10000 Ciss
VDS= 80V VDS= 50V VDS= 20V
1000
Coss Crss
100 1 10 VDS, Drain-to-Source Voltage (V) 100
0
20
40
60
80
100
120
QG Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFB/S/SL4410PbF
1000
1000
OPERATION IN THIS AREA LIMITED BY R DS(on) 100µsec 1msec
100 T J = 175°C
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
100
10
T J = 25°C
10msec 10 DC Tc = 25°C Tj = 175°C Single Pulse 1 0 1 10 100 1000
VGS = 0V 1 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VSD, Source-to-Drain Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
Fig 8. Maximum Safe Operating Area
130
100 Limited By Package 75
125
ID, Drain Current (A)
120
50
115
110
25
105
0 25 50 75 100 125 150 175 T C , Case Temperature (°C)
100 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs. Case Temperature
2.0
Fig 10. Drain-to-Source Breakdown Voltage
900
EAS , Single Pulse Avalanche Energy (mJ)
800 700 600 500 400 300 200 100 0
1.5
ID 6.7A 9.7A BOTTOM 58A TOP
Energy (µJ)
1.0
0.5
0.0 0 20 40 60 80 100 120
25
50
75
100
125
150
175
VDS, Drain-to-Source Voltage (V)
Starting T J , Junction Temperature (°C)
4
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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IRFB/S/SL4410PbF
1
D = 0.50
Thermal Response ( Z thJC )
0.1
0.20 0.10 0.05
0.01
0.02 0.01
τJ
R1 R1 τJ τ1 τ2
R2 R2 τC τ
Ri (°C/W) τi (sec) 0.2736 0.000376 0.3376 0.004143
τ1
τ2
0.001
SINGLE PULSE ( THERMAL RESPONSE )
Ci= τi/Ri Ci i/Ri
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
1E-006 1E-005 0.0001 0.001 0.01 0.1
0.0001
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Avalanche Current (A)
100
Duty Cycle = Single Pulse 0.01
10
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆ Tj = 150°C and Tstart =25°C (Single Pulse)
0.05 0.10
1
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Τ j = 25°C and Tstart = 150°C.
0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
250
EAR , Avalanche Energy (mJ)
200
TOP Single Pulse BOTTOM 1% Duty Cycle ID = 58A
150
100
50
0 25 50 75 100 125 150 175
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long as neither Tjmax nor Iav (max) is exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav
Starting T J , Junction Temperature (°C)
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFB/S/SL4410PbF
5.0
20
VGS(th) Gate threshold Voltage (V)
4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 200
15
IRRM (A)
ID = 150µA ID = 250µA ID = 1.0mA ID = 1.0A
10
5
IF = 19A VR = 85V T = 25°C _____ J T = 125°C ---------J
0 100 200 300 400 500 600 700 800 900 1000 dif/dt (A/µs)
T J , Temperature ( °C )
Fig 16. Threshold Voltage vs. Temperature
20
Fig. 17 - Typical Recovery Current vs. dif/dt
400 350
15
300 250
IRRM (A)
Qrr (nC)
10
200 150
5
IF = 38A V = 85V R T = 25°C _____ J TJ = 125°C ----------
100 50 0
IF = 19A VR = 85V T = 25°C _____ J T = 125°C ---------J
0 100 200 300 400 500 600 700 800 900 1000 dif/dt (A/µs)
100 200 300 400 500 600 700 800 900 1000 dif/dt (A/µs)
Fig. 18 - Typical Recovery Current vs. dif/dt
400 350 300 250
Qrr (nC)
Fig. 19 - Typical Stored Charge vs. dif/dt
200 150 100 50 0 100 200 300 400 500 600 700 800 900 1000 dif/dt (A/µs)
I = 38A F V = 85V R TJ = 25°C _____ TJ = 125°C ----------
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFB/S/SL4410PbF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
• • • • dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple ≤ 5% ISD
* VGS = 5V for Logic Level Devices Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01Ω
I AS
Fig 21a. Unclamped Inductive Test Circuit
LD VDS
Fig 21b. Unclamped Inductive Waveforms
+
VDD D.U.T VGS Pulse Width < 1µs Duty Factor < 0.1%
90%
VDS
10%
VGS
td(on) tr td(off) tf
Fig 22a. Switching Time Test Circuit
Fig 22b. Switching Time Waveforms
Id Vds Vgs
L
0
DUT 1K
VCC
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
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Fig 23a. Gate Charge Test Circuit
Fig 23b. Gate Charge Waveform
7
IRFB/S/SL4410PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
@Y6HQG@) UCDTÃDTÃ6IÃDSA Ã GPUÃ8P9@Ã &'( 6TT@H7G@9ÃPIÃXXÃ (Ã! DIÃUC@Ã6TT@H7G`ÃGDI@ÃÅ8Å Ir)ÃÅQÅÃvÃhriyÃyvrÃvv vqvphrÃÅGrhqÃÃA
rrÅ
DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@
Q6SUÃIVH7@S
96U@Ã8P9@ `@6SÃÃ2Ã! X@@FÃ ( GDI@Ã8
TO-220AB packages are not recommended for Surface Mount Application.
8
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IRFB/S/SL4410PbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
@Y6HQG@) UCDTÃDTÃ6IÃDSG" "G GPUÃ8P9@Ã &'( 6TT@H7G@9ÃPIÃXXÃ (Ã ((& DIÃUC@Ã6TT@H7G`ÃGDI@ÃÅ8Å DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@ Q6SUÃIVH7@S
96U@Ã8P9@ `@6SÃ&Ã2Ã ((& X@@FÃ ( GDI@Ã8
25
DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@ Q6SUÃIVH7@S
96U@Ã8P9@ QÃ2Ã9@TDBI6U@TÃG@69AS@@ QSP9V8UÃPQUDPI6G `@6SÃ&Ã2Ã ((& X@@FÃ ( 6Ã2Ã6TT@H7G`ÃTDU@Ã8P9@
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9
IRFB/S/SL4410PbF
Dimensions are shown in millimeters (inches)
D2Pak (TO-263AB) Package Outline
D2Pak (TO-263AB) Part Marking Information
UCDTÃDTÃ6IÃDSA$"TÃXDUC GPUÃ8P9@Ã'!# 6TT@H7G@9ÃPIÃXXÃ!Ã! DIÃUC@Ã6TT@H7G`ÃGDI@ÃÅGÅ DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@ Q6SUÃIVH7@S A$"T 96U@Ã8P9@ `@6SÃÃ2Ã! X@@FÃ! GDI@ÃG
25
DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPUÃ8P9@
10
Q6SUÃIVH7@S A$"T 96U@Ã8P9@ QÃ2Ã9@TDBI6U@TÃG@69ÃÃAS@@ QSP9V8UÃPQUDPI6G `@6SÃÃ2Ã! X@@FÃ! 6Ã2Ã6TT@H7G`ÃTDU@Ã8P9@
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IRFB/S/SL4410PbF
D2Pak (TO-263AB) Tape & Reel Information
TRR
1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153)
1.60 (.063) 1.50 (.059)
0.368 (.0145) 0.342 (.0135)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
11.60 (.457) 11.40 (.449)
15.42 (.609) 15.22 (.601)
24.30 (.957) 23.90 (.941)
TRL
10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 16.10 (.634) 15.90 (.626) 4.72 (.136) 4.52 (.178)
FEED DIRECTION
13.50 (.532) 12.80 (.504)
27.40 (1.079) 23.90 (.941)
4
330.00 (14.173) MAX.
60.00 (2.362) MIN.
NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039) 24.40 (.961) 3
30.40 (1.197) MAX. 4
Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.05/07
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