IRFU3411PBF

PD - 95371A l l l l l l l Advanced Process Technology Ultra Low On-Resistance Dynamic dv/dt Rating 175°C Operating Temperature Fast Switching Fully Avalanche Rated Lead-Free G IRFR3411PbF IRFU3411PbF HEXFET® Power MOSFET D VDSS = 100V RDS(on) = 44mΩ Description Advanced HEXFET® Power MOSFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The D-Pak is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead, I-Pak, version (IRFU series) is for throughhole mounting applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount applications. S ID = 32A D-Pak IRFR3411 I-Pak IRFU3411 Absolute Maximum Ratings Parameter ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current  Power Dissipation Linear Derating Factor Gate-to-Source Voltage Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt ƒ Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Max. 32 23 110 130 0.83 ± 20 16 13 7.0 -55 to + 175 300 (1.6mm from case ) Units A W W/°C V A mJ V/ns °C Thermal Resistance Parameter RθJC RθJA RθJA Junction-to-Case Junction-to-Ambient (PCB mount)* Junction-to-Ambient Typ. ––– ––– ––– Max. 1.2 50 110 Units °C/W www.irf.com 1 12/03/04 IRFR/U3411PbF Electrical Characteristics @ TJ = 25°C (unless otherwise specified) V(BR)DSS ∆V(BR)DSS/∆TJ RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss EAS Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Single Pulse Avalanche Energy ‚ Min. Typ. Max. Units Conditions 100 ––– ––– V VGS = 0V, I D = 250µA ––– 0.12 ––– V/°C Reference to 25°C, I D = 1mA ––– 36 44 mΩ VGS = 10V, ID = 16A „ 2.0 ––– 4.0 V VDS = VGS , ID = 250µA 21 ––– ––– S VDS = 50V, ID = 16A„ ––– ––– 25 VDS = 100V, VGS = 0V µA ––– ––– 250 VDS = 80V, VGS = 0V, TJ = 150°C ––– ––– 100 VGS = 20V nA ––– ––– -100 VGS = -20V ––– 48 71 ID = 16A ––– 9.0 14 nC VDS = 80V ––– 14 21 VGS = 10V, See Fig. 6 and 13 ––– 11 ––– VDD = 50V ––– 35 ––– ID = 16A ns ––– 39 ––– RG = 5.1Ω ––– 35 ––– VGS = 10V, See Fig. 10 „ Between lead, 4.5 ––– ––– 6mm (0.25in.) nH G from package ––– 7.5 ––– and center of die contact ––– 1960 ––– VGS = 0V ––– 250 ––– VDS = 25V ––– 40 ––– pF ƒ = 1.0MHz, See Fig. 5 ––– 700… 185† mJ IAS = 16A, L = 1.5mH D S Source-Drain Ratings and Characteristics IS ISM VSD trr Qrr ton Notes: Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time Min. Typ. Max. Units Conditions D MOSFET symbol 33 ––– ––– showing the A G integral reverse ––– ––– 110 S p-n junction diode. ––– ––– 1.2 V TJ = 25°C, IS = 16A, VGS = 0V „ ––– 115 170 ns TJ = 25°C, IF = 16A ––– 505 760 nC di/dt = 100A/µs „ Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)  Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11) ‚ Starting TJ = 25°C, L =1.5mH RG = 25Ω, IAS = 16A. (See Figure 12) ƒ ISD ≤ 16A, di/dt ≤ 340A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. „ Pulse width ≤ 400µs; duty cycle ≤ 2%. … This is a typical value at device destruction and represents operation outside rated limits. † This is a calculated value limited to TJ = 175°C . * When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint dering techniques refer to application note #AN-994. 2 www.irf.com IRFR/U3411PbF 1000 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP 1000 I D , Drain-to-Source Current (A) 100 I D , Drain-to-Source Current (A) VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP 100 4.5V 10 10 4.5V 1 0.1 20µs PULSE WIDTH TJ = 25 °C 1 10 100 1 0.1 20µs PULSE WIDTH TJ = 175 °C 1 10 100 VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 1000 3.5 RDS(on) , Drain-to-Source On Resistance (Normalized) ID = 33A I D , Drain-to-Source Current (A) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -60 -40 -20 0 TJ = 25 ° C 100 TJ = 175 ° C 10 4.0 V DS = 50V 20µs PULSE WIDTH 5.0 6.0 7.0 8.0 9.0 VGS = 10V 20 40 60 80 100 120 140 160 180 VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature ( °C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3 IRFR/U3411PbF 3000 2500 VGS , Gate-to-Source Voltage (V) VGS = 0V, f = 1MHz Ciss = Cgs + Cgd , Cds SHORTED Crss = Cgd Coss = Cds + Cgd 20 ID = 16A VDS = 80V VDS = 50V VDS = 20V 16 C, Capacitance (pF) 2000 Ciss 12 1500 8 1000 Coss 500 4 Crss 0 0 FOR TEST CIRCUIT SEE FIGURE 13 0 20 40 60 80 1 10 100 VDS , Drain-to-Source Voltage (V) QG , Total Gate Charge (nC) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 1000 1000 OPERATION IN THIS AREA LIMITED BY R DS(on) ISD , Reverse Drain Current (A) 100 TJ = 175 ° C 10 ID, Drain-to-Source Current (A) 100 10 100µsec 1msec TJ = 25 ° C 1 1 T A = 25°C T J = 175°C Single Pulse 10msec 0.1 0.2 V GS = 0 V 0.6 1.0 1.4 1.8 0.1 1 10 100 1000 VDS , Drain-toSource Voltage (V) VSD ,Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRFR/U3411PbF 35 VDS 30 RD VGS RG V GS Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % D.U.T. + 25 -VDD ID , Drain Current (A) 20 15 10 Fig 10a. Switching Time Test Circuit VDS 90% 5 0 25 50 75 100 125 150 175 TC , Case Temperature ( ° C) Fig 9. Maximum Drain Current Vs. Case Temperature 10% VGS td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms 10 (Z thJC ) 1 D = 0.50 Thermal Response 0.20 0.10 0.1 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = 2. Peak T 0.01 0.00001 0.0001 0.001 0.01 t1/ t 2 +T C 1 P DM t1 t2 J = P DM x Z thJC 0.1 t1, Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRFR/U3411PbF 15V EAS , Single Pulse Avalanche Energy (mJ) 400 VDS L DRIVER ID 6.5A 11.3A BOTTOM 16A TOP 300 RG 20V D.U.T IAS tp + V - DD A 200 0.01Ω Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp 100 0 25 50 75 100 125 150 175 Starting TJ , Junction Temperature ( °C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ QG 12V .2µF .3µF VGS QGS VG QGD VGS 3mA D.U.T. + V - DS IG ID Charge Current Sampling Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit 6 www.irf.com IRFR/U3411PbF Peak Diode Recovery dv/dt Test Circuit D.U.T* + ƒ + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer ‚ - „ +  RG VGS • dv/dt controlled by RG • ISD controlled by Duty Factor "D" • D.U.T. - Device Under Test + VDD * Reverse Polarity of D.U.T for P-Channel Driver Gate Drive P.W. Period D= P.W. Period [VGS=10V ] *** D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt [VDD] Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple ≤ 5% [ISD ] *** VGS = 5.0V for Logic Level and 3V Drive Devices Fig 14. For N-channel HEXFET® power MOSFETs www.irf.com 7 IRFR/U3411PbF D-Pak (TO-252AA) Package Outline D-Pak (TO-252AA) Part Marking Information EXAMPLE: THIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 1234 ASSEMBLED ON WW 16, 1999 IN THE ASSEMBLY LINE "A" Note: "P" in ass embly line pos ition indicates "Lead-Free" PART NUMBER INTERNAT IONAL RECTIFIER LOGO IRFU120 12 916A 34 ASSEMBLY LOT CODE DATE CODE YEAR 9 = 1999 WEEK 16 LINE A OR PART NUMBER INT ERNATIONAL RECTIFIER LOGO IRFU120 12 34 DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPT IONAL) YEAR 9 = 1999 WEEK 16 A = ASSEMBLY S IT E CODE ASSEMBLY LOT CODE 8 www.irf.com IRFR/U3411PbF I-Pak (TO-251AA) Package Outline ( Dimensions are shown in millimeters (inches) ) I-Pak (TO-251AA) Part Marking Information EXAMPLE: T HIS IS AN IRFU120 WIT H AS SEMBLY LOT CODE 5678 AS S EMB LED ON WW 19, 1999 IN T HE ASS EMB LY LINE "A" Note: "P" in ass embly line pos ition indicates "Lead-Free" INT ERNAT IONAL RECT IFIER LOGO PART NUMBER IRF U120 919A 56 78 AS S EMB LY LOT CODE DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A OR INTERNATIONAL RECTIFIER LOGO PART NUMBER IRFU120 56 78 AS S EMBLY LOT CODE DATE CODE P = DES IGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 9 = 1999 WEEK 19 A = AS S EMBL Y S ITE CODE www.irf.com 9 IRFR/U3411PbF D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 16.3 ( .641 ) 15.7 ( .619 ) 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q101] market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.12/04 10 www.irf.com