IRFZ48ZSPBF

PD - 95574 AUTOMOTIVE MOSFET Features Advanced Process Technology Ultra Low On-Resistance Dynamic dv/dt Rating 175°C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax Lead-Free IRFZ48ZPbF IRFZ48ZSPbF IRFZ48ZLPbF HEXFET® Power MOSFET D VDSS = 55V RDS(on) = 11mΩ G S Description Specifically designed for Automotive applications, this HEXFET® Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 175°C junction operating temperature, fast switching speed and improved repetitive avalanche rating . These features combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications. ID = 61A TO-220AB IRFZ48Z D2Pak IRFZ48ZS TO-262 IRFZ48ZL Absolute Maximum Ratings Parameter ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS EAS EAS (tested) IAR EAR TJ TSTG Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (See Fig. 9) Pulsed Drain Current Max. 61 43 240 91 0.61 ± 20 73 120 See Fig.12a,12b,15,16 -55 to + 175 Units A c Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy (Thermally Limited) Single Pulse Avalanche Energy Tested Value Avalanche Current W W/°C V mJ A mJ °C c i d Repetitive Avalanche Energy Operating Junction and Storage Temperature Range h Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 screw 300 (1.6mm from case ) 10 lbf•in (1.1N•m) Thermal Resistance Parameter RθJC RθCS RθJA RθJA Junction-to-Case Case-to-Sink, Flat, Greased Surface Junction-to-Ambient Junction-to-Ambient (PCB Mount, steady state) Typ. ––– 0.50 ––– ––– Max. 1.64 ––– 62 40 Units °C/W j HEXFET® is a registered trademark of International Rectifier. www.irf.com 1 07/19/04 IRFZ48Z/S/LPbF Static @ TJ = 25°C (unless otherwise specified) Parameter V(BR)DSS ∆ΒVDSS/∆TJ RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Coss Coss Coss eff. Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance Min. Typ. Max. Units 55 ––– ––– 2.0 24 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 0.054 ––– 8.6 11 ––– 4.0 ––– ––– ––– 20 ––– 250 ––– 200 ––– -200 43 64 11 16 16 24 15 ––– 69 ––– 35 ––– 39 ––– 4.5 ––– 7.5 1720 300 160 1020 230 380 ––– ––– ––– ––– ––– ––– ––– pF V V/°C mΩ V S µA nA nC Conditions VGS = 0V, ID = 250µA Reference to 25°C, ID = 1mA VGS = 10V, ID = 37A VDS = VGS, ID = 250µA VDS = 25V, ID = 37A VDS = 55V, VGS = 0V VDS = 55V, VGS = 0V, TJ = 125°C VGS = 20V VGS = -20V ID = 37A VDS = 44V VGS = 10V VDD = 28V ID = 37A RG = 12Ω VGS = 10V Between lead, D f f f ns nH 6mm (0.25in.) from package G S and center of die contact VGS = 0V VDS = 25V ƒ = 1.0MHz, See Fig. 5 VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz VGS = 0V, VDS = 44V, ƒ = 1.0MHz VGS = 0V, VDS = 0V to 44V Diode Characteristics Parameter IS ISM VSD trr Qrr ton Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time Min. Typ. Max. Units ––– ––– ––– ––– ––– ––– ––– ––– 20 13 61 A 240 1.3 31 20 V ns nC Conditions MOSFET symbol showing the integral reverse G D Ù p-n junction diode. TJ = 25°C, IS = 37A, VGS = 0V TJ = 25°C, IF = 37A, VDD = 30V di/dt = 100A/µs f S f Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes:  Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11). ‚ Limited by TJmax, starting TJ = 25°C, L =0.11mH, RG = 25Ω, IAS = 37A, VGS =10V. Part not recommended for use above this value. ƒ ISD ≤ 37A, di/dt ≤ 920A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. „ Pulse width ≤ 1.0ms; duty cycle ≤ 2%. … Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS . † Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance. ‡ This value determined from sample failure population. 100% tested to this value in production. ˆ This is applied to D2Pak, when mounted on 1" square PCB ( FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994. 2 www.irf.com IRFZ48Z/S/LPbF 1000 TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V 1000 TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V ID, Drain-to-Source Current (A) 100 BOTTOM ID, Drain-to-Source Current (A) 100 BOTTOM 4.5V 10 10 4.5V 30µs PULSE WIDTH Tj = 25°C 0.1 1 10 100 1000 30µs PULSE WIDTH Tj = 175°C 1 0.1 1 10 100 1000 V DS, Drain-to-Source Voltage (V) 1 V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 1000 Gfs, Forward Transconductance (S) 60 T J = 25°C ID, Drain-to-Source Current (Α) 50 100 T J = 175°C 40 30 T J = 175°C 20 10 T J = 25°C VDS = 25V 30µs PULSE WIDTH 1.0 4 5 6 7 8 9 10 10 V DS = 10V 0 0 10 20 30 40 ID,Drain-to-Source Current (A) VGS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance vs. Drain Current www.irf.com 3 IRFZ48Z/S/LPbF 10000 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd 12.0 ID= 37A VGS, Gate-to-Source Voltage (V) 10.0 VDS= 44V VDS= 28V VDS= 11V C, Capacitance(pF) Ciss 1000 8.0 6.0 Coss Crss 100 1 10 100 4.0 2.0 0.0 0 10 20 30 40 50 VDS, Drain-to-Source Voltage (V) QG Total Gate Charge (nC) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 1000 1000 OPERATION IN THIS AREA LIMITED BY R DS(on) ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 100 T J = 175°C 100 100µsec 10 TJ = 25°C 10 Tc = 25°C Tj = 175°C Single Pulse 1 1 10 1msec 10msec VGS = 0V 1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VSD, Source-to-Drain Voltage (V) 100 VDS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRFZ48Z/S/LPbF 70 RDS(on) , Drain-to-Source On Resistance (Normalized) 2.5 60 ID, Drain Current (A) ID = 37A VGS = 10V 2.0 50 40 30 20 10 0 25 50 75 100 125 150 175 T C , Case Temperature (°C) 1.5 1.0 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 T J , Junction Temperature (°C) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Normalized On-Resistance vs. Temperature 10 Thermal Response ( Z thJC ) 1 D = 0.50 0.20 0.10 0.1 0.05 0.02 0.01 τJ R1 R1 τJ τ1 τ2 R2 R2 τC τ Ri (°C/W) τi (sec) 0.9848 0.000451 0.6546 0.002487 τ1 τ2 0.01 SINGLE PULSE ( THERMAL RESPONSE ) 0.001 1E-006 1E-005 0.0001 Ci= τi/Ri Ci= i/Ri Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRFZ48Z/S/LPbF 300 EAS , Single Pulse Avalanche Energy (mJ) 15V 250 VDS L DRIVER ID 3.5A 4.9A BOTTOM 37A TOP 200 RG 20V VGS D.U.T IAS tp + V - DD A 150 0.01Ω 100 Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp 50 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) I AS Fig 12b. Unclamped Inductive Waveforms QG Fig 12c. Maximum Avalanche Energy vs. Drain Current 10 V QGS VG QGD VGS(th) Gate threshold Voltage (V) 4.0 3.5 3.0 Charge Fig 13a. Basic Gate Charge Waveform ID = 250µA 2.5 2.0 L 0 1.5 DUT 1K VCC 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 200 T J , Temperature ( °C ) Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage vs. Temperature 6 www.irf.com IRFZ48Z/S/LPbF 1000 Duty Cycle = Single Pulse Avalanche Current (A) 100 0.01 10 Allowed avalanche Current vs avalanche pulsewidth, tav assuming ∆ Tj = 25°C due to avalanche losses 0.05 0.10 1 0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 15. Typical Avalanche Current vs.Pulsewidth 80 EAR , Avalanche Energy (mJ) TOP Single Pulse BOTTOM 1% Duty Cycle ID = 37A 60 40 20 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 15, 16). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav ) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav Fig 16. Maximum Avalanche Energy vs. Temperature www.irf.com 7 IRFZ48Z/S/LPbF Driver Gate Drive D.U.T + P.W. Period D= P.W. Period VGS=10V ƒ + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt ‚ - „ +  RG • • • • dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD VDD + - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs RD V DS VGS RG 10V Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % D.U.T. + -VDD Fig 18a. Switching Time Test Circuit VDS 90% 10% VGS td(on) tr t d(off) tf Fig 18b. Switching Time Waveforms 8 www.irf.com IRFZ48Z/S/LPbF TO-220AB Package Outline Dimensions are shown in millimeters (inches) 2.87 (.113) 2.62 (.103) 10.54 (.415) 10.29 (.405) 3.78 (.149) 3.54 (.139) -A6.47 (.255) 6.10 (.240) -B4.69 (.185) 4.20 (.165) 1.32 (.052) 1.22 (.048) 4 15.24 (.600) 14.84 (.584) LEAD ASSIGNMENTS 1.15 (.045) MIN 1 2 3 LEAD ASSIGNMENTS IGBTs, CoPACK 1 - GATE 2 - DRAIN 1- GATE 1- GATE 32- DRAINSOURCE 2- COLLECTOR 3- EMITTER 3- SOURCE 4 - DRAIN HEXFET 14.09 (.555) 13.47 (.530) 4- DRAIN 4.06 (.160) 3.55 (.140) 4- COLLECTOR 3X 3X 1.40 (.055) 1.15 (.045) 0.93 (.037) 0.69 (.027) M BAM 3X 0.55 (.022) 0.46 (.018) 0.36 (.014) 2.54 (.100) 2X NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH 2.92 (.115) 2.64 (.104) 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. TO-220AB Part Marking Information E XAMPL E : T HIS IS AN IR F 1010 L OT CODE 1789 AS S E MB LE D ON WW 19, 1997 IN T H E AS S E MB L Y LINE "C" INT E R NAT IONAL R E CT IF IE R L OGO AS S E MB L Y L OT CODE PAR T NU MB E R Note: "P" in assembly line position indicates "Lead-Free" DAT E CODE YE AR 7 = 1997 WE E K 19 L INE C www.irf.com 9 IRFZ48Z/S/LPbF D2Pak Package Outline Dimensions are shown in millimeters (inches) D2Pak Part Marking Information T HIS IS AN IRF 530S WIT H LOT CODE 8024 AS S E MB LE D ON WW 02, 2000 IN T HE AS S E MB LY LINE "L" Note: "P" in as s embly line pos ition indicates "Lead-F ree" INT E RNAT IONAL RE CT IF IE R L OGO AS S E MB LY L OT CODE PAR T NUMB E R F 530S DAT E CODE YE AR 0 = 2000 WE E K 02 L INE L OR INT ER NAT IONAL R ECT IF IER LOGO AS S EMB LY LOT CODE PART NUMB ER F 530S DAT E CODE P = DES IGNAT ES LEAD-F REE PRODU CT (OPT IONAL) YEAR 0 = 2000 WEEK 02 A = AS S EMB L Y S IT E CODE 10 www.irf.com IRFZ48Z/S/LPbF TO-262 Package Outline Dimensions are shown in millimeters (inches) TO-262 Part Marking Information E XAMPLE : T HIS IS AN IR L 3103L L OT CODE 1789 AS S E MB L E D ON WW 19, 1997 IN T HE AS S E MB LY LINE "C" Note: "P" in as s embly line pos ition indicates "L ead-F ree" INT ER NAT IONAL RE CT IF IE R LOGO AS S E MB LY L OT CODE PAR T NU MB ER DAT E CODE YE AR 7 = 1997 WE E K 19 L INE C OR INT E R NAT IONAL R E CT IF IE R LOGO AS S E MB L Y L OT CODE PAR T NU MB ER DAT E CODE P = DE S IGNAT E S L EAD-F R E E PR ODU CT (OPT IONAL ) YE AR 7 = 1997 WE E K 19 A = AS S E MB L Y S IT E CODE www.irf.com 11 IRFZ48Z/S/LPbF D2Pak Tape & Reel Information Dimensions are shown in millimeters (inches) TRR 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135) FEED DIRECTION 1.85 (.073) 1.65 (.065) 11.60 (.457) 11.40 (.449) 15.42 (.609) 15.22 (.601) 24.30 (.957) 23.90 (.941) TRL 10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 16.10 (.634) 15.90 (.626) 4.72 (.136) 4.52 (.178) FEED DIRECTION 13.50 (.532) 12.80 (.504) 27.40 (1.079) 23.90 (.941) 4 330.00 (14.173) MAX. 60.00 (2.362) MIN. NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. 30.40 (1.197) MAX. 26.40 (1.039) 24.40 (.961) 3 4 TO-220AB package is not recommended for Surface Mount Application. Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q101] market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 07/04 12 www.irf.com