IRL1404SPFF

PD - 95148 Advanced Process Technology Ultra Low On-Resistance l Dynamic dv/dt Rating l 175°C Operating Temperature l Fast Switching l Fully Avalanche Rated l Lead-Free Description l l HEXFET® Power MOSFET D IRL1404SPbF IRL1404LPbF VDSS = 40V RDS(on) = 0.004Ω G S Seventh Generation HEXFET® power MOSFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The D2Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible onresistance in any existing surface mount package. The D2Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRL1404L) is available for low- ID = 160A† D2Pak IRL1404S TO-262 IRL1404L Absolute Maximum Ratings ID @ TC = 25°C ID @ TC = 100°C IDM PD @TA = 25°C PD @TC = 25°C VGS EAS IAR EAR dv/dt TJ TSTG Parameter Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current  Power Dissipation Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy‚ Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt ƒ Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Max. 160† 110† 640 3.8 200 1.3 ± 20 520 95 20 5.0 -55 to + 175 300 (1.6mm from case) Units A W W W/°C V mJ A mJ V/ns °C Thermal Resistance Parameter RθJC RθCS RθJA Junction-to-Case Case-to-Sink, Flat, Greased Surface Junction-to-Ambient (PCB Mounted)‡ Typ. ––– 0.50 ––– Max. 0.75 ––– 40 Units °C/W www.irf.com 1 04/19/04 IRL1404S/LPbF Electrical Characteristics @ TJ = 25°C (unless otherwise specified) V(BR)DSS ∆V(BR)DSS/∆TJ RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Coss Coss Coss eff. Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance … Min. Typ. Max. Units Conditions 40 ––– ––– V VGS = 0V, ID = 250µA ––– 0.038 ––– V/°C Reference to 25°C, D = 1mA ––– ––– 0.004 Ω VGS = 10V, ID = 95A „ 0.0059 VGS = 4.3V, ID = 40A „ 1.0 ––– 3.0 V VDS = VGS, ID = 250µA 93 ––– ––– S VDS = 25V, ID = 95A ––– ––– 20 VDS = 40V, VGS = 0V µA ––– ––– 250 VDS = 32V, VGS = 0V, TJ = 150°C ––– ––– 200 VGS = 20V nA ––– ––– -200 VGS = -20V ––– ––– 140 ID = 95A ––– ––– 48 nC VDS = 32V ––– ––– 60 VGS = 5.0V, See Fig. 6 „ ––– 18 ––– VDD = 20V ns ––– 270 ––– ID = 95A ––– 38 ––– RG = 2.5Ω VGS = 4.5V ––– 130 ––– RD = 0.25Ω „ D Between lead, 4.5 ––– nH ––– 6mm (0.25in.) G from package 7.5 ––– ––– and center of die contact S ––– 6600 ––– VGS = 0V ––– 1700 ––– pF VDS = 25V ––– 350 ––– ƒ = 1.0MHz, See Fig. 5 ––– 6700 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz ––– 1500 ––– VGS = 0V, VDS = 32V, ƒ = 1.0MHz ––– 1500 ––– VGS = 0V, VDS = 0V to 32V Source-Drain Ratings and Characteristics IS ISM VSD trr Qrr ton Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)  Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time Min. Typ. Max. Units Conditions D MOSFET symbol ––– ––– 160† showing the A G integral reverse ––– ––– 640 S p-n junction diode. ––– ––– 1.3 V TJ = 25°C, IS = 95A, VGS = 0V „ ––– 63 94 ns TJ = 25°C, IF = 95A ––– 170 250 nC di/dt = 100A/µs „ Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) 2 www.irf.com IRL1404S/LPbF 1000 I D , Drain-to-Source Current (A) 4.3V I D , Drain-to-Source Current (A)  VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.3V TOP 1000  VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.3V TOP 4.3V 100 100 10 0.1 20µs PULSE WIDTH  T = 25 C J ° 1 10 100 10 0.1 20µs PULSE WIDTH  T = 175 C J ° 1 10 100 VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 1000 2.5 R DS(on) , Drain-to-Source On Resistance (Normalized) ID = 160A  I D , Drain-to-Source Current (A) TJ = 25 ° C  TJ = 175 ° C  2.0 1.5 1.0 0.5 100 4.0  V DS = 15V 20µs PULSE WIDTH 7.0 5.0 6.0 8.0 VGS , Gate-to-Source Voltage (V) 0.0 -60 -40 -20 VGS = 10V  0 20 40 60 80 100 120 140 160 180 TJ , Junction Temperature ( ° C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3 IRL1404S/LPbF 10000 VGS , Gate-to-Source Voltage (V) 8000  VGS = 0V, f = 1MHz Ciss = Cgs + Cgd , Cds SHORTED Crss = Cgd Coss = Cds + Cgd 20 ID = 95A  16  VDS = 32V VDS = 20V C, Capacitance (pF) Ciss  6000 12 4000 8 2000 C oss C rss 1 10 100 4 0 0 FOR TEST CIRCUIT  SEE FIGURE 13 0 100 200 300 400 500 VDS , Drain-to-Source Voltage (V) QG , Total Gate Charge (nC) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 1000 10000 ISD , Reverse Drain Current (A) OPERATION IN THIS AREA LIMITED BY R  DS(on) 100 TJ = 175 ° C  I D , Drain Current (A) 1000  10us  100us  1ms 10 TJ = 25 ° C  100 1 0.0 V GS = 0 V  0.5 1.0 1.5 2.0 2.5 3.0 10  TC = 25 ° C TJ = 175 ° C Single Pulse 1 10  10ms 100 VSD ,Source-to-Drain Voltage (V) VDS , Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRL1404S/LPbF 160  PACKAGE LIMITED BY VGS 120 VDS RD I D , Drain Current (A) RG D.U.T. + -VDD 10V 80 Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % 40 VDS 90% 0 25 50 75 100 125 150 175 TC , Case Temperature ( °C) 10% VGS td(on) tr t d(off) tf Fig 9. Maximum Drain Current Vs. Case Temperature 1 D = 0.50 Thermal Response (Z thJC ) 0.20 0.1 0.10 0.05 0.02 0.01 0.01 SINGLE PULSE  (THERMAL RESPONSE) 0.001 0.00001  Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.1 0.0001 0.001 0.01  PDM t1 t2 1 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRL1404S/LPbF 1 5V EAS , Single Pulse Avalanche Energy (mJ) 1200 VDS L D R IV E R 1000  TOP BOTTOM ID 39A 67A 95A 800 RG 20V D .U .T IA S tp + V - DD A 600 0 .0 1 Ω Fig 12a. Unclamped Inductive Test Circuit V (B R )D SS tp 400 200 0 25 Starting TJ , Junction Temperature( ° C) 50 75 100 125 150 175 IAS Fig 12b. Unclamped Inductive Waveforms Fig 12c. Maximum Avalanche Energy Vs. Drain Current 10 V QGS VG QG QGD 12V Current Regulator Same Type as D.U.T. 50KΩ .2µF .3µF D.U.T. VGS 3mA + V - DS Charge IG ID Current Sampling Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit 6 www.irf.com IRL1404S/LPbF Peak Diode Recovery dv/dt Test Circuit D.U.T* + ƒ + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer ‚ - „ +  RG VGS • dv/dt controlled by RG • ISD controlled by Duty Factor "D" • D.U.T. - Device Under Test + VDD * Reverse Polarity of D.U.T for P-Channel Driver Gate Drive P.W. Period D= P.W. Period [VGS=10V ] *** D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt [VDD] Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple ≤ 5% [ ISD ] *** VGS = 5.0V for Logic Level and 3V Drive Devices Fig 14. For N-channel HEXFET® power MOSFETs www.irf.com 7 IRL1404S/LPbF D2Pak Package Outline Dimensions are shown in millimeters (inches) D2Pak Part Marking Information (Lead-Free) T H I S IS AN IR F 5 30 S WIT H L OT COD E 80 24 AS S E MB L E D ON WW 0 2, 20 00 IN T H E AS S E MB L Y L IN E "L " N ote: "P " in as s embly line pos ition indicates "L ead-F ree" IN T E R N AT ION AL R E CT IF IE R L OGO AS S E MB L Y L OT COD E P AR T N U MB E R F 53 0S D AT E COD E YE AR 0 = 2 00 0 WE E K 02 L IN E L OR INT E R N AT IONAL R E CT IF IE R L OGO AS S E MB L Y L OT CODE P AR T NU MB E R F 530S DAT E CODE P = DE S IGN AT E S L E AD -F R E E P R ODU CT (OPT IONAL ) YE AR 0 = 2 000 WE E K 0 2 A = AS S E MB L Y S IT E CODE 8 www.irf.com IRL1404S/LPbF TO-262 Package Outline TO-262 Part Marking Information E XAMP L E : T H IS IS AN IR L 3103L L OT CODE 1789 AS S E MB L E D ON WW 19, 1997 IN T H E AS S E MB L Y L INE "C" Note: "P " in as s embly line pos ition indicates "L ead-F ree" INT E R NAT IONAL R E CT IF IE R L OGO AS S E MB L Y L OT CODE P AR T NU MB E R DAT E CODE YE AR 7 = 1997 WE E K 19 L INE C OR INT E R NAT IONAL R E CT IF IE R L OGO AS S E MB L Y L OT CODE P AR T NU MB E R DAT E CODE P = DE S IGNAT E S L E AD-F R E E P R ODU CT (OP T IONAL ) YE AR 7 = 1997 WE E K 19 A = AS S E MB L Y S IT E CODE www.irf.com 9 IRL1404S/LPbF D2Pak Tape & Reel Information Dimensions are shown in millimeters (inches) TR R 1 .6 0 (.0 63 ) 1 .5 0 (.0 59 ) 4 .10 (.16 1 ) 3 .90 (.15 3 ) 1 .6 0 (.0 6 3 ) 1 .5 0 (.0 5 9 ) 0 .3 6 8 (.0 1 4 5 ) 0 .3 4 2 (.0 1 3 5 ) F E E D D IR E C TIO N 1 .8 5 (.0 7 3 ) 1 .6 5 (.0 6 5 ) 1 1 .6 0 (.4 5 7 ) 1 1 .4 0 (.4 4 9 ) 1 5 .4 2 (.6 0 9 ) 1 5 .2 2 (.6 0 1 ) 2 4 .3 0 (.9 5 7 ) 2 3 .9 0 (.9 4 1 ) TRL 1 0 .9 0 (.4 2 9 ) 1 0 .7 0 (.4 2 1 ) 1 .7 5 (.0 6 9 ) 1 .2 5 (.0 4 9 ) 1 6 .1 0 ( .6 3 4 ) 1 5 .9 0 ( .6 2 6 ) 4 .7 2 (.1 3 6 ) 4 .5 2 (.1 7 8 ) F E E D D IR E C T IO N 1 3 .5 0 (.5 3 2 ) 1 2 .8 0 (.5 0 4 ) 2 7 .4 0 ( 1.0 7 9 ) 2 3 .9 0 ( .9 4 1 ) 4 33 0.00 (14.173) M A X. 60 .0 0 (2 .3 6 2) M IN . N O TES : 1 . C O M F O R M S T O E IA - 41 8 . 2 . C O N T R O LL IN G D IM E N S IO N : M IL L IM E T E R . 3 . D IM E N S IO N M E A S U R E D @ H U B . 4 . IN C L U D E S F L A N G E D IS T O R T IO N @ O U T E R E D G E . 26.40 (1.039) 24.40 (.961) 3 3 0 .40 ( 1.1 9 7 ) M A X. 4 Notes:  Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 ) ‚ Starting TJ = 25°C, L = 0.35mH RG = 25Ω, IAS = 95A. (See Figure 12) ƒ ISD ≤ 95A, di/dt ≤ 160A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C „ Pulse width ≤ 300µs; duty cycle ≤ 2%. † Calculated continuous current based on maximum allowable junction temperature; for recommended current-handing of the package refer to Design Tip # 93-4. This is applied to D2Pak, When mounted on 1" square PCB (FR-4 or G-10 Material) . For recommended footprint and soldering techniques refer to application note #AN-994. ‡ … Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.04/04 10 www.irf.com Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/