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IRL8113S

IRL8113S

  • 厂商:

    IRF

  • 封装:

  • 描述:

    IRL8113S - HEXFET Power MOSFET - International Rectifier

  • 数据手册
  • 价格&库存
IRL8113S 数据手册
PD - 95821 Applications l High Frequency Synchronous Buck Converters for Computer Processor Power HEXFET® Power MOSFET IRL8113 IRL8113S IRL8113L VDSS RDS(on) max Qg (Typ.) 30V 6.0m: 23nC Benefits l Low RDS(on) at 4.5V VGS l Low Gate Charge l Fully Characterized Avalanche Voltage and Current TO-220AB IRL8113 D2Pak IRL8113S TO-262 IRL8113L Absolute Maximum Ratings Parameter VDS VGS ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C PD @TC = 100°C TJ TSTG Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Max. 30 105 Units V A c h 74 h 420 110 57 ± 20 Maximum Power Dissipation Maximum Power Dissipation Linear Derating Factor Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting Torque, 6-32 or M3 screw W 0.76 -55 to + 175 W/°C °C f 300 (1.6mm from case) 10 lbf in (1.1N m) y y Thermal Resistance Parameter RθJC RθCS RθJA RθJA Junction-to-Case i Typ. Max. 1.32 ––– 62 40 Units °C/W Case-to-Sink, Flat Greased Surface Junction-to-Ambient fi f ––– 0.50 ––– ––– Junction-to-Ambient (PCB Mount) gi Notes  through ‡ are on page 12 www.irf.com 1 1/6/04 IRL8113/S/L Static @ TJ = 25°C (unless otherwise specified) Parameter BVDSS ∆ΒVDSS/∆TJ RDS(on) VGS(th) ∆VGS(th)/∆TJ IDSS IGSS gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw Qoss td(on) tr td(off) tf Ciss Coss Crss Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) Output Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. Typ. Max. Units 30 ––– ––– ––– 1.35 ––– ––– ––– ––– ––– 86 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– -5.0 ––– ––– ––– ––– ––– 23 6.0 2.0 8.3 6.7 10 14 14 38 18 5.0 2840 620 290 ––– 0.020 4.8 5.7 ––– ––– 6.0 7.1 2.25 ––– 1.0 150 100 -100 ––– 35 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– pF VGS = 0V VDS = 15V ns nC nC VDS = 15V VGS = 4.5V ID = 17A S nA V mV/°C µA V Conditions VGS = 0V, ID = 250µA V/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 21A VGS = 4.5V, ID = 17A e e VDS = VGS, ID = 250µA VDS = 24V, VGS = 0V VDS = 24V, VGS = 0V, TJ = 125°C VGS = 20V VGS = -20V VDS = 15V, ID = 17A See Fig. 16 VDS = 16V, VGS = 0V VDD = 15V, VGS = 4.5V ID = 17A Clamped Inductive Load e ƒ = 1.0MHz Avalanche Characteristics EAS IAR EAR Parameter Single Pulse Avalanche Energy Avalanche Current Ù d Typ. ––– ––– ––– Max. 220 17 11 Units mJ A mJ Repetitive Avalanche Energy ™ ––– ––– ––– ––– ––– ––– ––– ––– 18 7.2 Diode Characteristics Parameter IS ISM VSD trr Qrr Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Min. Typ. Max. Units 105 h Conditions MOSFET symbol D A 420 1.0 27 11 V ns nC Ù showing the integral reverse G S p-n junction diode. TJ = 25°C, IS = 17A, VGS = 0V TJ = 25°C, IF = 17A, VDD = 15V di/dt = 100A/µs e e 2 www.irf.com IRL8113/S/L 1000 TOP VGS 10V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V 3.0V 1000 TOP VGS 10V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V 3.0V ID, Drain-to-Source Current (A) BOTTOM ID, Drain-to-Source Current (A) BOTTOM 100 100 3.0V 3.0V ≤ 60µs PULSE WIDTH Tj = 25°C 10 0.1 1 10 ≤ 60µs PULSE WIDTH Tj = 175°C 10 0.1 1 10 VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 1000 2.0 RDS(on) , Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (Α) ID = 42A VGS = 10V 100 1.5 T J = 175°C 10 T J = 25°C 1.0 VDS = 10V ≤ 60µs PULSE WIDTH 1 1.0 2.0 3.0 4.0 5.0 6.0 7.0 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 VGS, Gate-to-Source Voltage (V) T J , Junction Temperature (°C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature www.irf.com 3 IRL8113/S/L 100000 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd 12 ID= 17A VGS, Gate-to-Source Voltage (V) 10 8 6 4 2 0 VDS= 24V VDS= 15V C, Capacitance (pF) 10000 Ciss 1000 Coss Crss 100 1 10 100 0 10 20 30 40 50 60 VDS, Drain-to-Source Voltage (V) QG Total Gate Charge (nC) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 1000.0 10000 OPERATION IN THIS AREA LIMITED BY R DS(on) ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 1000 100.0 T J = 175°C 100 100µsec 10.0 10 1.0 T J = 25°C VGS = 0V 1 Tc = 25°C Tj = 175°C Single Pulse 0.1 1.0 10.0 1msec 10msec 100.0 0.1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VSD, Source-to-Drain Voltage (V) 0.1 VDS , Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRL8113/S/L 120 LIMITED BY PACKAGE 100 ID , Drain Current (A) 2.5 VGS(th) Gate threshold Voltage (V) 2.0 80 60 40 20 0 25 50 75 100 125 150 175 T C , Case Temperature (°C) 1.5 ID = 250µA 1.0 0.5 -75 -50 -25 0 25 50 75 100 125 150 175 T J , Temperature ( °C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Threshold Voltage vs. Temperature 1 Thermal Response ( Z thJC ) D = 0.50 0.1 0.20 0.10 0.05 R1 R1 τJ τ1 τ2 R2 R2 R3 R3 τ3 τC τ τ3 0.01 0.02 0.01 τJ Ri (°C/W) τi (sec) 0.430 0.000266 0.397 0.493 0.000685 0.007393 τ1 τ2 0.001 Ci= τi/Ri Ci= τi/Ri SINGLE PULSE ( THERMAL RESPONSE ) Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.0001 0.001 0.01 0.1 0.0001 1E-006 1E-005 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRL8113/S/L RDS(on), Drain-to -Source On Resistance ( mΩ) 40 1000 EAS, Single Pulse Avalanche Energy (mJ) ID = 21A 30 800 ID 8.8A 11A BOTTOM 17A TOP 600 20 400 10 T J = 125°C T J = 25°C 200 0 2.0 4.0 6.0 8.0 10.0 0 25 50 75 100 125 150 175 VGS, Gate-to-Source Voltage (V) Starting T J, Junction Temperature (°C) Fig 12. On-Resistance Vs. Gate Voltage Fig 13c. Maximum Avalanche Energy Vs. Drain Current LD VDS 15V VDS L DRIVER + VDD - RG VGS 20V D.U.T IAS tp + V - DD A D.U.T VGS Pulse Width < 1µs Duty Factor < 0.1% 0.01Ω Fig 13a. Unclamped Inductive Test Circuit V(BR)DSS tp Fig 14a. Switching Time Test Circuit VDS 90% 10% VGS I AS td(on) tr td(off) tf Fig 13b. Unclamped Inductive Waveforms Fig 14b. Switching Time Waveforms 6 www.irf.com IRL8113/S/L D.U.T Driver Gate Drive + P.W. Period D= P.W. Period VGS=10V ƒ + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt ‚ - „ - +  RG • • • • dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD VDD + - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs Id Current Regulator Same Type as D.U.T. Vds Vgs 50KΩ 12V .2µF .3µF D.U.T. VGS 3mA + V - DS Vgs(th) IG ID Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Test Circuit Fig 17. Gate Charge Waveform www.irf.com 7 IRL8113/S/L Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; Synchronous FET The power loss equation for Q2 is approximated by; * P =P loss conduction + P drive + P output P = Irms × Rds(on) loss + (Qg × Vg × f ) ( 2 ) Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput This can be expanded and approximated by; Q  +  oss × Vin × f + (Qrr × Vin × f )  2 *dissipated primarily in Q1. Ploss = (Irms × Rds(on ) ) 2   Qgs 2 Qgd +I× × Vin × f  +  I × × Vin × ig ig   + (Qg × Vg × f ) +  Qoss × Vin × f  2   f  This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by the power supply input buss voltage. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Qoss Characteristic 8 www.irf.com IRL8113/S/L TO-220AB Package Outline Dimensions are shown in millimeters (inches) 2.87 (.113) 2.62 (.103) 10.54 (.415) 10.29 (.405) 3.78 (.149) 3.54 (.139) -A6.47 (.255) 6.10 (.240) -B4.69 (.185) 4.20 (.165) 1.32 (.052) 1.22 (.048) 4 15.24 (.600) 14.84 (.584) 1.15 (.045) MIN 1 2 3 LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN 14.09 (.555) 13.47 (.530) 4.06 (.160) 3.55 (.140) 3X 3X 1.40 (.055) 1.15 (.045) 0.93 (.037) 0.69 (.027) M BAM 3X 0.55 (.022) 0.46 (.018) 0.36 (.014) 2.54 (.100) 2X NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH 2.92 (.115) 2.64 (.104) 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. TO-220AB Part Marking Information EXAMPLE: THIS IS AN IRF1010 LOT CODE 1789 AS S EMBLED ON WW 19, 1997 IN T HE AS S EMBLY LINE "C" INTERNATIONAL RECTIFIER LOGO AS S EMBLY LOT CODE PART NUMBER DAT E CODE YEAR 7 = 1997 WEEK 19 LINE C For GB Production EXAMPLE: T HIS IS AN IRF1010 L OT CODE 1789 AS S EMBLED ON WW 19, 1997 IN T HE AS S EMBLY LINE "C" INTERNATIONAL RECT IFIER LOGO LOT CODE PART NUMBER DAT E CODE www.irf.com 9 D2Pak Package Outline Dimensions are shown in millimeters (inches) IRL8113/S/L D2Pak Part Marking Information T HIS IS AN IRF530S WIT H LOT CODE 8024 AS S EMBLED ON WW 02, 2000 IN T HE AS S EMBLY LINE "L" INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER F530S DAT E CODE YEAR 0 = 2000 WEEK 02 LINE L PART NUMBER F530S DAT E CODE For GB Production T HIS IS AN IRF530S WIT H LOT CODE 8024 AS S EMBLED ON WW 02, 2000 IN T HE AS S EMBLY LINE "L" INT ERNAT IONAL RECT IFIER LOGO LOT CODE 10 www.irf.com IRL8113/S/L TO-262 Package Outline Dimensions are shown in millimeters (inches) IGBT 1- GATE 2- COLLECTOR TO-262 Part Marking Information EXAMPLE: THIS IS AN IRL3103L LOT CODE 1789 AS SEMBLED ON WW 19, 1997 IN T HE AS S EMBLY LINE "C" INT ERNAT IONAL RECTIFIER LOGO AS SEMBLY LOT CODE PART NUMBER DAT E CODE YEAR 7 = 1997 WEEK 19 LINE C www.irf.com 11 IRL8113/S/L D2Pak Tape & Reel Information TRR 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135) FEED DIRECTION 1.85 (.073) 1.65 (.065) 11.60 (.457) 11.40 (.449) 15.42 (.609) 15.22 (.601) 24.30 (.957) 23.90 (.941) TRL 10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 16.10 (.634) 15.90 (.626) 4.72 (.136) 4.52 (.178) FEED DIRECTION 13.50 (.532) 12.80 (.504) 27.40 (1.079) 23.90 (.941) 4 330.00 (14.173) MAX. 60.00 (2.362) MIN. NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. 26.40 (1.039) 24.40 (.961) 3 30.40 (1.197) MAX. 4 Notes:  Repetitive rating; pulse width limited by max. junction temperature. ‚ Starting TJ = 25°C, L = 1.58mH, RG = 25Ω, IAS = 21A. ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%. „ This is only applied to TO-220AB pakcage. … This is applied to D2Pak, when mounted on 1" square PCB (FR4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994. † Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 42A. ‡ Rθ is measured at TJ approximately 90°C TO-220AB package is not recommended for Surface Mount Application. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 1/04 12 www.irf.com
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