PD - 96275
IRLB3036GPbF
Applications l DC Motor Drive l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Optimized for Logic Level Drive l Very Low RDS(ON) at 4.5V VGS l Superior R*Q at 4.5V VGS l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free l Halogen-Free
HEXFET® Power MOSFET
D
G S
VDSS RDS(on) typ. max. ID (Silicon Limited) ID (Package Limited)
60V 1.9mΩ 2.4mΩ 270A 195A
c
TO-220AB IRLB3036GPbF
G
D
S
Gate
Drain
Max.
270 190 195 1100 380 2.5 ±16 8.0
Source
Units
A
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C ID @ TC = 100°C ID @ TC = 25°C IDM PD @TC = 25°C VGS dv/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Package Limited) Pulsed Drain Current Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw
c c
d
W W/°C V V/ns °C
f
-55 to + 175 300 10lb in (1.1N m) 290 See Fig. 14, 15, 22a, 22b mJ A mJ
x
x
Avalanche Characteristics
EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy
d
e
g
Thermal Resistance
Symbol
RθJC RθCS RθJA Junction-to-Case Case-to-Sink, Flat, Greased Surface Junction-to-Ambient
j
Parameter
Typ.
––– 0.50 –––
Max.
0.40 ––– 62
Units
°C/W
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1
10/16/09
IRLB3036GPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
60 ––– ––– ––– 1.0 ––– ––– ––– –––
–––
Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage ∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient RDS(on) VGS(th) IDSS IGSS RG(int) Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance
––– ––– V VGS = 0 V, ID = 250µA 0.061 ––– V/°C Reference to 25°C, ID = 5mA VGS = 1 0V, ID = 165A 1.9 2.4 mΩ 2.2 2.8 VGS = 4 .5V, ID = 140A ––– 2.5 V VDS = VGS, ID = 250µA VDS = 60V, VGS = 0 V ––– 20 µA ––– 250 VDS = 60V, VGS = 0 V, TJ = 125°C ––– 100 VGS = 1 6V nA ––– -100 VGS = -16V
g g
d
2.0
–––
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
340 ––– ––– ––– 91 140 ––– 31 ––– ––– 51 ––– ––– 40 ––– ––– 66 ––– ––– 220 ––– ––– 110 ––– ––– 110 ––– ––– 11210 ––– ––– 1020 ––– ––– 500 ––– ––– 1430 ––– ––– 1880 ––– S
Conditions
Effective Output Capacitance (Energy Related) Effective Output Capacitance (Time Related)
ià h
VDS = 10V, ID = 165A ID = 165A VDS = 30V nC VGS = 4 .5V ID = 165A, VDS =0V, VGS = 4.5V VDD = 3 9V ID = 165A ns RG = 2.1 Ω VGS = 4 .5V VGS = 0 V VDS = 50V pF ƒ = 1.0MHz VGS = 0 V, VDS = 0V to 48V VGS = 0 V, VDS = 0V to 48V
g
g
i h
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Notes:
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time
Min. Typ. Max. Units
––– ––– ––– ––– 270 A 1100
Conditions
MOSFET symbol showing the integral reverse
G D
Ãe
Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
S p-n junction diode. ––– ––– 1.3 V TJ = 25°C, IS = 165A, VGS = 0V VR = 51V, TJ = 25°C ––– 62 ––– ns IF = 165A TJ = 125°C ––– 66 ––– di/dt = 100A/µs TJ = 25°C ––– 310 ––– nC TJ = 125°C ––– 360 ––– ––– 4.4 ––– A TJ = 25°C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
g
g
Calcuted continuous current based on maximum allowable junction
temperature Bond wire current limit is 195A. Note that current limitation arising from heating of the device leds may occur with some lead mounting arrangements. Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25°C, L = 0.021mH RG = 25Ω, IAS = 165A, VGS =10V. Part not recommended for use above this value . ISD ≤ 165A, di/dt ≤ 430A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%. Coss eff. (TR) is a fixed capacitance that gives the same charging time as
Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as Rθ is measured at TJ approximately 90°C.
Coss while VDS is rising from 0 to 80% VDSS.
2
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IRLB3036GPbF
1000
TOP VGS 15V 10V 4.5V 4.0V 3.5V 3.3V 3.0V 2.7V
1000
TOP VGS 15V 10V 4.5V 4.0V 3.5V 3.3V 3.0V 2.7V
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
BOTTOM
10
100
1
2.7V
2.7V
≤60µs PULSE WIDTH
Tj = 25°C 0.1 0.1 1 10 100 1000 V DS, Drain-to-Source Voltage (V) 10 0.1 1
≤60µs PULSE WIDTH
Tj = 175°C 10
100
1000
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
RDS(on) , Drain-to-Source On Resistance (Normalized)
Fig 2. Typical Output Characteristics
2.5 ID = 165A 2.0 VGS = 10V
ID, Drain-to-Source Current (A)
100
T J = 175°C
10
1.5
1
T J = 25°C VDS = 25V ≤60µs PULSE WIDTH
1.0
0.1 1 2 3 4 5 6
0.5 -60 -40 -20 0 20 40 60 80 100 120140160 180 T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
100000
VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd
Fig 4. Normalized On-Resistance vs. Temperature
5.0 ID= 165A
VGS, Gate-to-Source Voltage (V)
4.0
VDS= 48V VDS= 30V
C, Capacitance (pF)
10000
Ciss
3.0
Coss 1000 Crss
2.0
1.0
100 1 10 VDS, Drain-to-Source Voltage (V) 100
0.0 0 20 40 60 80 100 120 QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRLB3036GPbF
1000 10000 OPERATION IN THIS AREA LIMITED BY R DS(on) 1000 100µsec 1msec 100 Limited by package 10 Tc = 25°C Tj = 175°C Single Pulse 1 0.0 0.5 1.0 1.5 2.0 2.5 0 1 10 100 VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V) 10msec DC
ISD, Reverse Drain Current (A)
100
T J = 175°C
10
T J = 25°C
1 VGS = 0V 0.1
ID, Drain-to-Source Current (A)
Fig 7. Typical Source-Drain Diode Forward Voltage
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
Fig 8. Maximum Safe Operating Area
75 Id = 5mA
300 250
ID, Drain Current (A)
Limited By Package
70
200 150 100 50 0 25 50 75 100 125 150 175 T C , Case Temperature (°C)
65
60
55 -60 -40 -20 0 20 40 60 80 100 120140 160180 T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs. Case Temperature
3.0 2.5 2.0
Fig 10. Drain-to-Source Breakdown Voltage
1200
EAS , Single Pulse Avalanche Energy (mJ)
1000 800 600 400 200 0
ID 27A 50A BOTTOM 165A TOP
Energy (µJ)
1.5 1.0 0.5 0.0 -10 0 10 20 30 40 50 60 70
25
50
75
100
125
150
175
Fig 11. Typical COSS Stored Energy
VDS, Drain-to-Source Voltage (V)
Starting T J , Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
4
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IRLB3036GPbF
1
Thermal Response ( Z thJC ) °C/W
D = 0.50 0.1 0.20 0.10 0.05 0.01 0.02 0.01 SINGLE PULSE ( THERMAL RESPONSE ) 1E-005 0.0001 0.001
τJ τJ τ1 R1 R1 τ2 R2 R2 R3 R3 τ3 R4 R4 τC τ τ1 τ2 τ3 τ4 τ4
Ri (°C/W)
0.01115 0.08360 0.18950 0.11519
τi (sec)
0.000009 0.000080 0.001295 0.006726
Ci= τi/Ri Ci i/Ri
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.01 0.1
0.001 1E-006
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
Avalanche Current (A)
100
0.01
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆ Tj = 150°C and Tstart =25°C (Single Pulse)
0.05 0.10 10 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Τ j = 25°C and Tstart = 150°C. 1 1.0E-06 1.0E-05 1.0E-04 tav (sec) 1.0E-03 1.0E-02 1.0E-01
Fig 14. Typical Avalanche Current vs.Pulsewidth
300 250 200 150 100 50 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 165A
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 22a, 22b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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EAR , Avalanche Energy (mJ)
5
IRLB3036GPbF
3.0
VGS(th) , Gate threshold Voltage (V)
14 12 10
IRRM (A)
2.5
IF = 110A V R = 51V TJ = 25°C TJ = 125°C
2.0 ID = 250µA 1.5 ID = 1.0mA ID = 1.0A 1.0
8 6 4 2
0.5 -75 -50 -25 0 25 50 75 100 125 150 175 200 T J , Temperature ( °C )
0
100
200
300
400
500
diF /dt (A/µs)
Fig 16. Threshold Voltage vs. Temperature
12 IF = 165A V R = 51V TJ = 25°C TJ = 125°C
Fig. 17 - Typical Recovery Current vs. dif/dt
900 800 700 600
QRR (A)
10
IF = 110A V R = 51V TJ = 25°C TJ = 125°C
IRRM (A)
8
500 400 300 200
6
4
2 0 100 200 300 400 500 diF /dt (A/µs)
100 0 100 200 300 400 500 diF /dt (A/µs)
Fig. 18 - Typical Recovery Current vs. dif/dt
600 IF = 165A V R = 51V 500 TJ = 25°C TJ = 125°C
Fig. 19 - Typical Stored Charge vs. dif/dt
QRR (A)
400
300
200 0 100 200 300 400 500 diF /dt (A/µs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRLB3036GPbF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
• • • • dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple ≤ 5% ISD
* VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01Ω
I AS
Fig 22a. Unclamped Inductive Test Circuit
VDS VGS RG RD
Fig 22b. Unclamped Inductive Waveforms
VDS 90%
D.U.T.
+
- VDD
V10V GS
Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %
10% VGS
td(on) tr t d(off) tf
Fig 23a. Switching Time Test Circuit
Current Regulator Same Type as D.U.T.
Fig 23b. Switching Time Waveforms
Id Vds Vgs
50KΩ 12V .2µF .3µF
D.U.T. VGS
3mA
+ V - DS
Vgs(th)
IG
ID
Current Sampling Resistors
Qgs1 Qgs2
Qgd
Qgodr
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Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
7
IRLB3036GPbF
Dimensions are shown in millimeters (inches)
TO-220AB Package Outline
TO-220AB Part Marking Information
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TO-220AB packages are not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 10/2009
8
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