IRLI540NPBF

IRLI540NPbF Logic-Level Gate Drive l Advanced Process Technology l Isolated Package l High Voltage Isolation = 2.5KVRMS … l Sink to Lead Creepage Dist. = 4.8mm l Fully Avalanche Rated l Lead-Free Description l PD -95454 HEXFET® Power MOSFET D VDSS = 100V RDS(on) = 0.044Ω G S ID = 23A Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The TO-220 Fullpak eliminates the need for additional insulating hardware in commercial-industrial applications. The moulding compound used provides a high isolation capability and a low thermal resistance between the tab and external heatsink. This isolation is equivalent to using a 100 micron mica barrier with standard TO-220 product. The Fullpak is mounted to a heatsink using a single clip or by a single screw fixing. Parameter ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current  † Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy‚† Avalanche Current† Repetitive Avalanche Energy Peak Diode Recovery dv/dt ƒ † Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 screw TO-220 FULLP AK Absolute Maximum Ratings Max. 23 16 120 54 0.36 ± 16 310 18 5.4 5.0 -55 to + 175 300 (1.6mm from case ) 10 lbf•in (1.1N•m) Units A W W/°C V mJ A mJ V/ns °C Thermal Resistance Parameter RθJC RθJA Junction-to-Case Junction-to-Ambient Typ. ––– ––– Max. 2.8 65 Units °C/W 6/23/04 IRLI540NPbF Electrical Characteristics @ TJ = 25°C (unless otherwise specified) V(BR)DSS ∆V(BR)DSS/∆TJ Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Drain to Sink Capacitance RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss C Max. Units Conditions ––– V VGS = 0V, ID = 250µA ––– V/°C Reference to 25°C, ID = 1mA† 0.044 VGS = 10V, ID = 12A „ 0.053 Ω VGS = 5.0V, ID = 12A „ 0.063 VGS = 4.0V, ID = 10A „ 2.0 V VDS = VGS , ID = 250µA ––– S VDS = 25V, ID = 18A† 25 VDS = 100V, VGS = 0V µA 250 VDS = 80V, V GS = 0V, TJ = 150°C 100 VGS = 16V nA -100 VGS = -16V 74 ID = 18A 9.4 nC VDS = 80V 38 VGS = 5.0V, See Fig. 6 and 13 „ † ––– VDD = 50V ––– ID = 18A ns ––– RG = 5.0 Ω, VGS = 5.0V ––– RD = 2.7Ω, See Fig. 10 „ † Between lead, ––– 4.5 ––– 6mm (0.25in.) nH G from package ––– 7.5 ––– and center of die contact ––– 1800 ––– VGS = 0V ––– 350 ––– VDS = 25V pF ––– 170 ––– ƒ = 1.0MHz, See Fig. 5† ––– 12 ––– ƒ = 1.0MHz Min. 100 ––– ––– ––– ––– 1.0 14 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– Typ. ––– 0.11 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 11 81 39 62 D S Source-Drain Ratings and Characteristics IS I SM VSD t rr Q rr ton Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) † Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time Min. Typ. Max. Units Conditions D MOSFET symbol 23 ––– ––– showing the A G integral reverse ––– ––– 120 p-n junction diode. S ––– ––– 1.3 V TJ = 25°C, IS = 18A, VGS = 0V „ ––– 190 290 ns TJ = 25°C, IF = 18A ––– 1.1 1.7 µC di/dt = 100A/µs „ † Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes:  Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 ) ‚ Starting TJ = 25°C, L = 1.9mH RG = 25Ω, IAS = 18A. (See Figure 12) ƒ ISD ≤ 18A, di/dt ≤ 180A/µs, VDD ≤ V(BR)DSS, T J ≤ 175°C „ Pulse width ≤ 300µs; duty cycle ≤ 2%. … t=60s, ƒ=60Hz † Uses IRL540N data and test conditions IRLI540NPbF 1000 VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP 1000 ID , Drain-to-Source Current (A) 100 ID , Drain-to-Source Current (A) VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP 100 10 10 2.5V 20µs PULSE WIDTH TJ = 25°C 1 10 2.5V 1 0.1 100 A VDS , Drain-to-Source Voltage (V) 1 0.1 20µs PULSE WIDTH TJ = 175°C 1 10 100 A VDS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics R DS(on) , Drain-to-Source On Resistance (Normalized) 1000 3.0 ID = 30A I D , Drain-to-Source Current (A) 2.5 100 TJ = 25°C TJ = 175°C 2.0 1.5 10 1.0 0.5 1 VDS = 50V 20µs PULSE WIDTH 2 4 6 8 10 A 0.0 -60 -40 -20 0 20 40 60 VGS = 10V 80 100 120 140 160 180 A VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature (°C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature IRLI540NPbF 3000 C, Capacitance (pF) Ciss 2000 V GS , Gate-to-Source Voltage (V) V GS = 0V, f = 1MHz C iss = C gs + C gd , C ds SHORTED C rss = C gd C oss = C ds + C gd 15 I D = 18A VDS = 80V VDS = 50V V DS = 20V 12 9 6 1000 Coss Crss 3 0 1 10 100 A 0 0 20 40 FOR TEST CIRCUIT SEE FIGURE 13 60 80 100 A V DS , Drain-to-Source Voltage (V) Q G , Total Gate Charge (nC) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 1000 1000 ISD , Reverse Drain Current (A) OPERATION IN THIS AREA LIMITED BY RDS(on) 100 I D , Drain Current (A) 100 TJ = 175°C TJ = 25°C 10 10µs 100µs 10 1ms 1 0.4 0.6 0.8 1.0 1.2 1.4 VGS = 0V 1.6 A 1.8 1 1 TC = 25°C TJ = 175°C Single Pulse 10 10ms 100 1000 A VSD , Source-to-Drain Voltage (V) VDS , Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area IRLI540NPbF 25 V DS 20 RD VGS RG D.U.T. + ID , Drain Current (A) -VDD 15 5.0V Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % 10 Fig 10a. Switching Time Test Circuit 5 VDS 90% 0 25 50 TC , Case Temperature ( °C) 75 100 125 150 175 Fig 9. Maximum Drain Current Vs. Case Temperature 10% VGS td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms 10 Thermal Response (Z thJC ) D = 0.50 1 0.20 0.10 0.05 0.1 0.02 0.01 PDM t1 SINGLE PULSE (THERMAL RESPONSE) t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.001 0.01 0.1 1 10 0.01 0.00001 0.0001 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case IRLI540NPbF E AS , Single Pulse Avalanche Energy (mJ) 800 TOP BOTTOM 600 15V ID 7.3A 13A 18A VDS L DRIVER 400 RG 10V D.U.T IAS tp + V - DD A 0.01Ω 200 Fig 12a. Unclamped Inductive Test Circuit 0 25 50 75 100 125 150 175 A V(BR)DSS tp Starting TJ , Junction Temperature (°C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ QG 12V .2µF .3µF 5.0 V QGS VG QGD VGS 3mA D.U.T. + V - DS Charge IG ID Current Sampling Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit IRLI540NPbF Peak Diode Recovery dv/dt Test Circuit D.U.T + ƒ + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer ‚ - „ +  RG • • • • dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test + VDD Driver Gate Drive P.W. Period D= P.W. Period VGS=10V * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt VDD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS IRLI540NPbF TO-220 Full-Pak Package Outline Dimensions are shown in millimeters (inches) TO-220 Full-Pak Part Marking Information E X AM P L E : T H IS IS AN IR F I8 4 0 G W IT H AS S E M B L Y L OT CODE 3 432 AS S E M B L E D O N W W 2 4 1 9 9 9 IN T H E AS S E M B L Y L IN E "K " IN T E R N AT IO N AL R E CT IF IE R L OGO AS S E M B L Y L OT CODE P AR T N U M B E R IR F I8 40 G 924 K 34 32 Note: "P" in assembly line position indicates "Lead-Free" D AT E C O D E Y E AR 9 = 1 9 9 9 WE E K 24 L IN E K Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.06/04