PD - 91414C
IRLMS6702
HEXFET® Power MOSFET
l l l l
Generation V Technology Micro6 Package Style Ultra Low RDS(on) P-Channel MOSFET
D
1
6
A D
VDSS = -20V RDS(on) = 0.20Ω
D
2
5
D
Description
Fifth Generation HEXFET® power MOSFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET® power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The Micro6 package with its customized leadframe produces a HEXFET® power MOSFET with RDS(on) 60% less than a similar size SOT-23. This package is ideal for applications where printed circuit board space is at a premium. It's unique thermal design and RDS(on) reduction enables a current-handling increase of nearly 300% compared to the SOT-23.
G
3
4
S
Top View
Micro6
Absolute Maximum Ratings
Parameter
ID @ TA = 25°C ID @ TA = 70°C IDM PD @TA = 25°C V GS dv/dt TJ, TSTG Continuous Drain Current, VGS @ -4.5V Continuous Drain Current, VGS @ -4.5V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt Junction and Storage Temperature Range
Max.
-2.4 -1.9 -13 1.7 13 ± 12 5.0 -55 to + 150
Units
A W
mW/°C
V V/ns °C
Thermal Resistance Ratings
RθJA Maximum Junction-to-Ambient
Parameter
Min.
Typ.
Max
75
Units
°C/W
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1
3/18/04
IRLMS6702
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Drain-to-Source Breakdown Voltage ∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient V (BR)DSS RDS(on) VGS(th) gfs IDSS I GSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. -20 -0.70 1.5 Typ. Max. Units Conditions V V GS = 0V, ID = -250µA -0.005 V/°C Reference to 25°C, ID = -1mA 0.200 V GS = -4.5V, ID = -1.6A Ω 0.375 V GS = -2.7V, ID = -0.80A V V DS = V GS, ID = -250µA S V DS = -10V, I D = -0.80A -1.0 V DS = -16V, V GS = 0V µA -25 V DS = -16V, V GS = 0V, TJ = 125°C -100 V GS = -12V nA 100 V GS = 12V 5.8 8.8 I D = -1.6A 1.8 2.6 nC V DS = -16V 2.1 3.1 V GS = -4.5V, See Fig. 6 and 9 13 V DD = -10V 20 I D = -1.6A ns 21 R G = 6.0Ω 18 R D = 6.1Ω, See Fig. 10 210 V GS = 0V 130 pF V DS = -15V 73 = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
I SM
VSD trr Qrr
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge
Min. Typ. Max. Units 25 15 -1.7 -13 -1.2 37 22 V ns nC A
Conditions MOSFET symbol showing the G integral reverse p-n junction diode. TJ = 25°C, IS = -1.6A, VGS = 0V TJ = 25°C, I F = -1.6A di/dt = -100A/µs
D
S
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Pulse width ≤ 300µs; duty cycle ≤ 2%. Surface mounted on FR-4 board, t ≤ 5sec.
ISD ≤ -1.6A, di/dt ≤ -100A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C
2
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IRLMS6702
100
VGS - 7.5V - 5.0V - 4.0V - 3.5V - 3.0V - 2.5V - 2.0V BOTTOM -1.75V TOP
100
-I D , Drain-to-Source Current (A)
10
-ID , Drain-to-Source Current (A)
VGS - 7.5V - 5.0V - 4.0V - 3.5V - 3.0V - 2.5V - 2.0V BOTTOM -1.75V TOP
10
1
1
-1.75V
-1.75V
0.1 0.1 1
20µs PULSE WIDTH TJ = 25°C A
10
0.1 0.1 1
20µs PULSE WIDTH TJ = 150°C
10
A
-VDS , Drain-to-Source Voltage (V)
-V , Drain-to-Source Voltage (V) DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
2.0
R DS(on) , Drain-to-Source On Resistance (Normalized)
I D = -1.6A
-ID , Drain-to-Source Current (A)
1.5
10
TJ = 25°C TJ = 150°C
1
1.0
0.5
0.1 1.5 2.0 2.5 3.0
VDS = -10V 20µs PULSE WIDTH
3.5 4.0 4.5 5.0
A
0.0 -60 -40 -20 0 20 40 60 80
V GS = -4.5V
100 120 140 160
A
-VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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3
IRLMS6702
400
-VGS , Gate-to-Source Voltage (V)
V GS = 0V, f = 1MHz C iss = Cgs + C gd , Cds SHORTED C rss = C gd C oss = C ds + C gd
10
I D = -1.6A VDS = -16V
8
C, Capacitance (pF)
300
Ciss Coss
200
6
4
Crss
100
2
0 1 10 100
A
0 0 2 4
FOR TEST CIRCUIT SEE FIGURE 9
6 8 10
A
-VDS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
100
100
-ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY R DS(on)
10
-I D , Drain Current (A)
10 100µs
TJ = 150°C
TJ = 25°C
1
1ms 1 10ms
0.1 0.4 0.6 0.8 1.0
VGS = 0V
1.2
A
0.1 1
TA = 25°C TJ = 150°C Single Pulse
10
1.4
A
100
-VSD , Source-to-Drain Voltage (V)
-VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRLMS6702
V DS RD
-4.5V
QGS VG
QG QGD
RG
VGS
D.U.T.
+
-4.5V
Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %
Charge
Fig 9a. Basic Gate Charge Waveform
Current Regulator Same Type as D.U.T.
Fig 10a. Switching Time Test Circuit
td(on) tr t d(off) tf
50KΩ 12V .2µF .3µF
VGS 10%
+ D.U.T. VDS
VGS
-3mA
90%
IG ID
VDS
Current Sampling Resistors
Fig 9b. Gate Charge Test Circuit
100 D = 0.50
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJA )
0.20 10 0.10 0.05 0.02 1 0.01 SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJA + TA 0.0001 0.001 0.01 0.1 1 10 100
PDM t1 t2
0.1 0.00001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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-
VDD
5
IRLMS6702
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer
-
+
RG VGS*
**
• dv/dt controlled by RG • ISD controlled by Duty Factor "D" • D.U.T. - Device Under Test
+ -
VDD
*
*
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive P.W. Period D=
P.W. Period
[VGS=10V ] ***
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
[VDD]
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple ≤ 5%
[ISD ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices Fig 12. For P-channel HEXFET® power MOSFETs
6
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IRLMS6702
Package Outline
Micro6ä
3.00 (.118 ) 2.80 (.111 )
LEAD ASSIGNMENTS
-BD D S
RECOMMENDED FOOTPRINT
2X 0.95 (.0375 ) 6X (1.06 (.042 )
1.75 (.068 ) 1.50 (.060 ) -A-
6 1
5 2
4 3
3.00 (.118 ) 2.60 (.103 )
6 1
5 2
4 3 2.20 (.087 )
0.95 ( .0375 ) 2X
D 0.50 (.019 ) 6X 0.35 (.014 ) 0.15 (.006 ) M C A S B S
D
G 6X 0.65 (.025 )
0 -10 1.30 (.051 ) 0.90 (.036 ) -C0.15 (.006 ) MAX. 1.45 (.057 ) 0.90 (.036 ) 0.10 (.004 ) 6 SURFACES
O
O
6X
0.20 (.007 ) 0.09 (.004 )
0.60 (.023 ) 0.10 (.004 )
NOTES : 1. DIMENSIONING & TOLERANCING PER ANSI Y14.5M-1982. 2. CONTROLLING DIMENSION : MILLIMETER. 3. DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES).
Part Marking Information
Micro6ä
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