IRLR3103PBF

PD - 95085A IRLR/U3103PbF Logic-Level Gate Drive l Ultra Low On-Resistance l Surface Mount (IRLR3103) l Straight Lead (IRLU3103) l Advanced Process Technology l Fast Switching l Fully Avalanche Rated l Lead-Free Description l HEXFET® Power MOSFET D VDSS = 30V RDS(on) = 0.019Ω G S ID = 55A… Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. The D-PAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU series) is for throughhole mounting applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount applications. D-PAK TO-252AA I-PAK TO-251AA Absolute Maximum Ratings Parameter ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current ‡ Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy‚‡ Avalanche Current‡ Repetitive Avalanche Energy‡ Peak Diode Recovery dv/dt ƒ Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Max. 55… 39… 220 107 0.71 ± 16 240 34 11 5.0 -55 to + 175 300 (1.6mm from case ) Units A W W/°C V mJ A mJ V/ns °C Thermal Resistance Parameter RθJC RθJA RθJA Junction-to-Case Junction-to-Ambient (PCB mount) ** Junction-to-Ambient Typ. ––– ––– ––– Max. 1.4 50 110 Units °C/W www.irf.com 1 12/7/04 IRLR/U3103PbF Electrical Characteristics @ TJ = 25°C (unless otherwise specified) V(BR)DSS ∆V(BR)DSS/∆TJ Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Min. Typ. Max. Units Conditions 30 ––– ––– V VGS = 0V, ID = 250µA ––– 0.037 ––– V/°C Reference to 25°C, I D = 1mA ––– ––– 0.019 VGS = 10V, ID = 33A „ Ω ––– ––– 0.024 VGS = 4.5V, ID = 25A „ 1.0 ––– ––– V VDS = VGS, ID = 250µA 23 ––– ––– S VDS = 25V, ID = 34A‡ ––– ––– 25 VDS = 30V, VGS = 0V µA ––– ––– 250 VDS = 18V, VGS = 0V, TJ = 150°C ––– ––– 100 VGS = 16V nA ––– ––– -100 VGS = -16V ––– ––– 50 ID = 34A ––– ––– 14 nC VDS = 24V ––– ––– 28 VGS = 4.5V, See Fig. 6 and 13 „‡ ––– 9.0 ––– VDD = 15V ––– 210 ––– ID = 34A ns ––– 20 ––– RG = 3.4Ω, VGS = 4.5V ––– 54 ––– RD = 0.43Ω, See Fig. 10 „‡ Between lead, ––– 4.5 ––– nH 6mm (0.25in.) G from package ––– 7.5 ––– and center of die contact† ––– 1600 ––– VGS = 0V ––– 640 ––– pF VDS = 25V ––– 320 ––– ƒ = 1.0MHz, See Fig. 5‡ D S Source-Drain Ratings and Characteristics IS ISM VSD trr Qrr ton Notes: Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) ‡ Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time Min. Typ. Max. Units Conditions D MOSFET symbol ––– ––– 55… showing the A G integral reverse ––– ––– 220 p-n junction diode. S ––– ––– 1.3 V TJ = 25°C, IS = 28A, VGS = 0V „ ––– 81 120 ns TJ = 25°C, IF = 34A ––– 210 310 nC di/dt = 100A/µs „ † Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) max. junction temperature. ( See fig. 11 ) ‚ VDD = 15V, starting TJ = 25°C, L = 300µH RG = 25Ω, IAS = 34A. (See Figure 12)  Repetitive rating; pulse width limited by „ Pulse width ≤ 300µs; duty cycle ≤ 2% … Calculated continuous current based on maximum allowable junction † This is applied for I-PAK, LS of D-PAK is measured between lead and center of die contact temperature; Package limitation current = 20A ƒ ISD ≤ 34A, di/dt ≤ 140A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C ‡ Uses IRL3103 data and test conditions ** When mounted on 1" square PCB (FR-4 or G-10 Material ) . For recommended footprint and soldering techniques refer to application note #AN-994 2 www.irf.com IRLR/U3103PbF 1000 VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP 1000 TOP ID , Drain-to-Source Current (A) 100 ID , Drain-to-Source Current (A) VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 100 10 10 2.5V 2.5V 1 0.1 20µs PULSE WIDTH T J = 25°C 10 1 100 A 1 0.1 20µs PULSE WIDTH T J = 175°C 1 10 100 A VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics R DS(on) , Drain-to-Source On Resistance (Normalized) 1000 2.0 I D = 56A I D , Drain-to-Source Current (A) TJ = 25°C 100 1.5 TJ = 175°C 1.0 10 0.5 1 2.0 3.0 4.0 5.0 V DS = 15V 20µs PULSE WIDTH 6.0 7.0 8.0 9.0 A 0.0 -60 -40 -20 0 20 40 60 VGS = 10V 80 100 120 140 160 180 A VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature (°C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3 IRLR/U3103PbF 3200 2800 2400 2000 1600 1200 800 400 0 1 10 100 Ciss VGS , Gate-to-Source Voltage (V) V GS = 0V, f = 1MHz C iss = Cgs + C gd , Cds SHORTED C rss = C gd C oss = C ds + C gd 15 I D = 34A V DS = 24V V DS = 15V 12 C, Capacitance (pF) Coss 9 Crss 6 3 A 0 0 10 20 30 FOR TEST CIRCUIT SEE FIGURE 13 40 50 60 70 A VDS , Drain-to-Source Voltage (V) Q G , Total Gate Charge (nC) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 1000 1000 ISD , Reverse Drain Current (A) OPERATION IN THIS AREA LIMITED BY R DS(on) 10µs 100 100µs 100 TJ = 175°C TJ = 25°C I D , Drain Current (A) 1ms 10 10ms 10 0.4 0.8 1.2 1.6 2.0 VGS = 0V 2.4 A 1 1 TC = 25°C TJ = 175°C Single Pulse 10 2.8 100 A VSD , Source-to-Drain Voltage (V) VDS , Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRLR/U3103PbF 60 LIMITED BY PACKAGE 50 V DS VGS RG RD D.U.T. + ID , Drain Current (A) 40 -VDD 5.0V 30 Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % 20 Fig 10a. Switching Time Test Circuit VDS 90% 10 0 25 50 75 100 125 150 175 TC , Case Temperature ( °C) Fig 9. Maximum Drain Current Vs. Case Temperature 10% VGS td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms 10 Thermal Response (Z thJC ) 1 D = 0.50 0.20 0.10 PDM SINGLE PULSE (THERMAL RESPONSE) t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak TJ = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 0.1 0.05 0.02 0.01 0.01 0.00001 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRLR/U3103PbF EAS , Single Pulse Avalanche Energy (mJ) 600 TOP 500 15V BOTTOM ID 14A 24A 34A VDS L DRIVER 400 300 RG 10V D.U.T IAS tp + V - DD A 200 0.01Ω Fig 12a. Unclamped Inductive Test Circuit 100 0 VDD = 15V 25 50 75 100 125 150 175 A V(BR)DSS tp Starting TJ , Junction Temperature (°C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ QG 12V .2µF .3µF 5.0 V QGS VG QGD VGS 3mA D.U.T. + V - DS Charge IG ID Current Sampling Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit 6 www.irf.com IRLR/U3103PbF Peak Diode Recovery dv/dt Test Circuit D.U.T + ƒ + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer ‚ - „ +  RG • • • • dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test + VDD Driver Gate Drive P.W. Period D= P.W. Period VGS=10V * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt VDD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS www.irf.com 7 IRLR/U3103PbF D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) D-Pak (TO-252AA) Part Marking Information EXAMPLE: T HIS IS AN IRFR120 WIT H ASS EMBLY LOT CODE 1234 ASS EMBLED ON WW 16, 1999 IN T HE AS S EMBLY LINE "A" Note: "P" in as sembly line pos ition indicates "Lead-Free" INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER IRFU120 12 916A 34 DAT E CODE YEAR 9 = 1999 WEEK 16 LINE A OR INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER IRFU120 12 34 DAT E CODE P = DES IGNATES LEAD-FREE PRODUCT (OPT IONAL) YEAR 9 = 1999 WEEK 16 A = AS S EMBLY S IT E CODE 8 www.irf.com IRLR/U3103PbF I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) I-Pak (TO-251AA) Part Marking Information EXAMPLE: T HIS IS AN IRFU120 WIT H AS S EMBLY LOT CODE 5678 AS S EMBLED ON WW 19, 1999 IN T HE AS S EMBLY LINE "A" Note: "P" in assembly line position indicates "Lead-Free" INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER IRF U120 919A 56 78 DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A OR INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER IRFU120 56 78 DAT E CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPTIONAL) YEAR 9 = 1999 WEEK 19 A = AS S EMBLY S IT E CODE www.irf.com 9 IRLR/U3103PbF D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 16.3 ( .641 ) 15.7 ( .619 ) 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. Data and specifications subject to change without notice. 10 IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.12/04 www.irf.com Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/