IRLR3410PBF

PD - 95087A IRLR/U3410PbF l l l l l l l l Logic Level Gate Drive Ultra Low On-Resistance Surface Mount (IRLR3410) Straight Lead (IRLU3410) Advanced Process Technology Fast Switching Fully Avalanche Rated Lead-Free HEXFET® Power MOSFET D VDSS = 100V RDS(on) = 0.105Ω G S ID = 17A Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. The D-PAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU series) is for throughhole mounting applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount applications. Parameter ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current … Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy‚… Avalanche Current… Repetitive Avalanche Energy… Peak Diode Recovery dv/dt ƒ Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds D-PAK TO-252AA I-PAK TO-251AA Absolute Maximum Ratings Max. 17 12 60 79 0.53 ± 16 150 9.0 7.9 5.0 -55 to + 175 300 (1.6mm from case ) Units A W W/°C V mJ A mJ V/ns °C Thermal Resistance Parameter RθJC RθJA RθJA Junction-to-Case Junction-to-Ambient (PCB mount) ** Junction-to-Ambient Typ. ––– ––– ––– Max. 1.9 50 110 Units °C/W www.irf.com 1 12/7/04 IRLR/U3410PbF Electrical Characteristics @ TJ = 25°C (unless otherwise specified) V(BR)DSS ∆V(BR)DSS/∆TJ Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Min. Typ. Max. Units Conditions 100 ––– ––– V VGS = 0V, ID = 250µA ––– 0.122 ––– V/°C Reference to 25°C, I D = 1mA ––– ––– 0.105 VGS = 10V, ID = 10A „ ––– ––– 0.125 W VGS = 5.0V, ID = 10A „ ––– ––– 0.155 VGS = 4.0V, ID = 9.0A „ 1.0 ––– 2.0 V VDS = VGS, ID = 250µA 7.7 ––– ––– S VDS = 25V, ID = 9.0A… ––– ––– 25 VDS = 100V, VGS = 0V µA ––– ––– 250 VDS = 80V, VGS = 0V, TJ = 150°C ––– ––– 100 VGS = 16V nA ––– ––– -100 VGS = -16V ––– ––– 34 ID = 9.0A ––– ––– 4.8 nC VDS = 80V ––– ––– 20 VGS = 5.0V, See Fig. 6 and 13 „… ––– 7.2 ––– VDD = 50V ––– 53 ––– ID = 9.0A ns ––– 30 ––– RG = 6.0Ω, VGS = 5.0V ––– 26 ––– RD = 5.5Ω, See Fig. 10 „… Between lead, ––– 4.5 ––– nH 6mm (0.25in.) G from package ––– 7.5 ––– and center of die contact† ––– 800 ––– VGS = 0V ––– 160 ––– pF VDS = 25V ––– 90 ––– ƒ = 1.0MHz, See Fig. 5… D S Source-Drain Ratings and Characteristics IS ISM VSD trr Qrr ton Notes: Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) … Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time Min. Typ. Max. Units Conditions D MOSFET symbol 17 ––– ––– showing the A G integral reverse ––– ––– 60 p-n junction diode. S ––– ––– 1.3 V TJ = 25°C, IS = 9.0A, VGS = 0V „ ––– 140 210 ns TJ = 25°C, IF =9.0A ––– 740 1100 nC di/dt = 100A/µs „… Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) max. junction temperature. ( See fig. 11 ) ‚ VDD = 25V, starting TJ = 25°C, L = 3.1mH RG = 25Ω, IAS = 9.0A. (See Figure 12) TJ ≤ 175°C  Repetitive rating; pulse width limited by „ Pulse width ≤ 300µs; duty cycle ≤ 2% … Uses IRL530N data and test conditions ƒ ISD ≤ 9.0A, di/dt ≤ 540A/µs, VDD ≤ V(BR)DSS, † This is applied for I-PAK, LS of D-PAK is measured between lead and center of die contact ** When mounted on 1" square PCB (FR-4 or G-10 Material ) . For recommended footprint and soldering techniques refer to application note #AN-994 2 www.irf.com IRLR/U3410PbF 100 VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP 100 ID , Drain-to-Source Current (A) ID , Drain-to-Source Current (A) VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP 10 10 2.5V 1 1 2.5V 20µs PULSE WIDTH T J = 25°C 1 10 0.1 0.1 100 A 0.1 0.1 20µs PULSE WIDTH T J = 175°C 1 10 100 A VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 100 3.0 I D , Drain-to-Source Current (A) TJ = 25°C TJ = 175°C 10 R DS(on) , Drain-to-Source On Resistance (Normalized) I D = 15A 2.5 2.0 1.5 1 1.0 0.5 0.1 2 3 4 5 6 V DS = 50V 20µs PULSE WIDTH 7 8 9 10 A 0.0 -60 -40 -20 0 20 40 60 VGS = 10V 80 100 120 140 160 180 A VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature (°C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3 IRLR/U3410PbF 1400 1200 C, Capacitance (pF) 1000 Ciss V GS , Gate-to-Source Voltage (V) V GS = 0V, f = 1MHz C iss = Cgs + C gd , Cds SHORTED C rss = C gd C oss = C ds + C gd 15 I D = 9.0A 12 V DS = 80V V DS = 50V V DS = 20V 800 9 600 Coss Crss 6 400 3 200 0 1 10 100 A 0 0 10 20 FOR TEST CIRCUIT SEE FIGURE 13 30 40 50 A VDS , Drain-to-Source Voltage (V) Q G , Total Gate Charge (nC) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 100 1000 ISD , Reverse Drain Current (A) OPERATION IN THIS AREA LIMITED BY R DS(on) TJ = 175°C I D , Drain Current (A) 100 10 10µs TJ = 25°C 10 100µs 1 0.4 0.6 0.8 1.0 VGS = 0V 1.2 A 1 1 TC = 25°C TJ = 175°C Single Pulse 10 1ms 10ms 100 1.4 1000 A VSD , Source-to-Drain Voltage (V) VDS , Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRLR/U3410PbF 20 V DS VGS RD ID , Drain Current (A) 15 RG 5.0V D.U.T. + -VDD 10 Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % 5 Fig 10a. Switching Time Test Circuit VDS 90% 0 25 50 TC , Case Temperature ( ° C) 75 100 125 150 175 Fig 9. Maximum Drain Current Vs. Case Temperature 10% VGS td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms 10 Thermal Response (Z thJC ) 1 D = 0.50 0.20 0.10 0.05 0.1 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) PDM t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1 0.01 0.00001 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRLR/U3410PbF EAS , Single Pulse Avalanche Energy (mJ) 350 TOP 300 15V BOTTOM ID 3.7A 6.4A 9.0A 250 VDS L DRIVER 200 RG 10V D.U.T IAS tp + V - DD 150 A 0.01Ω 100 Fig 12a. Unclamped Inductive Test Circuit 50 0 VDD = 25V 25 50 75 100 125 150 175 A V(BR)DSS tp Starting TJ , Junction Temperature (°C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ QG 12V .2µF .3µF 5.0 V QGS VG QGD VGS 3mA D.U.T. + V - DS Charge IG ID Current Sampling Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit 6 www.irf.com IRLR/U3410PbF Peak Diode Recovery dv/dt Test Circuit D.U.T + ƒ + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer ‚ - „ +  RG • • • • dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test + VDD Driver Gate Drive P.W. Period D= P.W. Period VGS=10V * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt VDD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS www.irf.com 7 IRLR/U3410PbF D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) D-Pak (TO-252AA) Part Marking Information EXAMPLE: T HIS IS AN IRFR120 WIT H ASS EMBLY LOT CODE 1234 ASS EMBLED ON WW 16, 1999 IN T HE AS S EMBLY LINE "A" Note: "P" in as sembly line pos ition indicates "Lead-Free" INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER IRFU120 12 916A 34 DAT E CODE YEAR 9 = 1999 WEEK 16 LINE A OR INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER IRFU120 12 34 DAT E CODE P = DES IGNATES LEAD-FREE PRODUCT (OPT IONAL) YEAR 9 = 1999 WEEK 16 A = AS S EMBLY S IT E CODE 8 www.irf.com IRLR/U3410PbF I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) I-Pak (TO-251AA) Part Marking Information EXAMPLE: T HIS IS AN IRFU120 WIT H AS S EMBLY LOT CODE 5678 AS S EMBLED ON WW 19, 1999 IN T HE AS S EMBLY LINE "A" Note: "P" in assembly line position indicates "Lead-Free" INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER IRF U120 919A 56 78 DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A OR INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER IRFU120 56 78 DAT E CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) YEAR 9 = 1999 WEEK 19 A = AS S EMBLY S IT E CODE www.irf.com 9 IRLR/U3410PbF D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 16.3 ( .641 ) 15.7 ( .619 ) 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. Data and specifications subject to change without notice. 10 IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.12/04 www.irf.com Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/