IRLR3717

PD - 94718B IRLR3717 IRLU3717 Applications l High Frequency Synchronous Buck Converters for Computer Processor Power l High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use Benefits l Very Low RDS(on) at 4.5V VGS l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage and Current HEXFET® Power MOSFET VDSS RDS(on) max 20V 4.0m: Qg 21nC D-Pak IRLR3717 I-Pak IRLU3717 Absolute Maximum Ratings Parameter VDS VGS ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C PD @TC = 100°C TJ TSTG Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Max. 20 ± 20 120 81 Units V A ™ f f 460 89 44 0.59 -55 to + 175 W/°C °C W Maximum Power Dissipation Maximum Power Dissipation Linear Derating Factor Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case) Thermal Resistance Parameter RθJC RθJA RθJA Junction-to-Case † Junction-to-Ambient (PCB Mount) Junction-to-Ambient † Typ. Max. 1.69 50 110 Units °C/W gà † ––– ––– ––– Notes  through † are on page 11 www.irf.com 1 1/24/05 IRLR/U3717 Static @ TJ = 25°C (unless otherwise specified) Parameter BVDSS ∆ΒVDSS/∆TJ RDS(on) VGS(th) ∆VGS(th)/∆TJ IDSS IGSS gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw Qoss td(on) tr td(off) tf Ciss Coss Crss Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) Output Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. Typ. Max. Units 20 ––– ––– ––– 1.55 ––– ––– ––– ––– ––– 49 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 12 3.4 4.6 2.0 -6.4 ––– ––– ––– ––– ––– 21 6.4 1.9 7.2 5.5 9.1 13 14 14 5.8 16 2830 920 420 ––– ––– 4.0 5.5 2.45 ––– 1.0 150 100 -100 ––– 31 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– pF VGS = 0V VDS = 10V ns nC nC VDS = 10V VGS = 4.5V ID = 12A S nA V mV/°C µA V Conditions VGS = 0V, ID = 250µA mV/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 15A VGS = 4.5V, ID = 12A e e VDS = VGS, ID = 250µA VDS = 16V, VGS = 0V VDS = 16V, VGS = 0V, TJ = 125°C VGS = 20V VGS = -20V VDS = 10V, ID = 12A See Fig. 16 VDS = 10V, VGS = 0V VDD = 10V, VGS = 4.5V ID = 12A Clamped Inductive Load e ƒ = 1.0MHz Avalanche Characteristics EAS IAR EAR Parameter Single Pulse Avalanche Energy Avalanche Current Ù d Typ. ––– ––– ––– Max. 460 12 8.9 Units mJ A mJ Repetitive Avalanche Energy ™ ––– ––– ––– ––– ––– ––– ––– ––– 22 13 Diode Characteristics Parameter IS ISM VSD trr Qrr ton Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time Min. Typ. Max. Units 120 f Conditions MOSFET symbol D A 460 1.0 33 19 V ns nC Ù showing the integral reverse G S p-n junction diode. TJ = 25°C, IS = 12A, VGS = 0V TJ = 25°C, IF = 12A, VDD = 10V di/dt = 100A/µs e e Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) 2 www.irf.com IRLR/U3717 1000 TOP VGS 10V 6.0V 4.5V 4.0V 3.5V 3.0V 2.8V 2.5V 1000 TOP VGS 10V 6.0V 4.5V 4.0V 3.5V 3.0V 2.8V 2.5V ID, Drain-to-Source Current (A) 100 BOTTOM ID, Drain-to-Source Current (A) 100 BOTTOM 10 1 2.5V 0.1 20µs PULSE WIDTH Tj = 25°C 0.1 1 10 100 10 2.5V 20µs PULSE WIDTH Tj = 175°C 1.0 0.1 1 10 100 V DS, Drain-to-Source Voltage (V) 0.01 V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 1000 2.0 100 T J = 175°C RDS(on) , Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (Α) ID = 30A VGS = 10V 1.5 10 1 T J = 25°C 1.0 VDS = 25V 20µs PULSE WIDTH 0.1 0 2 4 6 8 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 VGS, Gate-to-Source Voltage (V) T J , Junction Temperature (°C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature www.irf.com 3 IRLR/U3717 100000 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd 6.0 ID= 12A VGS, Gate-to-Source Voltage (V) 5.0 C, Capacitance(pF) VDS= 16V VDS= 10V 10000 4.0 3.0 Ciss 1000 Coss Crss 2.0 1.0 100 1 10 100 0.0 0 5 10 15 20 25 30 VDS, Drain-to-Source Voltage (V) QG Total Gate Charge (nC) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 1000.00 T J = 25°C T J = 175°C 10000 OPERATION IN THIS AREA LIMITED BY R DS(on) 1000 100.00 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 100 100µsec 10 Tc = 25°C Tj = 175°C Single Pulse 1 0 1 10 10.00 1msec 10msec VGS = 0V 1.00 0.0 0.5 1.0 1.5 2.0 2.5 VSD, Source-to-Drain Voltage (V) 100 1000 VDS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRLR/U3717 125 Limited By Package 100 ID, Drain Current (A) 3.0 VGS(th) Gate threshold Voltage (V) 2.5 2.0 75 ID = 250µA 1.5 50 1.0 25 0.5 0 25 50 75 100 125 150 175 T C , Case Temperature (°C) 0.0 -75 -50 -25 0 25 50 75 100 125 150 175 200 T J , Temperature ( °C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Threshold Voltage vs. Temperature 10 Thermal Response ( Z thJC ) 1 D = 0.50 0.20 0.1 0.10 0.05 0.02 0.01 τJ R1 R1 τJ τ1 τ2 R2 R2 R3 R3 τ3 τC τ τ3 Ri (°C/W) τi (sec) 0.771 0.000430 0.629 0.291 0.006491 0.072119 τ1 τ2 Ci= τi /Ri Ci= τi/Ri 0.01 SINGLE PULSE ( THERMAL RESPONSE ) 0.001 1E-006 1E-005 0.0001 0.001 0.01 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.1 1 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRLR/U3717 ( RDS (on), Drain-to -Source On Resistance mΩ) 12 2000 ID = 15A 10 EAS , Single Pulse Avalanche Energy (mJ) 1500 ID 8.2A 9.7A BOTTOM 12A TOP 8 1000 6 TJ = 125°C 4 500 TJ = 25°C 2 2.0 4.0 6.0 8.0 10.0 0 25 50 75 100 125 150 175 VGS, Gate-to-Source Voltage (V) Starting T J , Junction Temperature (°C) Fig 12. Typical On-Resistance Vs. Gate Voltage Fig 13a. Maximum Avalanche Energy vs. Drain Current LD VDS 15V + VDS L DRIVER VDD D.U.T A RG VGS 20V D.U.T IAS tp + V - DD VGS Pulse Width < 1µs Duty Factor < 0.1% 0.01Ω Fig 13b. Unclamped Inductive Test Circuit V(BR)DSS tp Fig 14a. Switching Time Test Circuit VDS 90% 10% VGS I AS td(on) tr td(off) tf Fig 13c. Unclamped Inductive Waveforms Fig 14b. Switching Time Waveforms 6 www.irf.com IRLR/U3717 D.U.T Driver Gate Drive + P.W. Period D= P.W. Period VGS=10V ƒ + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt ‚ - „ +  RG • • • • dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD VDD + - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs Current Regulator Same Type as D.U.T. Id Vds Vgs 50KΩ 12V .2µF .3µF D.U.T. VGS 3mA + V - DS Vgs(th) IG ID Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr Fig 16a. Gate Charge Test Circuit Fig 16b. Gate Charge Waveform www.irf.com 7 IRLR/U3717 Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; Synchronous FET The power loss equation for Q2 is approximated by; * Ploss = Pconduction + P + Poutput drive Ploss = Irms × Rds(on) + ( g × Vg × f ) Q ( 2 ) Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput This can be expanded and approximated by; ⎛Q ⎞ + ⎜ oss × Vin × f + (Qrr × Vin × f ) ⎝2 ⎠ *dissipated primarily in Q1. Ploss = (Irms 2 × Rds(on ) ) ⎛ Qgd +⎜I × × Vin × ig ⎝ + (Qg × Vg × f ) + ⎛ Qoss × Vin × f ⎞ ⎝2 ⎠ ⎞ ⎞⎛ Qgs 2 f⎟ + ⎜ I × × Vin × f ⎟ ig ⎠⎝ ⎠ This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by the power supply input buss voltage. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Qoss Characteristic 8 www.irf.com IRLR/U3717 D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) D-Pak (TO-252AA) Part Marking Information EXAMPLE: T HIS IS AN IRFR120 WITH AS SEMBLY LOT CODE 1234 ASSEMBLED ON WW 16, 1999 IN THE ASS EMBLY LINE "A" Note: "P" in assembly line position indicates "Lead-Free" PART NUMBER INTERNAT IONAL RECTIF IER LOGO IRFU120 12 916A 34 AS SEMBLY LOT CODE DATE CODE YEAR 9 = 1999 WEEK 16 LINE A OR PART NUMBER INTERNATIONAL RECT IFIER LOGO IRFU120 12 34 DATE CODE P = DES IGNATES LEAD-F REE PRODUCT (OPT IONAL) YEAR 9 = 1999 WEEK 16 A = AS SEMBLY SIT E CODE ASSEMBLY LOT CODE www.irf.com 9 IRLR/U3717 I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) I-Pak (TO-251AA) Part Marking Information EXAMPLE: T HIS IS AN IRF U120 WIT H AS SEMBLY LOT CODE 5678 AS SEMBLE D ON WW 19, 1999 IN T HE ASSEMBLY LINE "A" Note: "P" in as s embly line pos ition indicates "Lead-F ree" PART NUMBER INT E RNAT IONAL RECT IFIER LOGO IRFU120 919A 56 78 ASSE MBLY LOT CODE DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A OR INT ERNAT IONAL RECT IFIER LOGO PART NUMBER IRF U120 56 78 ASS EMBLY LOT CODE DAT E CODE P = DESIGNAT ES LEAD-FREE PRODUCT (OPT IONAL) YEAR 9 = 1999 WEEK 19 A = ASS EMBLY SIT E CODE 10 www.irf.com IRLR/U3717 D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 16.3 ( .641 ) 15.7 ( .619 ) 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1 . CONTROLLING DIMENSION : MILLIMETER. 2 . ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3 . OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. Notes:  Repetitive rating; pulse width limited by max. junction temperature. ‚ Starting TJ = 25°C, L = 6.4mH, RG = 25Ω, IAS = 12A. ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%. „ Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 30A. … When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994. † Rθ is measured at TJ approximately 90°C Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 01/05 www.irf.com 11