IRLR7843

PD - 94638A HEXFET Power MOSFET Applications l High Frequency Synchronous Buck Converters for Computer Processor Power l High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use Benefits l Very Low RDS(on) at 4.5V VGS l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage and Current IRLR7843 IRLU7843 ® Qg 34nC VDSS 30V RDS(on) max 3.3m: D-Pak IRLR7843 I-Pak IRLU7843 Absolute Maximum Ratings Parameter VDS VGS ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C PD @TC = 100°C TJ TSTG Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Max. 30 ± 20 161 113 620 140 71 0.95 -55 to + 175 300 (1.6mm from case) Units V ™ f f A W W/°C °C Maximum Power Dissipation Maximum Power Dissipation Linear Derating Factor Operating Junction and Storage Temperature Range g g Soldering Temperature, for 10 seconds Thermal Resistance Parameter RθJC RθJA RθJA Junction-to-Case Junction-to-Ambient (PCB Mount) Junction-to-Ambient Typ. Max. 1.05 50 110 Units °C/W gà ––– ––– ––– Notes  through … are on page 11 www.irf.com 1 12/30/03 IRLR/U7843 Static @ TJ = 25°C (unless otherwise specified) Parameter BVDSS ∆ΒVDSS/∆TJ RDS(on) VGS(th) ∆VGS(th)/∆TJ IDSS IGSS gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw Qoss td(on) tr td(off) tf Ciss Coss Crss Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) Output Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. Typ. Max. Units 30 ––– ––– ––– 1.5 ––– ––– ––– ––– ––– 37 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 19 2.6 3.2 ––– -5.4 ––– ––– ––– ––– ––– 34 9.1 2.5 12 10 15 21 25 42 34 19 4380 940 430 ––– ––– 3.3 4.0 2.3 ––– 1.0 150 100 -100 ––– 50 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– pF nC nC V Conditions VGS = 0V, ID = 250µA mV/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 15A V VGS = 4.5V, ID VDS = VGS, ID = 250µA e = 12A e mV/°C µA VDS = 24V, VGS = 0V nA S VDS = 24V, VGS = 0V, TJ = 125°C VGS = 20V VGS = -20V VDS = 15V, ID = 12A VDS = 15V VGS = 4.5V ID = 12A See Fig. 16 VDS = 15V, VGS = 0V VDD = 15V, VGS = 4.5V e ns ID = 12A Clamped Inductive Load VGS = 0V VDS = 15V ƒ = 1.0MHz Avalanche Characteristics EAS IAR EAR Parameter Single Pulse Avalanche Energy Avalanche Current Ù d Repetitive Avalanche Energy ™ ––– ––– ––– ––– ––– ––– ––– ––– 39 36 Typ. ––– ––– ––– Max. 1440 12 14 Units mJ A mJ Diode Characteristics Parameter IS ISM VSD trr Qrr ton Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time Min. Typ. Max. Units 161 f Conditions MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25°C, IS = 12A, VGS = 0V TJ = 25°C, IF = 12A, VDD = 15V di/dt = 100A/µs A 620 1.0 59 54 V ns nC Ù e e Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) 2 www.irf.com IRLR/U7843 1000 VGS 10V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V BOTTOM 2.5V TOP 1000 ID, Drain-to-Source Current (A) 100 ID, Drain-to-Source Current (A) 100 VGS 10V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V BOTTOM 2.5V TOP 10 2.5V 10 1 2.5V 20µs PULSE WIDTH Tj = 25°C 0.1 0.1 1 10 100 20µs PULSE WIDTH Tj = 175°C 1 0.1 1 10 100 VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 1000 2.0 RDS(on) , Drain-to-Source On Resistance ID, Drain-to-Source Current (Α) ID = 30A VGS = 10V 100 10 T J = 25°C (Normalized) T J = 175°C 1.5 1.0 1 2.0 3.0 VDS = 15V 20µs PULSE WIDTH 4.0 5.0 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 VGS , Gate-to-Source Voltage (V) T J , Junction Temperature (°C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature www.irf.com 3 IRLR/U7843 100000 12 VGS, Gate-to-Source Voltage (V) VGS = 0V, f = 1 MHZ Ciss = C gs + Cgd, C ds Crss = C gd Coss = Cds + Cgd SHORTED ID= 12A 10 8 6 4 2 0 VDS= 24V VDS= 15V C, Capacitance (pF) 10000 Ciss 1000 Coss Crss 100 1 10 100 0 20 40 60 80 VDS, Drain-to-Source Voltage (V) Q G Total Gate Charge (nC) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 1000.0 10000 OPERATION IN THIS AREA LIMITED BY R DS(on) 100.0 T J = 175°C 10.0 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 1000 100 100µsec 10 Tc = 25°C Tj = 175°C Single Pulse 1 0.1 1.0 10.0 1msec 10msec 100.0 1000.0 1.0 T J = 25°C VGS = 0V 0.1 0.0 0.5 1.0 1.5 VSD, Source-toDrain Voltage (V) VDS , Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRLR/U7843 160 LIMITED BY PACKAGE 2.5 VGS(th) Gate threshold Voltage (V) ID , Drain Current (A) 120 2.0 ID = 250µA 1.5 80 1.0 40 0.5 0 25 50 75 100 125 150 175 T C , Case Temperature (°C) 0.0 -75 -50 -25 0 25 50 75 100 125 150 175 T J , Temperature ( °C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Threshold Voltage vs. Temperature 10 Thermal Response ( Z thJC ) 1 D = 0.50 0.20 0.10 0.05 0.02 0.01 τJ τJ τ1 τ1 R1 R1 τ2 R2 R2 τC τ2 τ 0.1 Ri (°C/W) 0.5084 0.5423 τi (sec) 0.000392 0.011108 0.01 Ci= τi/Ri Ci i/Ri SINGLE PULSE ( THERMAL RESPONSE ) 0.001 1E-006 1E-005 0.0001 0.001 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRLR/U7843 15V 6000 EAS, Single Pulse Avalanche Energy (mJ) VDS L DRIVER 5000 ID 8.6A 9.6A BOTTOM 12A TOP RG 20V VGS D.U.T IAS tp + V - DD 4000 A 0.01Ω 3000 Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp 2000 1000 0 25 50 75 100 125 150 175 Starting T J, Junction Temperature (°C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS LD VDS Fig 12b. Unclamped Inductive Waveforms + VDD Current Regulator Same Type as D.U.T. D.U.T VGS Pulse Width < 1µs Duty Factor < 0.1% 50KΩ 12V .2µF .3µF D.U.T. VGS 3mA + V - DS Fig 14a. Switching Time Test Circuit VDS 90% IG ID 10% Current Sampling Resistors VGS td(on) tr td(off) tf Fig 13. Gate Charge Test Circuit Fig 14b. Switching Time Waveforms 6 www.irf.com IRLR/U7843 D.U.T Driver Gate Drive + P.W. Period D= P.W. Period VGS=10V ƒ + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt ‚ - - „ +  RG • • • • dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD VDD + - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs Id Vds Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Waveform www.irf.com 7 IRLR/U7843 Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; Synchronous FET The power loss equation for Q2 is approximated by; * Ploss = Pconduction + P + Poutput drive Ploss = Irms × Rds(on) + ( g × Vg × f ) Q ( 2 ) Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput This can be expanded and approximated by; Q  +  oss × Vin × f + (Qrr × Vin × f ) 2  *dissipated primarily in Q1. Ploss = (Irms 2 × Rds(on ) )  Qgd +I × × Vin × ig  + (Qg × Vg × f ) +  Qoss × Vin × f  2   Qgs 2  f +  I × × Vin × f  ig   This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 i s a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by the power supply input buss voltage. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Qoss Characteristic 8 www.irf.com IRLR/U7843 D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) 6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) 6.45 (.245) 5.68 (.224) 6.22 (.245) 5.97 (.235) 1.02 (.040) 1.64 (.025) 1 2 3 0.51 (.020) MIN. 10.42 (.410) 9.40 (.370) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN -B1.52 (.060) 1.15 (.045) 1.14 (.045) 0.76 (.030) 0.89 (.035) 3X 0.64 (.025) 0.25 (.010) M AMB NOTES: 2X 0.58 (.023) 0.46 (.018) 2.28 (.090) 4.57 (.180) 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006). D-Pak (TO-252AA) Part Marking Information Notes : T his part marking information applies to devices produced before 02/26/2001 EXAMPLE: T HIS IS AN IRFR120 WIT H AS S EMBLY LOT CODE 9U1P INT ERNATIONAL RECTIFIER LOGO ASS EMBLY LOT CODE IRFU120 016 9U 1P DAT E CODE YEAR = 0 WEEK = 16 Notes : T his part marking information applies to devices produced after 02/26/2001 EXAMPLE: T HIS IS AN IRFR120 WIT H AS S EMBLY LOT CODE 1234 AS SEMBLED ON WW 16, 1999 IN T HE AS SEMBLY LINE "A" PART NUMBER IRFU120 12 916A 34 INT ERNATIONAL RECTIFIER LOGO ASS EMBLY LOT CODE DATE CODE YEAR 9 = 1999 WEEK 16 LINE A www.irf.com 9 IRLR/U7843 I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) 6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 6.45 (.245) 5.68 (.224) 1.52 (.060) 1.15 (.045) 1 -B2.28 (.090) 1.91 (.075) 9.65 (.380) 8.89 (.350) 2 3 NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006). 6.22 (.245) 5.97 (.235) 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 0.58 (.023) 0.46 (.018) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN 3X 1.14 (.045) 0.76 (.030) 3X 0.89 (.035) 0.64 (.025) M AMB 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) 2.28 (.090) 2X 0.25 (.010) I-Pak (TO-251AA) Part Marking Information Notes : T his part marking information applies to devices produced before 02/26/2001 EXAMPLE: T HIS IS AN IRFR120 WIT H AS SEMBLY LOT CODE 9U1P INTERNATIONAL RECT IFIER LOGO AS SEMBLY LOT CODE DAT E CODE YEAR = 0 WEEK = 16 IRFU120 016 9U 1P Notes : T his part marking information applies to devices produced after 02/26/2001 EXAMPLE: T HIS IS AN IRFR120 WIT H AS SEMBLY LOT CODE 5678 AS SEMBLED ON WW 19, 1999 IN T HE ASS EMBLY LINE "A" INTERNATIONAL RECT IFIER LOGO ASS EMBLY LOT CODE PART NUMBER IRFU120 919A 56 78 DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A 10 www.irf.com IRLR/U7843 D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 16.3 ( .641 ) 15.7 ( .619 ) 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. Notes:  Repetitive rating; pulse width limited by max. junction temperature. ‚ Starting TJ = 25°C, L = 20mH, RG = 25Ω, IAS = 12A. ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%. „ Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 30A. … When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.12/03 www.irf.com 11