IRLR8503PBF

PD- 95095A IRLR8503PbF IRLR8503PbF • • • • N-Channel Application-Specific MOSFET Ideal for CPU Core DC-DC Converters Low Conduction Losses Minimizes Parallel MOSFETs for high current applications • Lead-Free HEXFET® MOSFET for DC-DC Converters D Description This new device employs advanced HEXFET Power MOSFET technology to achieve very low on-resistance. The reduced conduction losses makes it ideal for high efficiency DC-DC converters that power the latest generation of microprocessors. The IRLR8503 has been optimized and is 100% tested for all parameters that are critical in synchronous buck converters including RDS(on), gate charge and Cdv/dtinduced turn-on immunity. The IRLR8503 offers an extremely low combination of Qsw & RDS(on) for reduced losses in control FET applications. The package is designed for vapor phase, infra-red, convection, or wave soldering techniques. Power dissipation of greater than 2W is possible in a typical PCB mount application. G S D-Pak DEVICE RATINGS (MAX. Values) IRLR8503PbF VDS RDS(on) QG Qsw Qoss IRLR8503 30 ±20 44 32 196 62 30 –55 to 150 15 196 W °C A A 30V 18 mΩ 20 nC 8 nC 29.5 nC Absolute Maximum Ratings Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain or Source Current (VGS ≥ 10V)… Pulsed Drain Current Power Dissipation… TC = 25°C TC = 90°C Junction & Storage Temperature Range Continuous Source Current (Body Diode) Pulsed source Current  Thermal Resistance Parameter Maximum Junction-to-Ambientƒ Maximum Junction-to-Lead Symbol R θ JA R θJL Max. 50 2.0 Units °C/W °C/W TJ, TSTG IS ISM TC = 25°C TC = 90°C IDM PD Symbol VDS VGS ID Units V www.irf.com 1 12/06/04 IRLR8503PbF Electrical Characteristics Parameter Drain-to-Source Breakdown Voltage* Static Drain-Source on Resistance* Gate Threshold Voltage* Drain-Source Leakage Current VGS(th) IDSS Symbol V(BR)DSS RDS (on) Min 30 – – 1.0 – – Gate-Source Leakage Current* Total Gate Charge Control FET* Total Gate Charge Sync FET* Pre-Vth Gate-Source Charge Post-Vth Gate-Source Charge Gate to Drain Charge Switch Charge* (Qgs2 + Qgd) Output Charge* Gate Resistance Turn-on Delay Time Drain Voltage Rise Time Turn-off Delay Time Drain Voltage Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance IGSS Qg Qg Qgs1 Qgs2 Qgd Q SW Qoss Rg td (on) trv td (off) tfv Ciss Coss Crss – – – – – – – – – – – – – – – – – – – 15 13 3.7 1.3 4.1 5.4 23 1.7 10 18 11 3 1650 650 58 30* 150 ±100 20 17 – – – 8 29.5 – – – – – – – – pF VDS = 25V, VGS = 0 ns Ω VDD = 16V, ID = 15A VGS = 5V Clamped Inductive Load See test diagram Fig 14. VDS = 16V, VGS = 0 nC nA Typ – 11 13 Max – 16 18 V µA Units V mΩ Conditions VGS = 0V, ID = 250µA VGS = 10V, ID =15A‚ VGS = 4.5V, ID =15A VDS = VGS, ID = 250µA VDS = 24V, VGS = 0 VDS = 24V, VGS = 0, Tj = 100°C VGS = ±12V VGS= 5V, ID= 15A, VDS =16V, VGS = 5V, VDS < 100mV VDS = 16V, ID = 15A Source-Drain Rating & Characteristics Parameter Diode Forward Voltage* Reverse Recovery Charge „ Reverse Recovery Charge (with Parallel Schottky)„ Symbol VSD Q rr Qrr(s) Min – – – 76 67 Typ Max 1.0 Units V nC Conditions IS = 15A‚ , VGS = 0V di/dt = 700A/µs VDS = 16V, VGS = 0V, IS = 15A di/dt = 700A/µs (with 10BQ040) VDS = 16V, VGS = 0V, IS = 15A Notes:  ‚ ƒ * „ Typ = measured - Qoss Repetitive rating; pulse width limited by max. junction temperature. … Calculated continuous current based on maximum allowable Pulse width ≤ 300 µs; duty cycle ≤ 2%. Junction temperature; switching and other losses will When mounted on 1 inch square copper board, t < 10 sec. decrease RMS current capability; package limitation current = 20A. Devices are 100% tested to these parameters. 2 www.irf.com IRLR8503PbF Power MOSFET Optimization for DC-DC Converters While the IRLR8103V and IRLR8503 can and are being used in a variety of applications, they were designed and optimized for low voltage DC-DC conversion in a synchronous buck converter topology, specifically, microprocessor power applications. The IRLR8503 (Figure 1) was optimized for the control FET socket, while the IRLR8103V was optimized for the synchronous FET function. Table 2 – New Charge Parameters New Charge Parameter QGS1 QGS2 QGCONT QSWITCH Q OSS Description Pre-Threshold Gate Charge Post-Threshold Gate Charge Control FET Total QG Charge during control FET switching Combines QGS2 and QGD Output charge Charge supplied to COSS during the QGD period of control FET switching Synchronous FET Total QG (VDS ≤ 0) Figure 5 Figure 6 Figure 4 Figure 3 Waveform I RLR8503 (Cont FET) QGSYNC CGD Drain Voltage Drain Voltage CDS VGTH QG (Control FET) QSwitch QGD Gate Voltage 0V Dead Time IRLR8103V (Sync FET) CGS Gate Voltage VGTH QG (Sync FET) 0A Figure 1 – Application Topology Figure 2 – Inter-electrode Capacitance QGS1 QGS2 Drain Current Because of the inter-electrode capacitance (Figure 2) of the Power MOSFET, specifying the RDSON of the device is not enough to ensure good performance. An optimization between RDSON and charge must be performed to insure the best performing MOSFET for a given application. Both die size and device architecture must be varied to achieve the minimum possible in-circuit losses. This is independently true for both control FET and synchronous FET. Unfortunately, the capacitances of a FET are non-linear and voltage dependent. Therefore, it is inconvenient to specify and use them effectively in switching power supply power loss estimations. This was well understood years ago and resulted in changing the emphasis from capacitance to gate charge on Power MOSFET data sheets. Table 1 – Traditional Charge Parameters Device Capacitance C GS CGS + CGD C GD Corresponding Charge Parameter QGS QG QGD Body Diode Current Drain Current Figure 3 – Control FET Waveform Figure 4 – Sync FET Waveform The waveforms are broken into segments corresponding to charge parameters. These, in turn, correspond to discrete time segments of the switching waveform. VIN g1 N1 Cont FET Coss1 2n SN g2 N2 Sync FET Coss2 2n Switch node voltage (VSN) N1 Gate Voltage N1 Current N1 Coss Discharge + N2 Coss Charge Figure 5 – QOSS Equivalent Circuit Figure 6 – QOSS Waveforms International Rectifier has recently taken the industry a step further by specifying new charge parameters that are even more specific to DC-DC converter design (Table 2). In order to understand these parameters, it is best to start with the in-circuit waveforms in Figure 3 & Figure 4. Losses may be broken into four categories: conduction loss, gate drive loss, switching loss, and output loss. The following simplified power loss equation is true for both MOSFETs in a synchronous buck converter: PLOSS = PCONDUCTION + PGATE DRIVE + PSWITCH + POUTPUT For the synchronous FET, the PSWITCH term becomes virtually zero and is ignored. www.irf.com 3 IRLR8503PbF Table 3 and Table 4 describes the event during the various charge segments and shows an approximation of losses during that period. Table 3 – Control FET Losses Description Segment Losses 2 Conduction Losses associated with MOSFET on time. IRMS is a function of load P COND = I RMS × R DS ( on) current and duty cycle. Loss Gate Drive Losses associated with charging and discharging the gate of the PIN = VG × QG × ƒ MOSFET every cycle. Use the control FET QG. Loss Switching Loss Losses during the drain voltage and drain current transitions for every full cycle. Losses occur during the QGS2 and QGD time period and can be simplified by using Qswitch. PQGS 2 ≈ VIN × IL × PQGD ≈ VIN × IL × PSWITCH ≈ VIN × IL Q GS 2 ׃ IG Q GD ׃ IG Q SW ׃ IG Output Loss Losses associated with the QOSS of the device every cycle when the control Q FET turns on. Losses are caused by both FETs, but are dissipated by the control POUTPUT = OSS × VIN × F 2 FET. Segment Losses Table 4 – Synchronous FET Losses Description Conduction Losses associated with MOSFET on time. IRMS is a function of load current and Loss duty cycle. Gate Drive Losses associated with charging and discharging the gate of the MOSFET every Loss cycle. Use the Sync FET QG. Switching Loss Generally small enough to ignore except at light loads when the current reverses in the output inductor. Under these conditions various light load power saving techniques are employed by the control IC to maintain switching losses to a negligible level. PCOND = IRMS × RDSon 2 PIN = VG × QG × ƒ PSWITCH ≈ 0 Output Loss Losses associated with the QOSS of the device every cycle when the control FET Q turns on. They are caused by the synchronous FET, but are dissipated in the control POUTPUT = OSS × VIN × ƒ 2 FET. Typical PC Application The IRLR8103V and the IRLR8503 are suitable for Synchronous Buck DC-DC Converters, and are optimized for use in next generation CPU applications. The IRLR8103V is primarily optimized for use as the low side synchronous FET (Q2) with low RDS(on) and high CdV/dt immunity.The IRLR8503 is primarily optimized for use as the high side control FET (Q2) with low cobmined Qsw and RDS(on) , but can also be used as a synchronous FET. The IRLR8503 is also tested for Cdv/dt immunity, critical for the low side socket. The typical configuration in which these devices may be used in shown in Figure 7. IRLR8503 Control FET (Q1) 1 x IRLR8103V or or 2 x IRLR8503 Synchronous FET (Q2) Figure 7. 2 & 3-FET solution for Synchronous Buck Topology. 4 www.irf.com IRLR8503PbF 2.5 Typical Characteristics IRLR8503 6.0 VGS, Gate-to-Source Voltage (V) R DS(on) , Drain-to-Source On Resistance ID = 15A VGS = 4.5V 2.0 ID = 15A VDS = 20V 4.0 (Normalized) 1.5 2.0 1.0 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 0.0 0 4 8 12 16 T J , Junction Temperature ( °C ) QG, Total Gate Charge (nC) Figure 8. Normalized On-Resistance vs. Temperature R DS(on) , Drain-to -Source On Resistance ( Ω ) 0.015 Figure 9. Gate-to-Source Voltage vs. Typical Gate Charge 2500 0.014 2000 VGS Ciss Crss Coss = = = = 0V, f = 1MHz Cgs + Cgd , Cds SHORTED Cgd Cds + Cgd C, Capacitance (pF) Ciss 1500 0.013 0.012 1000 Coss ID = 15A 0.011 500 0.010 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 0 Crss 1 10 100 V DS , Drain-to-Source Voltage (V) VGS, Gate -to -Source Voltage (V) Figure 10. Typical Rds(on) vs. Gate-to-Source Voltage 100 1000.0 Figure 11. Typical Capacitance vs. Drain-to-Source Voltage ID, Drain-to-Source Current (Α ) 100.0 T J = 150°C 10.0 T J = 25°C VDS = 15V 1.0 2.5 3.0 3.5 20µs PULSE WIDTH 4.0 4.5 5.0 5.5 VGS, Gate-to-Source Voltage (V) Figure 12. Typical Transfer Characteristics www.irf.com 5 IRLR8503PbF 10 Thermal Response (Z thJC ) 1 D = 0.50 0.20 0.10 0.05 0.1 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) PDM t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak TJ = P DM x ZthJC + TC 0.0001 0.001 0.01 0.1 1 0.01 0.00001 t1 , Rectangular Pulse Duration (sec) Figure 13. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient Inductive Load Circuit Figure 15. Switching waveform Figure 14. Clamped Inductive Load test diagram 6 www.irf.com IRLR8503PbF D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) D-Pak (TO-252AA) Part Marking Information EXAMPLE: T HIS IS AN IRFR120 WITH AS S EMBLY LOT CODE 1234 AS S EMBLED ON WW 16, 1999 IN THE AS S EMBLY LINE "A" Note: "P" in as sembly line pos ition indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO AS S EMBLY LOT CODE PART NUMBER IRFU120 12 916A 34 DAT E CODE YEAR 9 = 1999 WEEK 16 LINE A OR INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER IRFU120 12 34 DATE CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) YEAR 9 = 1999 WEEK 16 A = AS S EMBLY S ITE CODE www.irf.com 7 IRLR8503PbF D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 16.3 ( .641 ) 15.7 ( .619 ) 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. Data and specifications subject to change without notice. This product has been designed and qualified for the commercial market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.12/04 8 www.irf.com