PD- 91363E
IRLR024N IRLU024N
HEXFET® Power MOSFET
l l l l l l
Logic-Level Gate Drive Surface Mount (IRLR024N) Straight Lead (IRLU024N) Advanced Process Technology Fast Switching Fully Avalanche Rated
D
VDSS = 55V
G S
RDS(on) = 0.065Ω ID = 17A
Description
Fifth Generation HEXFET® Power MOSFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible onresistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. The D-PAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount applications.
D-Pak I-Pak IRLR024N IRLU024N
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, V GS @ 10V Continuous Drain Current, V GS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds
Max.
17 12 72 45 0.3 ± 16 68 11 4.5 5.0 -55 to + 175 300 (1.6mm from case )
Units
A W W/°C V mJ A mJ V/ns °C
Thermal Resistance
Parameter
RθJC RθJA RθJA Junction-to-Case Case-to-Ambient (PCB mount)** Junction-to-Ambient
Typ.
––– ––– –––
Max.
3.3 50 110
Units
°C/W
** When mounted on 1" square PCB (FR-4 or G-10 Material ) . For recommended footprint and soldering techniques refer to application note #AN-994
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1
2/10/00
IRLR/U024N
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
V(BR)DSS
∆V(BR)DSS/∆TJ
Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance
RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss
Min. Typ. Max. Units Conditions 55 ––– ––– V V GS = 0V, ID = 250µA ––– 0.061 ––– V/°C Reference to 25°C, ID = 1mA ––– ––– 0.065 VGS = 10V, ID = 10A ––– ––– 0.080 Ω VGS = 5.0V, ID = 10A ––– ––– 0.110 VGS = 4.0V, ID = 9.0A 1.0 ––– 2.0 V VDS = VGS, ID = 250µA 8.3 ––– ––– S VDS = 25V, ID = 11A ––– ––– 25 VDS = 55V, VGS = 0V µA ––– ––– 250 VDS = 44V, VGS = 0V, TJ = 150°C ––– ––– 100 VGS = 16V nA ––– ––– -100 VGS = -16V ––– ––– 15 ID = 11A ––– ––– 3.7 nC VDS = 44V ––– ––– 8.5 VGS = 5.0V, See Fig. 6 and 13 ––– 7.1 ––– VDD = 28V ––– 74 ––– ID = 11A ns ––– 20 ––– RG = 12Ω, VGS = 5.0V ––– 29 ––– R D = 2.4Ω, See Fig. 10 Between lead, ––– 4.5 ––– nH 6mm (0.25in.) G from package ––– 7.5 ––– and center of die contact ––– 480 ––– VGS = 0V ––– 130 ––– pF V DS = 25V ––– 61 ––– ƒ = 1.0MHz, See Fig. 5
D
S
Source-Drain Ratings and Characteristics
IS
ISM
VSD trr Qrr ton Notes:
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol ––– ––– 17 showing the A G integral reverse ––– ––– 72 S p-n junction diode. ––– ––– 1.3 V TJ = 25°C, IS = 11A, V GS = 0V ––– 60 90 ns TJ = 25°C, IF = 11A ––– 130 200 nC di/dt = 100A/µs Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11)
Pulse width ≤ 300µs; duty cycle ≤ 2%.
This is applied for I-PAK, LS of D-PAK is measured between
lead and center of die contact
VDD = 25V, starting TJ = 25°C, L = 790µH
RG = 25Ω, I AS = 11A. (See Figure 12) TJ ≤ 175°C
ISD ≤ 11A, di/dt ≤ 290A/µs, VDD ≤ V(BR)DSS,
Uses IRLZ24N data and test conditions.
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IRLR/U024N
100
V GS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP
100
10
ID , D rain-to-S ource C urrent (A )
ID , D ra in -to-S ou rce C u rrent (A )
V GS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP
10
2 .5V
1
1
2.5 V 2 0 µ s P U L S E W ID T H T J = 2 5°C
0.1 1 10
0.1
A
0.1 0.1 1
2 0 µ s P U LS E W ID T H T J = 1 75 °C
10
100
A
100
V D S , D rain-to-S ource V olta g e ( V )
V D S , D rain-to-S ource V olta g e ( V )
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
3.0
TJ = 2 5 °C
R D S (on ) , D rain -to-S ou rc e O n R es is tan c e (N orm a liz ed)
I D = 17 A 18 A
I D , D rain-to-So urce C urren t (A )
2.5
TJ = 1 7 5 °C
10
2.0
1.5
1
1.0
0.5
0.1 2 3 4 5 6
V D S = 1 5V 2 0µ s P U L S E W ID TH
7 8 9 10
A
0.0 -60 -40 -20 0 20 40 60 80
V G S = 1 0V
100 120 140 160 180
A
V G S , G ate-to -So urce Volta g e ( V )
T J , J unc tion T em perature (°C )
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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IRLR/U024N
800
V G S , G ate-to-S ource V oltage (V )
C , Capacitance (pF)
600
C i ss
V GS C is s C rs s C o ss
= = = =
0V , f = 1M H z C g s + C g d , Cd s S H O R T E D C gd C d s + C gd
15
I D = 11 A V D S = 4 4V V D S = 2 8V
12
9
400
C o ss
6
200
C r ss
3
0 1 10 100
A
0 0 4 8
F O R TE S T C IRC UIT S E E FIG U R E 1 3
12 16 20
A
V D S , D rain-to-S ourc e V olta g e ( V )
Q G , T otal G ate C har g e ( nC )
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
100
1000
I S D , R ev ers e D rain C urre nt (A )
O P E R AT ION IN TH IS AR E A LIM ITE D B Y R D S (on)
I D , D rain C urrent (A )
T J = 1 75 °C T J = 25°C
10
100 1 0µ s
10
1 00 µ s
1 0.4 0.8 1.2 1.6
VG S = 0V
A
1 1
T C = 2 5°C T J = 175°C S in g le P ulse
10
1m s 1 0m s
A
100
2.0
V S D , S ource-to-D rain V olta g e ( V )
VD S , Drain-to-Source Volta g e ( V )
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRLR/U024N
20
VDS VGS
RD
D.U.T.
+
I D , Drain Current (A)
15
RG
-VDD
5V
10
Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
5
VDS 90%
0 25 50 75 100 125 150 175
TC , Case Temperature ( ° C)
10% VGS
Fig 9. Maximum Drain Current Vs. Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
10
Therm al R esponse (Z thJ C )
D = 0 .5 0
1
0 .2 0 0 .1 0 0 .0 5 0 .0 2 0 .0 1
0.1
PD M
S IN G L E P U L S E (T H E R M A L R E S P O N S E )
N ote s: 1 . D u ty fac tor D = t
t
1 t2
1
/t
2
0.01 0.00001
2. P e a k TJ = P D M x Z th JC + T C
A
1
0.0001
0.001
0.01
0.1
t 1 , R e ctan g ula r P ulse D u ratio n (sec )
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRLR/U024N
140
E A S , S ingle Pulse Avalanc he E nergy (m J)
TO P
120
1 5V
B OTTOM
100
ID 4 .5 A 7.8 A 1 1A
VDS
L
D R IV E R
80
RG
20V tp
D .U .T
IA S
+ V - DD
60
A
0 .0 1 Ω
40
Fig 12a. Unclamped Inductive Test Circuit
20
0
V DD = 25 V
25 50 75 100 125 150
A
175
V (B R )D SS tp
S tartin g T J , J unc tion T em perature ( °C )
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
50KΩ
QG
12V
.2µF
.3µF
10 V
QGS VG QGD
VGS
3mA
D.U.T.
+ V - DS
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
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IRLR/U024N
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer
-
+
RG • • • • dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFET® MOSFETs
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IRLR/U024N
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
6 .7 3 (.2 6 5 ) 6 .3 5 (.2 5 0 ) -A5 .4 6 (.2 1 5 ) 5 .2 1 (.2 0 5 ) 4 1 .2 7 (.0 5 0 ) 0 .8 8 (.0 3 5 )
2 .3 8 (.0 9 4 ) 2 .1 9 (.0 8 6 )
1 .1 4 (.0 4 5 ) 0 .8 9 (.0 3 5 ) 0 .5 8 (.0 2 3 ) 0 .4 6 (.0 1 8 )
6 .4 5 (.2 4 5 ) 5 .6 8 (.2 2 4 ) 6 .2 2 (.2 4 5 ) 5 .9 7 (.2 3 5 ) 1.0 2 (.0 4 0 ) 1.6 4 (.0 2 5 ) 1 2 3 0 .5 1 (.0 2 0 ) M IN . 1 0 .4 2 (.4 1 0 ) 9 .4 0 (.3 7 0 )
L E A D A S S IG N M E N T S 1 - GATE 2 - D R A IN 3 - S OU R CE 4 - D R A IN
-B 1 .5 2 (.0 6 0 ) 1 .1 5 (.0 4 5 ) 1 .1 4 (.0 4 5 ) 0 .7 6 (.0 3 0 ) 2 .2 8 ( .0 9 0 ) 4 .5 7 ( .1 8 0 ) 0 .8 9 (.0 3 5 ) 3X 0 .6 4 (.0 2 5 ) 0 .2 5 ( .0 1 0 ) M AMB N O TE S :
2X
0 .5 8 (.0 2 3 ) 0 .4 6 (.0 1 8 )
1 D IM E N S IO N IN G & T O L E R A N C IN G P E R A N S I Y 1 4 .5 M , 1 9 8 2 . 2 C O N T R O L L IN G D IM E N S IO N : IN C H . 3 C O N F O R M S T O J E D E C O U T L IN E T O -2 5 2 A A . 4 D IM E N S IO N S S H O W N A R E B E F O R E S O L D E R D IP , S O L D E R D IP M A X. + 0 .1 6 (.0 0 6 ) .
D-Pak (TO-252AA) Part Marking Information
8
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IRLR/U024N
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
6 .7 3 (.26 5 ) 6 .3 5 (.25 0 ) -A 5 .4 6 (.2 1 5 ) 5 .2 1 (.2 0 5 ) 4 1 .2 7 (.0 5 0 ) 0 .8 8 (.0 3 5 )
2 .3 8 (.0 9 4 ) 2 .1 9 (.0 8 6 ) 0 .5 8 (.0 2 3 ) 0 .4 6 (.0 1 8 ) L E A D A S S IG N M E N T S 1 - G A TE 2 - D R A IN 3 - S OUR C E 4 - D R A IN
6 .4 5 (.2 4 5 ) 5 .6 8 (.2 2 4 ) 1 .5 2 (.0 6 0 ) 1 .1 5 (.0 4 5 ) 1 -B 2.2 8 (.0 9 0) 1.9 1 (.0 7 5) 9 .6 5 (.3 8 0 ) 8 .8 9 (.3 5 0 ) 2 3 6 .2 2 (.2 4 5 ) 5 .9 7 (.2 3 5 )
N O TE S : 1 D IM E N S IO N IN G & TO L E R A N C IN G P E R A N S I Y 1 4 .5 M , 19 8 2 . 2 C O N T R O L L IN G D IM E N S IO N : IN C H . 3 C O N F O R M S T O J E D E C O U TL IN E T O -2 5 2 A A . 4 D IM E N S IO N S S H O W N A R E B E F O R E S O L D E R D IP , S O L D E R D IP M A X . + 0 .1 6 (.0 0 6 ).
3X
1 .1 4 (.0 45 ) 0 .7 6 (.0 30 )
3X
0 .8 9 ( .0 3 5 ) 0 .6 4 ( .0 2 5 ) M AMB
1 .1 4 (.0 4 5 ) 0 .8 9 (.0 3 5 ) 0 .58 (.0 2 3 ) 0 .46 (.0 1 8 )
2 .2 8 (.0 9 0 ) 2X
0 .2 5 (.0 1 0 )
I-Pak (TO-251AA) Part Marking Information
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IRLR/U024N
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
TRL
1 6.3 ( .641 ) 1 5.7 ( .619 )
16 .3 ( .641 ) 15 .7 ( .619 )
12 .1 ( .4 76 ) 11 .9 ( .4 69 )
F E E D D IR E C T IO N
8.1 ( .318 ) 7.9 ( .312 )
F E E D D IR E C T IO N
NO T ES : 1. C O N T R O LL IN G D IM E N S IO N : M ILLIM E T E R . 2. A LL D IM E N S IO N S A R E S H O W N IN M ILL IM E T E R S ( IN C H E S ). 3. O U T L IN E C O N F O R M S T O E IA -4 81 & E IA -54 1.
13 IN C H
16 m m NOTES : 1. O U T LIN E C O N F O R M S T O E IA -481 .
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020 IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111 IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086 IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371 Data and specifications subject to change without notice. 2/10
10
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