IRLU120N

PD - 91541B IRLR/U120N HEXFET® Power MOSFET l l l l l Surface Mount (IRLR120N) Straight Lead (IRLU120N) Advanced Process Technology Fast Switching Fully Avalanche Rated D VDSS = 100V G S RDS(on) = 0.185Ω ID = 10A Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. The D-PAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU series) is for throughhole mounting applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount applications. D -P A K T O -2 52 A A I-P A K T O -25 1 A A Absolute Maximum Ratings Parameter ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current † Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy‚† Avalanche Current† Repetitive Avalanche Energy† Peak Diode Recovery dv/dt ƒ Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Max. 10 7.0 35 48 0.32 ± 16 85 6.0 4.8 5.0 -55 to + 175 300 (1.6mm from case ) Units A W W/°C V mJ A mJ V/ns °C Thermal Resistance Parameter RθJC RθJA RθJA Junction-to-Case Junction-to-Ambient (PCB mount) ** Junction-to-Ambient Typ. ––– ––– ––– Max. 3.1 50 110 Units °C/W www.irf.com 1 5/11/98 IRLR/U120N Electrical Characteristics @ TJ = 25°C (unless otherwise specified) V(BR)DSS ∆V(BR)DSS/∆TJ Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Min. 100 ––– ––– ––– ––– 1.0 3.1 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– Typ. ––– 0.12 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 4.0 35 23 22 Max. Units Conditions ––– V VGS = 0V, ID = 250µA ––– V/°C Reference to 25°C, ID = 1mA 0.185 VGS = 10V, ID = 6.0A „ 0.225 W VGS = 5.0V, ID = 6.0A „ 0.265 VGS = 4.0V, ID = 5.0A „ 2.0 V VDS = VGS, ID = 250µA ––– S VDS = 25V, ID = 6.0A† 25 VDS = 100V, VGS = 0V µA 250 VDS = 80V, VGS = 0V, TJ = 150°C 100 VGS = 16V nA -100 VGS = -16V 20 ID = 6.0A 4.6 nC VDS = 80V 10 VGS = 5.0V, See Fig. 6 and 13 „† ––– VDD = 50V ––– ID = 6.0A ns ––– RG = 11Ω, VGS = 5.0V ––– RD = 8.2Ω, See Fig. 10 „† Between lead, 4.5 ––– nH 6mm (0.25in.) G from package 7.5 ––– and center of die contact… 440 ––– VGS = 0V 97 ––– pF VDS = 25V 50 ––– ƒ = 1.0MHz, See Fig. 5† D S Source-Drain Ratings and Characteristics IS ISM VSD trr Qrr ton Notes: Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) † Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time Min. Typ. Max. Units Conditions D MOSFET symbol 10 ––– ––– showing the A G integral reverse ––– ––– 35 p-n junction diode. S ––– ––– 1.3 V TJ = 25°C, IS = 6.0A, VGS = 0V „ ––– 110 160 ns TJ = 25°C, IF =6.0A ––– 410 620 nC di/dt = 100A/µs „† Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)  Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 ) ‚ VDD = 25V, starting TJ = 25°C, L = 4.7mH RG = 25Ω, IAS = 6.0A. (See Figure 12) TJ ≤ 175°C „ Pulse width ≤ 300µs; duty cycle ≤ 2%. … This is applied for I-PAK, LS of D-PAK is measured between lead and center of die contact ƒ ISD ≤ 6.0A, di/dt ≤ 340A/µs, VDD ≤ V(BR)DSS, † Uses IRL520N data and test conditions. ** When mounted on 1" square PCB (FR-4 or G-10 Material ) . For recommended footprint and soldering techniques refer to application note #AN-994 2 www.irf.com IRLR/U120N 100 ID , D rain-to-S ource C urrent (A ) 10 ID , D rain-to-S ource C urrent (A ) V GS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP 100 V GS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP 10 2.5V 1 1 2.5V 0.1 0.1 1 2 0µ s P U LS E W ID TH T J = 25°C 10 A 0.1 0.1 1 2 0µ s P U LS E W ID TH T J = 175°C 10 100 A 100 V D S , D rain-to-S ource V oltage (V ) V D S , D rain-to-S ource V oltage (V ) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 100 3.0 R D S (on ) , D rain-to-S ource O n R esistance (N orm alized) I D = 1 0A I D , D ra in -to-S o urc e C urren t (A ) T J = 2 5 °C 10 2.5 T J = 1 7 5 °C 2.0 1.5 1 1.0 0.5 0.1 VDS = 5 0V 2 0 µ s P U L S E W ID T H 2 4 6 8 10 A 0.0 -60 -40 -20 0 20 40 60 80 V G S = 1 0V and 100 120 140 160 180 A V G S , G a te -to -S o u rc e V o lta g e ( V ) T J , Junction T em perature (°C ) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3 IRLR/U120N 800 V G S , G ate-to-S ource V oltage (V ) V GS C iss C rss C oss = = = = 0V , f = 1M H z C gs + C gd , C ds S H O R TE D C gd C ds + C gd 15 I D = 6.0A V D S = 8 0V V D S = 50V V D S = 20V 12 C , C apacitanc e (pF ) 600 C is s 9 400 C oss 200 6 C rs s 3 0 1 10 100 A 0 0 5 10 F O R TE S T C IR C U IT S E E FIG U R E 13 15 20 25 A V D S , D rain-to-S ource V oltage (V ) Q G , Total G ate C harge (nC ) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 100 100 I S D , R everse D rain C urrent (A ) O P E R A TIO N IN TH IS A R E A LIM ITE D B Y R D S (on) 10µ s 10 TJ = 175°C I D , D rain C urrent (A ) 10 100µ s T J = 25°C 1m s 1 10 m s 1 0.1 0.4 0.6 0.8 1.0 V G S = 0V 1.2 A 0.1 1 T C = 2 5°C T J = 175°C S ingle P ulse 10 100 A 1000 1.4 V S D , S ource-to-D rain V olta g e (V ) V D S , D rain-to-S ource V oltage (V ) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRLR/U120N 10 VDS 8 RD VGS RG I D , D rain C urrent (A m ps) D.U.T. + -VDD 6 5.0V Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % 4 Fig 10a. Switching Time Test Circuit 2 VDS 90% 0 25 50 75 100 125 150 A 175 TC , C ase T em perature (°C ) Fig 9. Maximum Drain Current Vs. Case Temperature 10% VGS td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms 10 Thermal Response (Z thJC ) D = 0.50 1 0.20 0.10 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) P DM t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak TJ = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 0.1 0.01 0.00001 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRLR/U120N 200 E A S , S ingle P ulse A valanc he E nergy (m J) TO P 160 15V B O TTO M ID 2.4A 4.2A 6.0 A VDS L D R IV E R 120 RG 10V D .U .T IA S tp + V - DD 80 A 0 .0 1 Ω 40 Fig 12a. Unclamped Inductive Test Circuit 0 25 50 75 100 125 150 A 175 V (B R )D S S tp S tarting T J , Junc tion T em perature (°C ) Fig 12c. Maximum Avalanche Energy Vs. Drain Current IAS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ QG 12V .2µF .3µF 5.0 V QGS VG QGD VGS 3mA D.U.T. + V - DS Charge IG ID Current Sampling Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit 6 www.irf.com IRLR/U120N Peak Diode Recovery dv/dt Test Circuit D.U.T + ƒ + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer ‚ - „ +  RG • • • • dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test + VDD Driver Gate Drive P.W. Period D= P.W. Period VGS=10V * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt VDD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS www.irf.com 7 IRLR/U120N Package Outline TO-252AA Outline Dimensions are shown in millimeters (inches) 6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 6.45 (.245) 5.68 (.224) 6.22 (.245) 5.97 (.235) 1.02 (.040) 1.64 (.025) 1 2 3 0.51 (.020) M IN. 10.42 (.410) 9.40 (.370) 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) LE A D A S S IG N M E N T S 1 - GATE 2 - D R A IN 3 - SOURCE 4 - D R A IN -B1.52 (.060) 1.15 (.045) 3X 2X 1.14 (.045) 0.76 (.030) 2.28 (.090) 4.57 (.180) 0.89 (.035) 0.64 (.025) 0.25 (.010) M AMB 0.58 (.023) 0.46 (.018) N O TE S : 1 D IM E N S IO N IN G & TO LE R A N C IN G P E R A N S I Y 14.5M , 1982. 2 C O N TR O LLIN G D IM E N S IO N : IN C H . 3 C O N F O R M S T O JE D E C O U TLIN E TO -252A A . 4 D IM E N S IO N S S H O W N A RE B E F O R E S O LD E R D IP , S O LD E R D IP M A X. +0.16 (.006). Part Marking Information TO-252AA (D-PARK) E XA M P L E : TH IS IS A N IR F R 1 20 W IT H A S S E M B LY LOT CODE 9U1P IN TE R N A TIO N A L R E C T IF IE R LO G O A IR F R 1 20 9U 1P F IR S T P O R TIO N OF PART NUMBER A S S E M B LY LOT CODE S E C O N D P O R TIO N OF PART NUMBER 8 www.irf.com IRLR/U120N Package Outline TO-251AA Outline Dimensions are shown in millimeters (inches) 6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 6.45 (.245) 5.68 (.224) 1.52 (.060) 1.15 (.045) 1 -B2.28 (.090) 1.91 (.075) 9.65 (.380) 8.89 (.350) 2 3 N O TE S : 1 D IM E N S IO N IN G & TO LE R A N C IN G P E R A N S I Y 14.5M , 1982. 2 C O N T R O LLIN G D IM E N S IO N : IN C H . 3 C O N F O R M S TO J E D E C O U T LIN E T O -252A A . 4 D IM E N S IO N S S H O W N A R E B E F O R E S O LD E R D IP , S O LD E R D IP M A X. +0.16 (.006). 1.14 (.045) 0.76 (.030) 6.22 (.245) 5.97 (.235) 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 0.58 (.023) 0.46 (.018) LE A D A S S IG N M E N T S 1 - GATE 2 - D R A IN 3 - SOURCE 4 - D R A IN 3X 3X 0.89 (.035) 0.64 (.025) M AMB 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) 2.28 (.090) 2X 0.25 (.010) Part Marking Information TO-251AA (I-PARK) E X A M P L E : T H IS IS A N IR F U 1 2 0 W IT H A S S E M B L Y LO T C OD E 9U 1P IN T E R N A T IO N A L R E C TIF IE R LO GO IR F U 120 9U 1P F IR S T P O R T IO N OF PART NUMBER ASSEMBLY LOT CODE S E C O N D P O R T IO N OF PART NUMBER www.irf.com 9 IRLR/U120N Tape & Reel Information TO-252AA TR TRR TRL 1 6.3 ( .6 41 ) 1 5.7 ( .6 19 ) 16 .3 ( .64 1 ) 15 .7 ( .61 9 ) 12 .1 ( .4 7 6 ) 11 .9 ( .4 6 9 ) F E E D D IR E C T IO N 8 .1 ( .3 18 ) 7 .9 ( .3 12 ) F E E D D IR E C T IO N NOTES : 1 . C O N T R O LL IN G D IM E N S IO N : M ILL IM E T E R . 2 . A LL D IM E N S IO N S A R E S H O W N IN M ILL IM E T E R S ( IN C H E S ). 3 . O U T L IN E C O N F O R M S T O E IA -4 81 & E IA -54 1. 1 3 IN C H 16 m m NO TES : 1. O U T L IN E C O N F O R M S T O E IA -4 81 . WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020 IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T 3Z2, Tel: (905) 453 2200 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111 IR FAR EAST: 171 (K&H Bldg.) 30-4 Nishi-ikebukuro 3-chome, Toshima-ku, Tokyo Japan Tel: 81 33 983 0086 IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 16907 Tel: 65 221 8371 Data and specifications subject to change without notice. 5/98 10 www.irf.com