IRS21091PBF

Data Sheet No. PD60311 IRS21091(S)PbF Features • • • • • • • • • • • • • • Floating channel designed for bootstrap operation Fully operational to +600 V Tolerant to negative transient voltage, dV/dt immune Gate drive supply range from 10 V to 20 V Undervoltage lockout for both channels 3.3 V, 5 V, and 15 V input logic compatible Cross-conduction prevention logic Matched propagation delay for both channels High-side output in phase with IN input Logic and power ground +/- 5 V offset Internal 500 ns deadtime, and programmable up to 5 µs with one external RDT resistor Lower di/dt gate driver for better noise immunity The dual function DT/SD input turns off both channels RoHS compliant HALF-BRIDGE DRIVER Product Summary VOFFSET IO+/VOUT ton/off (typ.) Deadtime 600 V max. 120 mA / 250 mA 10 V - 20 V 750 ns & 200 ns 540 ns Packages Description The IRS21091 is a high voltage, high speed power MOSFET and IGBT driver with dependent high- and low-side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is 8 Lead PDIP 8 Lead SOIC compatible with standard CMOS or LSTTL output, IRS21091 IRS21091S down to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration which operates up to 600 V. Typical Connection VCC up to 600 V VCC IN DT/SD VB HO VS LO TO LOAD IN DT/SD COM (Refer to Lead Assignments for correct configuration). These diagrams show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1 IRS21091(S)PbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VB VS VHO VCC VLO DT/SD VIN dVS/dt PD RthJA TJ TS TL Definition High-side floating absolute voltage High-side floating supply offset voltage High-side floating output voltage Low-side and logic fixed supply voltage Low-side output voltage Programmable deadtime and shutdown pin voltage Logic input voltage (IN & DT/SD) Allowable offset supply voltage transient Package power dissipation @ TA ≤ +25 °C Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) (8 Lead PDIP) (8 Lead SOIC) (8 Lead PDIP) (8 Lead SOIC) Min. -0.3 VB - 25 VS - 0.3 -0.3 -0.3 VSS - 0.3 VSS - 0.3 — — — — — — -50 — Max. 625 VB + 0.3 VB + 0.3 25 VCC + 0.3 VCC + 0.3 VCC + 0.3 50 1.0 0.625 125 200 150 150 300 Units V V/ns W °C/W °C www.irf.com 2 IRS21091(S)PbF Recommended Operating Conditions The input/output logic timing diagram is shown in Fig.1. For proper operation the device should be used within the recommended conditions. The VS offset rating is tested with all supply biased at a 15 V differential. Symbol VB VS VHO VCC VLO VIN DT/SD TA Definition High-side floating supply absolute voltage High-side floating supply offset voltage High-side floating output voltage Low-side and logic fixed supply voltage Low-side output voltage Logic input voltage (IN & DT/SD) Programmable deadtime and shutdown pin voltage Ambient temperature Min. (Note 1) VS 10 0 V SS V SS -40 VS + 10 Max. VS + 20 600 VB 20 VCC VCC VCC 125 Units V °C Note 1: Logic operational for VS of -5 V to +600 V. Logic state held for VS of -5 V to -VBS. (Please refer to the Design Tip DT97-3 for more details). Dynamic Electrical Characteristics VBIAS (VCC, VBS) = 15 V, CL = 1000 pF, TA = 25 °C, unless otherwise specified. Symbol ton toff tsd MT tr tf DT MDT Definition Turn-on propagation delay Turn-off propagation delay Shutdown propagation delay Delay matching, HS & LS turn-on/off Turn-on rise time Turn-off fall time Deadtime: LO turn-off to HO turn-on(DTLO-HO) & HO turn-off to LO turn-on (DTHO-LO) Deadtime matching = DTLO - HO - DTHO-LO Min. — — — — — — 400 4 — — Typ. 750 200 550 0 100 35 540 5 0 0 Max. Units Test Conditions 950 280 715 70 220 80 680 6 60 600 µs ns ns VS = 0 V RDT= 0 Ω RDT = 200 kΩ RDT= 0 Ω RDT = 200 kΩ VS = 0 V VS = 0 V or 600 V www.irf.com 3 IRS21091(S)PbF Static Electrical Characteristics VBIAS ( VCC , VBS) = 15 V, and TA = 25 °C unless otherwise specified. The VIL, VIH, and IIN parameters are referenced to COM and are applicable to the respective input leads: IN and DT/SD. The VO, IO, and Ron parameters are referenced to COM and are applicable to the respective output leads: HO and LO. Symbol VIH VIL VSD,TH VOH VOL ILK IQBS IQCC IIN+ IINVCCUV+ VBSUV+ VCCUVVBSUVVCCUVH VBSUVH IO+ IO- Definition Logic “1” input voltage for HO & logic “0” for LO Logic “0” input voltage for HO & logic “1” for LO DT/SD input threshold High level output voltage, VBIAS - VO Low level output voltage, VO Offset supply leakage current Quiescent VBS supply current Quiescent VCC supply current Logic “1” input bias current Logic “0” input bias current VCC and VBS supply undervoltage positive going threshold VCC and VBS supply undervoltage negative going threshold Hysteresis Output high short circuit pulsed current Output low short circuit pulsed current Min. Typ. Max. Units Test Conditions 2.5 — 11.5 — — — 20 0.4 — — 8.0 7.4 0.3 120 250 — — 13 0.05 0.02 — 75 1.0 5 — 8.9 8.2 0.7 290 600 — 0.8 14.5 0.2 0.1 50 130 1.6 20 5 9.8 9.0 — — — mA VO = 0 V, PW ≤ 10 µs VO = 15 V,PW ≤ 10 µs V µA mA µA V IO = 2 mA VB = VS = 600 V IN = 0 V or 5 V IN = 0 V or 5 V RDT = 0 Ω IN = 5 V, DT/SD = 0 V IN = 0 V, DT/SD = 5 V VCC = 10 V to 20 V Lead Assignments 1 2 3 4 VCC IN DT/SD COM VB HO VS LO 8 7 6 5 1 2 3 4 VCC IN DT/SD COM VB HO VS LO 8 7 6 5 8 Lead PDIP 8 Lead SOIC IRS21091PbF www.irf.com IRS21091SPbF 4 IRS21091(S)PbF Functional Block Diagrams VB UV DETECT R HV LEVEL SHIFTER PULSE GENERATOR PULSE FILTER R S Q HO IN VSS/COM LEVEL SHIFT VS DT/SD DEADTIME UV DETECT VCC LO COM VSS/COM LEVEL SHIFT DELAY Lead Definitions Symbol Description IN DT/SD VB HO VS VCC LO COM Logic input for high-side and low-side gate driver outputs (HO and LO), in phase with HO Programmable deadtime lead,disables input/output logic when tied to VCC High-side floating supply High-side gate drive output High-side floating supply return Low-side and logic fixed supply Low-side gate drive output Low-side return www.irf.com 5 IRS21091(S)PbF IN DT/SD HO LO Figure 1. Input/Output Timing Diagram IN(LO) 50% 50% toff 90% 90% tf IN(HO) ton tr LO HO 10% 10% Figure 2. Switching Time Waveform Definitions 50% 50% IN 50% DT/SD tsd HO LO 90% HO LO DT LO-HO 90% 10% 90% DTHO-LO 10% MDT= DTLO-HO - DTHO-LO Figure 3. Shutdown Waveform Definitions Figure 4. Deadtime Waveform Definitions IN (LO) 50% 50% IN (HO) LO HO 10% MT 90% MT LO HO Figure 5. Delay Matching Waveform Definitions www.irf.com 6 IRS21091(S)PbF Note: For the following figures the VBIAS (VCC, VBS) = 15 V and TA = 25 OC unless otherwise specified. 1300 1300 Turn- on Propagation Delay ( ns ) 1100 Tur n- on Pr opagation Delay ( ns ) 1100 M ax. 900 M ax . Typ. 900 Typ. 700 700 500 -50 -25 0 25 50 o 75 100 125 5 00 10 12 14 16 18 20 Temperature ( C) V BIAS Supply Voltage (V) Figure 6B. Turn-On Propagation Delay vs. Supply Voltage Figure 6A. Turn-on Propagation Delay Figure 6A. Turn-On Propagation Delay vs. Temperature 500 500 Tur n- of f Pr opagation Delay ( ns ) Tur n- of f Pr opagation Delay ( ns ) 400 400 M ax. Typ. 200 300 M ax. Typ. 100 300 200 100 0 -50 -25 0 25 50 o 0 75 100 125 10 12 14 16 18 20 Temperature ( C) V BIAS Supply Voltage (V) Figure 7A. Turn-off Propagation Delay Figure 7A. Turn-Off Propagation Delay vs. Temperature Figure 7B. Turn-off Propagation Delay Figure 7B. Turn-Off Propagation Delay vs. Supply Voltage www.irf.com 7 IRS21091(S)PbF 500 500 SD Propagation Delay (ns) 400 SD Propagation Delay (ns) 400 M ax. 300 Typ. 200 300 M ax. 200 Typ. 100 100 0 50 25 0 25 50 o 0 75 100 125 10 12 14 16 18 20 Temperature ( C) Figure 8A. SD Propagation Delay vs. Temperature V BIAS Supply Voltage (V) Figure 8B. SD Propagation Delay vs. Supply Voltage 5 00 T urn-O n Rise i e (ns ) s m Turn-On R i e TTime (ns) 4 00 3 00 2 00 Max. 50 0 Turn-Onn Rise T i e (ns ) T urn-O R i e Time (ns) s m 40 0 30 0 Max. 20 0 Typ. 1 00 Typ. 10 0 0 0 -5 0 -2 5 0 25 50 75 1 00 1 25 Temperature(oC) Figure 9A. Turn-On Rise Time vs. Temperature 10 12 14 16 18 20 V BIAS Supply Voltage (V) Figure 9B. Turn-On Rise Time vs. Supply Volta ge www.irf.com 8 IRS21091(S)PbF 200 Turn-u r nf- O allFTilmeme s) s T Of F ff a l T i (n n Turn-Off Fall Time (ns) 200 150 100 M ax. 150 100 Max. 50 50 Typ. Typ. 0 -50 0 10 12 14 16 18 20 V BIAS Supply Voltage (V) Figure 10B. Turn-Off Fall Time vs. Supply Voltage -25 0 25 50 75 100 125 Temperature ( oC) Figure 10A. Turn-Off Fall Time vs. Temperature 1000 1000 800 800 M ax. Deadtime (ns) Deadtime (ns) M ax. 600 Typ. 400 M in. 600 Typ. M in. 400 200 -50 -25 0 25 50 o 200 75 100 125 10 12 14 16 18 20 Temperature ( C) Figure 11A. Deadtime vs. Temperature V BIAS Supply Voltage (V) Figure 11B. Deadtime vs. Supply Voltage www.irf.com 9 IRS21091(S)PbF 7 6 5 4 3 2 1 0 0 50 100 150 200 M ax. Typ. M in. 5 Input Voltage (V) 4 3 2 1 -50 Deadt (µ ( D ead tim eime s )s ) Min. -25 0 25 50 75 100 125 RDT ((KΩ) RDT kΩ) Figure 11C. Deadtime vs. R DT Temperature (°C) Figure 12A. Logic “1” Input Voltage vs. Temperat re u 5 Lo gic "0" Input Bia s Curr ent ( µA) 6 5 4 3 2 1 0 -50 -25 0 25 50 75 100 125 Max Input Voltage (V) 4 3 2 1 10 12 14 16 18 20 V BIAS Supply Voltage (V) Figure 12B. Logic “1” Input Voltage vs. Supply Voltage Min. Temperature (°C) Figure 13A. Logic "0" Input Bias Current vs. Temperature www.irf.com 10 IRS21091(S)PbF Logic "0" Input Bias Current (µA) 6 5 4 3 2 1 0 10 12 14 16 18 20 Supply Voltage (V) Figure 13B. Logic "0" Input Bias Current vs. Voltage Max SD Input threshold (+) (V) 18 16 14 12 10 8 -50 Max. -25 0 25 50 75 100 125 Temperature (oC) Figure 14A. SD Input Positive Going Threshold (+) vs. Temperature 16 14 12 10 8 10 High Level Output Voltage (V) 18 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0.0 0.0 -50 10 -50 Max. SD Input threshold (+) (V) Max. Typ. 12 14 16 18 20 V CC Supply Voltage (V) Figure 14B. SD Input Positive Going Threshold (+) vs. Supply Voltage -25 -25 0 0 25 25 50 50 o 75 75 100 100 125 125 Temperature ( o C) Temperature ( C) Figure 15A. High Level Output Voltage vs. Temperature www.irf.com 11 IRS21091(S)PbF High Level Output Voltage (V) 0.4 0.3 0.2 0.1 0.0 Typ. Max. Low Level Output Voltage (V) 0.5 0.5 0.4 0.3 0.2 0.1 Max. Typ. 10 12 14 16 18 20 0.0 -50 -25 0 25 50 o 75 100 125 VBIAS Supply Voltage (V) Figure 15B. High Level Output Voltage vs. Supply Voltage Temperature ( C) Figure 16A. Low Level Output Voltage vs. Temperature 0.4 0.3 0.2 Max. Of fssetSupppyyLeaakageC uurrent t(µ A) ) Off et Sup l l Le kage C r ren ( A Low Level Output Voltage (V) 0.5 500 400 300 200 0.1 Typ. 100 M ax. 0 -50 -25 0 25 50 75 100 125 0 10 12 14 16 18 20 VBIAS Supply Voltage (V) Figure 16B. Low Level Output Voltage vs. Supply Voltage Temperature ( oC) Figure 17A. Offset Supply Leakage Current vs. Temperature www.irf.com 12 IRS21091(S)PbF Of fs et Supply Leakage C urr ent (µ A) 500 400 V BS Supply Current (μA) 300 200 Max. 400 300 200 100 0 -50 Typ. Min. 100 Max. 0 0 100 200 300 400 500 600 -25 0 25 50 75 100 125 VB Boost Voltage (V) Figure 17B. Offset Supply Leakage Current vs. Boost Voltage Temperature (oC) Figure 18A. VBS Supply Current vs. Temperature 400 V BS Supply Current (μA) 300 200 100 0 10 12 14 16 18 20 Max. Typ. Min. 3.0 2.5 2.0 1.5 Typ. 1.0 0.5 0.0 -50 -25 0 25 50 75 100 125 M in. VCc cSSuplply Curr r en (( mA ) V C upp y Cu rent mA) M ax. Supply Voltage (V) Figure 18B. VBS Supply Current vs. Supply Voltage Temperature (oC) Figure 19A. VCC Supply Current vs. Temperature www.irf.com 13 IRS21091(S)PbF 3.0 60 Logicc “"1"Input t Curr r ent(( A)) Logi 1” Inpu Cu rent m A 12 14 16 18 20 V CC Supply Cur r ent ( mA ) 2.5 2.0 1.5 1.0 0.5 0.0 10 M ax. Typ. M in. 50 40 30 20 10 0 -50 -25 0 25 50 75 100 125 M ax. Typ. Figure 20B. V V CC Supply Voltage (V) S upply Current Temperature ( oC) Figure 19B. VCC Supply Current vs. VCC Supply Voltage Figure 20A. Logic “1” Input Current vs. Temperature 60 10 Logic 0” Input Current (µ A) Logic 1 u n A) Logic “"1”" IInputt Currentt (mA) 50 40 30 20 10 0 10 12 14 16 18 20 M ax. 8 Max. 6 4 2 0 -50 Typ. -25 0 25 50 75 100 125 V CC Supply Voltage (V) Figure 21B. Logic "1" Input Current Temperature (oC) Figure 21A. Logic “0” Input Current vs. Temperature Figure 20B. Logic “1” Input Current vs. Supply Voltage www.irf.com 14 IRS21091(S)PbF 10 8 M ax. 12 V CC UV LO Threshold (+) (V ) 12 14 16 18 20 Logic 0” Input Current (µ A) 11 6 4 2 0 10 V CC Supply Voltage (V) Figure 21B. Logic “0” Input Currentt vs. Supply Voltage 10 M ax. 9 Typ. M in. 8 7 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Figure 22. VCC Undervoltage Threshold (+) vs. Temperature 11 12 V B S UV LO Thr es hold (+) ( V ) 0 25 50 75 100 125 V CC UV LO Thr eshold (- ) (V ) 10 M ax. Typ. 8 M in. 7 11 M ax. 9 10 9 Typ. 8 M in. 6 -50 -25 7 -50 -25 0 25 50 o 75 100 125 Temperature ( oC) Figure 23. VCC Undervoltage Threshold (-) vs. Temperature Temperature ( C) Figure 24. VBS Undervoltage Threshold (+) vs. Temperature www.irf.com 15 IRS21091(S)PbF 11 500 Output Source Current (mA) 400 300 200 100 0 -50 -25 0 25 50 o V B S UV LO Thr es hold ( -) (V ) 10 M ax. Typ. 8 M in. 7 Typ. 9 Min. 6 75 100 125 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Figure 25. VBS Undervoltage Threshold (-) vs. Temperature Temperature ( C) Figure 26A. Output Source Current vs. Tem perature 500 Output Source Current (mA) Ou u Sin C rre e ( Outputt SinkkCuurrntn m A) ) 1000 800 600 400 200 Min. Typ. 400 300 200 100 0 Typ. Min. 10 12 14 16 18 20 0 -50 -25 0 25 50 75 100 125 V BIAS Supply Voltage (V) Figure 26B. Output Source Current vs. Supply Voltage Temperature (oC) Figure 27A. Output Sink Current vs. Temperature www.irf.com 16 IRS21091(S)PbF 1000 800 600 400 Typ. 0 V S Offset Supply Voltage (V) Ouuput SiinkkCuurrnt nmA) O ttput S n C rre e ( -2 Typ. -4 -6 200 Min. -8 0 10 12 14 16 18 20 VBIAS Supply Voltage (V) Figure 27B. Output Sink Currentt vs. Supply Voltage -10 10 12 14 16 18 20 V BS Floating Supply Voltage (V) Figure 28. Maximum VS Negative Offset vs. Supply Voltage www.irf.com 17 IRS21091(S)PbF Case Outlines 8 Lead PDIP 01-6014 01-3003 01 (MS-001AB) D A 5 B FOOTPRINT 8X 0.72 [.028] DIM A b c D INCHES MIN .0532 .013 .0075 .189 .1497 MAX .0688 .0098 .020 .0098 .1968 .1574 MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 A1 .0040 6 E 8 7 6 5 H 0.25 [.010] A E 6.46 [.255] 1 2 3 4 e e1 H K L 8X 1.78 [.070] .050 BASIC .025 BASIC .2284 .0099 .016 0° .2440 .0196 .050 8° 1.27 BASIC 0.635 BASIC 5.80 0.25 0.40 0° 6.20 0.50 1.27 8° 6X e e1 3X 1.27 [.050] y A C 0.10 [.004] y K x 45° 8X b 0.25 [.010] NOTES: A1 CAB 8X L 7 8X c 1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. 2. CONTROLLING DIMENSION: MILLIMETER 3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INC HES]. 4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA. 5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006]. 6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010]. 7 DIMENSION IS THE LENG TH OF LEAD FOR SOLDERING TO A SUBSTRATE. 8 Lead SOIC www.irf.com 01-6027 01-0021 11 (MS-012AA) 18 IRS21091(S)PbF Tape & Reel 8-lead SOIC LOAD ED TA PE FEED DIRECTION B A H D F C N OTE : CO NTROLLING D IMENSION IN M M E G C A R R I E R T A P E D IM E N S I O N F O R 8 S O I C N M etr ic Im p e r i a l Cod e M in M ax M in M ax A 7 .9 0 8 .1 0 0 . 31 1 0 .3 1 8 B 3 .9 0 4 .1 0 0 . 15 3 0 .1 6 1 C 1 1 .7 0 1 2.30 0 .4 6 0 .4 8 4 D 5 .4 5 5 .5 5 0 . 21 4 0 .2 1 8 E 6 .3 0 6 .5 0 0 . 24 8 0 .2 5 5 F 5 .1 0 5 .3 0 0 . 20 0 0 .2 0 8 G 1 .5 0 n/ a 0 . 05 9 n/ a H 1 .5 0 1 .6 0 0 . 05 9 0 .0 6 2 F D C E B A G H R E E L D IM E N S I O N S F O R 8 S O IC N M etr ic Im p e r i a l Cod e M in M ax M in M ax A 3 2 9. 6 0 3 3 0 .2 5 1 2 .9 7 6 1 3 .0 0 1 B 2 0 .9 5 2 1.45 0 . 82 4 0 .8 4 4 C 1 2 .8 0 1 3.20 0 . 50 3 0 .5 1 9 D 1 .9 5 2 .4 5 0 . 76 7 0 .0 9 6 E 9 8 .0 0 1 0 2 .0 0 3 . 85 8 4 .0 1 5 F n /a 1 8.40 n /a 0 .7 2 4 G 1 4 .5 0 1 7.10 0 . 57 0 0 .6 7 3 H 1 2 .4 0 1 4.40 0 . 48 8 0 .5 6 6 www.irf.com 19 IRS21091(S)PbF LEADFREE PART MARKING INFORMATION Part number IRxxxxxx S YWW? ?XXXX Lot Code (Prod mode - 4 digit SPN code) IR logo Date code Pin 1 Identifier ? P MARKING CODE Lead Free Released Non-Lead Free Released Assembly site code Per SCOP 200-002 ORDER INFORMATION 8-Lead PDIP IRS21091PbF 8-Lead SOIC IRS21091SPbF 8-Lead SOIC Tape & Reel IRS21091STRPbF The SOIC-8 is MSL2 qualified. This product has been designed and qualified for the industrial level. Qualification standards can be found at www.irf.com IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 Data and specifications subject to change without notice. 6/22/2007 www.irf.com 20