IRS21851STRPBF

Data Sheet No. PD60255 IRS21851SPbF • Gate drive supply range from 10 V to 20 V • Undervoltage lockout for VBS and V CC • 3.3 V and 5 V input logic compatible • Tolerant to negative transient voltage • Matched propagation delays for all channels • RoHS compliant Features SINGLE HIGH SIDE DRIVER IC Product Summary VOFFSET IO+/VOUT ton/off (typ.) 600 V max. 4A/ 4A 10 V - 20 V 170 ns & 170 ns Description The IRS21851 is a high voltage, high speed power MOSFET and IGBT single high-side driver with propagation delay matched output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The floating logic input is compatible with standard CMOS or LSTTL output, down to 3.3 V logic and can be operated up to 600 V above the ground. The output driver features a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high- side configuration, which operates up to 600 V. Package 8-Lead SOIC IRS21851 Typical Connection up to 600V VCC IN VCC IN COM VB HO VS TO LOAD (Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1 IRS21851SPbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VC C V IN VB VS VHO dVs /dt PD RthJA TJ TS TL Definition Low-side supply voltage Logic input voltage (HIN) High-side floating well supply voltage High-side floating well supply return voltage Floating gate drive output voltage Allowable VS offset supply transient relative to COM Package power dissipation @ TA ≤ +25 °C Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) Min. - 0.3 COM -0.3 - 0.3 V B - 20 VS - 0.3 — — — -55 -55 — Max. 20 (Note 1) VCC + 0.3 620 (Note 1) VB + 0.3 VB + 0.3 50 1.25 100 150 150 300 Units V V/ns W °C/W °C Note 1: All supplies are fully tested at 25 V. An internal 20 V clamp exists for each supply. Recommended Operating Conditions For proper operation, the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to COM. The offset rating are tested with supplies of (VCC-COM)=(VB-VS)=15 V. Symbol VC C V IN VB VS VHO TA HIN input voltage Definition Low-side supply voltage High-side floating well supply voltage High-side floating well supply offset voltage Floating gate drive output voltage Ambient temperature Min. 10 COM V S + 10 Note 2 VS -40 Max. 20 VC C VS + 20 600 VB 125 Units V °C Note 2: Logic operational for VS of -5 V to 600 V. Logic state held for VS of -5 V to -VBS. (Please refer to the Design Tip DT97-3 for more details). w ww.irf.com 2 IRS21851SPbF Dynamic Electrical Characteristics Symbol ton t off tr tf (VCC-COM)=(VB-VS)=15 V, TA = 25 oC. CL = 1000 pF unless otherwise specified. All parameters are referenced to COM. Definition Turn-on propagation delay Turn-off propagation delay Turn-on rise time Turn-off fall time Min. Typ. Max. Units Test Conditions — — — — 160 160 15 15 210 210 40 40 ns (VS -COM) = 0 V (VS -COM) = 600 V Static Electrical Characteristics (VCC-COM)=(VB-V S)=15 V. The VIN, VTH, and IIN parameters are referenced to COM. The VO and IO parameters are referenced respective VS and are applicale to the respective output leads HO. The VCC parameters are referenced to COM. The VBSUV parameters are referenced to VS. Symbol VCCUV+ VCCUVVBSUV+ VBSUVILK IQBS IQCC V IH V IL VOH, HO VOL, HO IIN+ IINIO+, HO IO-, HO Definition VCC s upply undervoltage positive going threshold VCC s upply undervoltage negative going threshold VBS s upply undervoltage positive going threshold VBS s upply undervoltage negative going threshold High-side floating well offset supply leakage current Quiescent VBS supply current Quiescent VCC s upply current Logic “1” input voltage Logic “0” input voltage HO high level output voltage, VBIAS - VO HO low level output voltage, VO Logic “1” input bias current Logic “0” input bias current Output high short circuit pulsed current HO Output low short circuit pulsed current HO Min. Typ. Max. Units Test Conditions 8.0 7.4 8.0 7.4 — — — 2.5 — — — — — — — 8.9 8.2 8.9 8.2 — 80 120 — — 20 10 10 0 4 4 9.8 9.0 9.8 9.0 50 150 240 — 0.8 60 30 20 5 — A — V mV µA IO = 2 mA VHIN = 5 V VHIN = 0 V VO = 0 V, VIN = 0 V PW ≤ 10 µs VO = 15 V, VIN = 15 V PW ≤ 10 µs µA VB = VS = 600 V HIN = 0 V or 5 V V w ww.irf.com 3 IRS21851SPbF Functional Block Diagram VCC 5V VREG VCCUV DETECT COM HIGHSIDE CHANNLE1 VB HIN PULSE GEN LEVEL SHIFT UP FILTER, LATCH UV DETECT DRIVER HO VS Lead Definitions Symbol VCC COM VB HO VS HIN Description Low-side supply voltage Ground High-side drive floating supply High-side driver outputs High voltage floating supply return Logic inputs for high-side gate driver output (in phase) Lead Assignments 1 2 3 4 COM VCC HIN VB HO VS 8 7 6 5 IRS21851S 8- Lead SOIC w ww.irf.com 4 IRS21851PbF 50% IN t on tr 50% t off tf OUT 90% 10% 90% 10% Figure 1. Switching Time Waveforms HIN HO Figure 2. Input/Output Timing Diagram w ww.irf.com 5 IRS21851SPbF T ur n- O n Propagation Delay (ns ) T ur n- O n Propagation Delay (ns ) 300 250 200 150 100 50 0 -50 -25 0 25 50 75 100 125 Max Typ 300 250 200 150 100 50 0 10 12 14 16 18 20 Supply Voltage (V) Figure 3B. Turn-On Propagation Delay vs. S upply Voltage Max Typ Temperature (°C) Figure 3A. Tu rn-On Propag ation Delay vs . Temperature T urn- Off Propagation Delay ( ns ) T ur n- O ff Propagation Delay (ns ) 300 250 200 150 100 50 0 -50 -25 0 25 50 75 100 125 Max Typ 250 200 Max Typ 150 100 50 0 10 12 14 16 18 20 Supply Voltage (V) Figure 4B. Turn-Off Propagation Delay vs. S upply Voltage Temperature (°C) Figure 4A. Tu rn-Off Propag ation Delay vs . Temperature w ww.irf.com 6 IRS21851SPbF 45 Tur n- O n Ris e Time ( ns ) 35 30 25 20 15 10 5 0 -50 -25 0 25 50 75 100 125 Typ Tur n- O n Ris e Time ( ns ) 40 Max 60 50 40 30 20 10 0 10 12 14 16 18 20 Temperature (°C) Figure 5A. Turn-On Rise Time vs. Temperature Supply Voltage (V) Figure 5B. Turn-On Rise Time vs. Supply V oltage Typ Max 45 T ur n- O ff F all T ime ( ns ) 35 30 25 20 15 10 5 0 -50 -25 0 25 50 75 100 125 Typ T urn- Off Fall Time ( ns) 40 Max 60 50 40 30 20 10 0 10 12 14 16 18 20 Temperature (°C) Figure 6A. Turn-Off Fall Time vs. Temperature Supply Voltage (V) Figure 6B. Turn-Off Fall Tim e vs. Supply V oltage Typ Max w ww.irf.com 7 IRS21851SPbF 3 Logic "1" Input Voltag e ( V) 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 Max Logic "1" Input Voltag e (V) 3 2.5 2 1.5 1 0.5 0 10 12 14 16 18 20 Temperature (°C) Figure 7A. L ogic "1" Input Voltage vs. Temperature Supply Voltage (V) Figure 7B. Logic "1" Input Voltage vs. Supply Voltage Max 0.9 Logic "0" Input Voltag e ( V) Logic "0" Input Voltag e (V) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -25 0 25 50 75 100 125 Min 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 10 12 14 16 18 20 Temperature (°C) Figure 8A. L ogic "0" Input Voltage vs. Temperature Supply Voltage (V) Figure 8B. Logic "0" Input Voltage vs. Supply V oltage Min w ww.irf.com 8 IRS21851SPbF 90 High Lev el Output ( m V) 70 60 50 40 30 20 10 0 -50 Typ Max High Lev el O utput (m V) 80 70 60 50 40 30 20 10 0 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (°C) Figure 9A. High Level Output vs. Temperature (Io = 2 mA) Supply Voltage (V) Figure 9B. High Level Outpu t vs. Supply Voltage (Io =2 mA) Typ Max 40 Low L ev el O utput ( m V) 30 25 20 15 10 5 0 -50 -25 0 25 50 75 100 125 Typ Low L ev el O utput ( m V) 35 Max 35 30 25 20 15 10 5 0 10 12 14 16 18 20 Temperature (°C) Figure 10A. Low Level Output vs. Temperature (Io=2 m A) Supply Voltage (V) Figure 10B. Low Level Output vs. Supply Vo ltage (Io=2 m A) Typ Max w ww.irf.com 9 IRS21851SPbF O ffs e t Supply Leak a ge Cur rent ( µA) 250 200 150 100 50 0 -50 Max -25 0 25 50 75 100 125 O ffs e t Supply Leak a ge Cur rent ( µA) 300 60 50 40 30 20 10 0 10 12 14 16 18 20 Supply Voltage (V) Max Temperature (°C) Figure 11A. Offset Su pply Leakage Current vs. Temperature Figure 11B. Offse t Supply Leak age Current vs. S upply Voltage 180 V B S Supp ly Cur r ent ( µA ) V B S Supp ly Curr ent ( µA ) 160 140 120 100 80 60 40 20 0 -50 -25 0 25 50 75 100 125 Typ Max 250 200 150 100 50 0 10 12 14 16 18 20 Temperature (°C) Figure 12A. VBS Supply Current vs. Temperature Supply Voltage (V) Figure 12B. V BS Supply Curre nt vs. Supply Voltage Max Typ w ww.irf.com 10 IRS21851SPbF 300 V CC Supp ly Cur r ent ( µA ) 250 200 150 100 50 0 -50 -25 0 25 50 75 100 125 Typ Max V CC Supp ly Curr ent ( µA ) 350 300 250 200 150 100 50 0 10 12 14 16 18 20 Temperature (°C) Figure 13A. VCC Supply Current vs. Temperature Supply Voltage (V) Figure 13B. V CC Supply Curre nt vs. Supply Voltage Max Typ Logic "0" Input Bias C urr ent ( µA) 5 4 3 2 1 0 -50 Max Logic "0" Input Bias C ur r ent ( µA) 6 6 5 4 3 2 1 0 10 12 14 16 18 20 Supply Voltage (V) Figure 14B. Log ic "0" Input Bias Current vs. S upply Voltage Max -25 0 25 50 75 100 125 Temperature (°C) Figure 14A. Lo gic "0" Input Bias Current vs . Temperature w ww.irf.com 11 IRS21851SPbF Lo gic "0" Input Bia s Curr ent ( µA) 5 4 3 2 1 0 -50 Max Logic "0" Input Bias C urrent (µA) 6 6 5 4 3 2 1 0 10 12 14 16 18 20 Supply Voltage (V) Max -25 0 25 50 75 100 125 Temperature (°C) Figure 15A. Logic "0" Input Bias Current vs. Temperature Figure 15B. Logic "0" Input Bias Current vs. Voltage 12 V CC UVL O Thres hold ( +) ( V) 11 10 9 8 7 6 -50 -25 0 25 50 75 100 125 Max Typ Min VCC UVL O T hr es hold ( - ) ( V) 12 11 10 9 8 7 6 -50 Max Typ Min -25 0 25 50 75 100 125 Temperature (°C) Figure 16. V CC Undervoltage Threshold (+) v s. Temperature Temperature (°C) Figure 17. V CC Undervoltage Threshold (-) v s. Temperature w ww.irf.com 12 IRS21851SPbF 12 V B S UVL O Thres hold ( +) ( V) VB S UVL O T hr es hold ( - ) ( V) 11 10 9 8 7 6 -50 -25 0 25 50 75 100 125 Max Typ Min 12 11 10 9 8 7 6 -50 Max Typ Min -25 0 25 50 75 100 125 Temperature (°C) Figure 18. V BS Undervoltage Threshold (+) v s. Temperature Temperature (°C) Figure 19. V BS Undervoltage Threshold (-) v s. Temperature Outp ut Sourc e Cur r e nt ( A) O utp ut Sour c e Cur r e nt ( A) 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -50 Typ 6 5 4 3 2 1 0 10 12 14 16 18 20 Typ -25 0 25 50 75 100 125 Temperature (°C) Figure 20A. Output Source Current vs. Temperature Supply Voltage (V) Figure 20B. Outp ut Source Cur rent vs. Supply V oltage w ww.irf.com 13 IRS21851SPbF O utp ut Sink Curr ent ( A) 3.5 3 2.5 2 1.5 1 0.5 0 -50 O utp ut Sink Cur r ent ( A) 5 4.5 4 Typ 6 5 4 3 2 1 0 10 12 14 16 18 20 Typ -25 0 25 50 75 100 125 Temperature (°C) Figure 21A. Output Sink Current vs. Temperature Supply Voltage (V) Figure 21B. Out put Sink Curre nt vs. Supply Voltage Case outline D A 8 7 6 5 B FOOTPRINT 8X 0.72 [.028] DIM A b c D INCHES MIN .0532 .013 .0075 .189 .1497 MAX .0688 .0098 .020 .0098 .1968 .1574 MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 A1 .0040 6 E 5 H 0.25 [.010] A E 6.46 [.255] e e1 H K L y 1 2 3 4 .050 BASIC .025 BASIC .2284 .0099 .016 0° .2440 .0196 .050 8° 1.27 BASIC 0.635 BASIC 5.80 0.25 0.40 0° 6.20 0.50 1.27 8° 6X e e1 3X 1.27 [.050] 8X 1.78 [.070] A K x 45° C 0.10 [.004] y 8X c 8X b 0.25 [.010] NOTES: A1 CAB 8X L 7 4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA. 1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. 2. CONTROLLING DIMENSION: MILLIMETER 3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. 4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA. 5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006]. 6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010]. 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE. 8-Lead SOIC w ww.irf.com 01-6027 14 IRS21851SPbF Tape & Reel 8-lead SOIC LOAD ED TA PE FEED DIRECTION B A H D F C N OT E : CO NTROLLING D IM ENSION IN M M E G C A R R I E R T A P E D IM E N S I O N F O R 8 S O I C N M e tr ic Im p e r ia l Co d e M in M ax M in M ax A 7 .9 0 8 .1 0 0. 31 1 0 .3 1 8 B 3 .9 0 4 .1 0 0. 15 3 0 .1 6 1 C 1 1 .7 0 1 2 . 30 0 .4 6 0 .4 8 4 D 5 .4 5 5 .5 5 0. 21 4 0 .2 1 8 E 6 .3 0 6 .5 0 0. 24 8 0 .2 5 5 F 5 .1 0 5 .3 0 0. 20 0 0 .2 0 8 G 1 .5 0 n/ a 0. 05 9 n/ a H 1 .5 0 1 .6 0 0. 05 9 0 .0 6 2 F D C E B A G H R E E L D IM E N S I O N S F O R 8 S O IC N M e tr ic Im p e r ia l Co d e M in M ax M in M ax A 32 9.60 3 3 0 .2 5 1 2 .9 76 1 3 .0 0 1 B 2 0 .9 5 2 1 . 45 0. 82 4 0 .8 4 4 C 1 2 .8 0 1 3 . 20 0. 50 3 0 .5 1 9 D 1 .9 5 2 .4 5 0. 76 7 0 .0 9 6 E 9 8 .0 0 1 0 2 .0 0 3. 85 8 4 .0 1 5 F n /a 1 8 . 40 n /a 0 .7 2 4 G 1 4 .5 0 1 7 . 10 0. 57 0 0 .6 7 3 H 1 2 .4 0 1 4 . 40 0. 48 8 0 .5 6 6 w ww.irf.com 15 IRS21851SPbF LEADFREE PART MARKING INFORMATION Part number IRxxxxxx S YWW? ?XXXX Lot Code (Prod mode - 4 digit SPN code) IR logo Date code Pin 1 Identifier ? P MARKING CODE Lead Free Released Non-Lead Free Released Assembly site code Per SCOP 200-002 ORDER INFORMATION 8-Lead SOIC order IRS21851SPbF 8-Lead SOIC Tape & Reel IRS21851STRPbF The SOIC-8 is MSL2 qualified. This product has been designed and qualified for the industrial level. Qualification standards can be found at www.irf.com IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 Data and specifications subject to change without notice. 12/4/2006 w ww.irf.com 16