IRS2336DPBF

October 16, 2009 IRS2336(D) IRS23364D HIGH VOLTAGE 3 PHASE GATE DRIVER IC Features • • • • • • • • • • • • • • • • • • • Drives up to six IGBT/MOSFET power devices Gate drive supplies up to 20 V per channel Integrated bootstrap functionality (IRS2336(4)D) Over-current protection Over-temperature shutdown input Advanced input filter Integrated deadtime protection Shoot-through (cross-conduction) protection Undervoltage lockout for VCC & VBS Enable/disable input and fault reporting Adjustable fault clear timing Separate logic and power grounds 3.3 V input logic compatible Tolerant to negative transient voltage Designed for use with bootstrap power supplies Matched propagation delays for all channels -40° to 125° operating range C C RoHS compliant Lead-Free Product Summary Topology VOFFSET IRS2336(D) VOUT IRS23364D 3 Phase ≤ 600 V 10 V – 20 V 11.5 V – 20 V 200 mA & 350 mA 530 ns & 530 ns 275 ns Io+ & I o- (typical) tON & tOFF (typical) Deadtime (typical) Package Options 28-Lead PDIP 28-Lead SOIC Wide Body Typical Applications • • • • Appliance motor drives Servo drives Micro inverter drives General purpose three phase inverters 48-Lead MLPQ7X7 (without 14 leads) 44-Lead PLCC (without 12 leads) Typical Connection Diagram www.irf.com © 2009 International Rectifier IRS2336x(D) Family Table of Contents Description Feature Comparison Simplified Block Diagram Typical Application Diagram Qualification Information Absolute Maximum Ratings Recommended Operating Conditions Static Electrical Characteristics Dynamic Electrical Characteristics Functional Block Diagram Input/Output Pin Equivalent Circuit Diagram Lead Definitions Lead Assignments Application Information and Additional Details Parameter Temperature Trends Package Details Tape and Reel Details Part Marking Information Ordering Information Page 3 3 4 4 5 6 7 8-9 10 11-12 13-14 15-16 17 18-34 35-38 39-42 43-45 46 47 www.irf.com © 2009 International Rectifier 2 IRS2336x(D) Family Description The IRS2336xD are high voltage, high speed, power MOSFET and IGBT gate drivers with three high-side and three low-side referenced output channels for 3-phase applications. This IC is designed to be used with low-cost bootstrap power supplies; the bootstrap diode functionality has been integrated into this device to reduce the component count and the PCB size. Proprietary HVIC and latch immune CMOS technologies have been implemented in a rugged monolithic structure. The floating logic input is compatible with standard CMOS or LSTTL outputs (down to 3.3 V logic). A current trip function which terminates all six outputs can be derived from an external current sense resistor. Enable functionality is available to terminate all six outputs simultaneously. An open-drain FAULT signal is provided to indicate that a fault (e.g., over-current, over-temperature, or undervoltage shutdown event) has occurred. Fault conditions are cleared automatically after a delay programmed externally via an RC network connected to the RCIN input. The output drivers feature a high-pulse current buffer stage designed for minimum driver cross-conduction. Shoot-through protection circuitry and a minimum deadtime circuitry have been integrated into this IC. Propagation delays are matched to simplify the HVIC’s use in high frequency applications. The floating channels can be used to drive N-channel power MOSFETs or IGBTs in the high-side configuration, which operate up to 600 V. Feature Comparison: IRS2336xD Family Part Number IRS2336(D) IRS23364D Input Logic HIN/N, LIN/N HIN, LIN UVLO 8.9 V/ 8.2 V 11.1 V/ 10.9 V VIT,TH 0.46 V 0.46 V tON, tOFF 530 ns, 530 ns 530 ns, 530 ns VOUT 10 V – 20 V 11.5 V – 20 V www.irf.com © 2009 International Rectifier 3 IRS2336x(D) Family Simplified Block Diagram Typical Application Diagram + DC Bus ≤ 600 V Input Voltage To Load - IRS2336xD VCC Control Inputs, EN, & FAULT www.irf.com © 2009 International Rectifier 4 IRS2336x(D) Family Qualification Information Qualification Level † Industrial †† Comments: This family of ICs has passed JEDEC’s Industrial qualification. IR’s Consumer qualification level is granted by extension of the higher Industrial level. ††† SOIC28W MSL3 , 260°C (per IPC/JEDEC J-STD-020) MLPQ7X7 PLCC44 PDIP28 MSL3 , 245°C (per IPC/JEDEC J-STD-020) ††† Moisture Sensitivity Level Human Body Model ESD Machine Model Charged Device Model IC Latch-Up Test RoHS Compliant † †† †††† Not applicable (non-surface mount package style) Class 2 (per JEDEC standard JESD22-A114) Class B (per EIA/JEDEC standard EIA/JESD22-A115) Class IV (per JEDEC standard JESD22-C101) Class I, Level A (per JESD78) Yes Qualification standards can be found at International Rectifier’s web site http://www.irf.com/ Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. ††† Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information. †††† Charged Device Model classification is based on SOIC28W package. www.irf.com © 2009 International Rectifier 5 IRS2336x(D) Family Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to VSS unless otherwise stated in the table. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Voltage clamps are included between VCC & COM (25 V), VCC & VSS (20 V), and VB & VS (20 V). Symbol VCC VIN VRCIN VB VS VHO VLO VFLT COM dVS/dt PW HIN Definition Low side supply voltage Logic input voltage (HIN, LIN, ITRIP, EN) IRS2336(D) IRS23364D Min -0.3 VSS-0.3 VSS-0.3 VSS-0.3 -0.3 † VB-20 VS-0.3 COM-0.3 VSS-0.3 VCC-25 — 500 — — — — — — — — — -55 — Max † 20 VSS+5.2 VCC+0.3 VCC+0.3 † 620 VB+0.3 VB+0.3 VCC+0.3 VCC+0.3 VCC+0.3 50 — 1.5 1.6 2.0 2.0 83 78 63 63 150 150 300 ºC ºC/W W Units PD RthJA TJ TS TL † RCIN input voltage High-side floating well supply voltage High-side floating well supply return voltage Floating gate drive output voltage Low-side output voltage Fault output voltage Power ground Allowable VS offset supply transient relative to VSS High-side input pulse width 28-Lead PDIP 28-Lead SOICW Package power dissipation @ TA ≤+25ºC 44-Lead PLCC 48-Lead MLPQ7X7 28-Lead PDIP 28-Lead SOICW Thermal resistance, junction to ambient 44-Lead PLCC 48-Lead MLPQ7X7 Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) V V/ns ns All supplies are tested at 25 V. An internal 20 V clamp exists for each supply. www.irf.com © 2009 International Rectifier 6 IRS2336x(D) Family Recommended Operating Conditions For proper operation, the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to VSS unless otherwise stated in the table. The offset rating is tested with supplies of (VCC-COM) = (VB-VS) = 15 V. Symbol VCC VIN VB VS VS(t) VHO VLO COM VFLT VRCIN VITRIP TA † †† Definition Low-side supply voltage HIN, LIN, & EN input voltage High-side floating well supply voltage High-side floating well supply offset voltage †† Transient high-side floating supply voltage Floating gate drive output voltage Low-side output voltage Power ground FAULT output voltage RCIN input voltage ITRIP input voltage Ambient temperature † IRS2336(D) IRS23364D IRS2336(D) IRS23364D IRS2336(D) IRS23364D Min 10 11.5 VSS VS+10 VS+11.5 COM-8 -50 Vs COM -5 VSS VSS VSS -40 Max 20 20 VSS+5 VCC VS+20 VS+20 600 600 VB VCC 5 VCC VCC VSS+5 125 Units V ºC Logic operation for VS of –8 V to 600 V. Logic state held for VS of –8 V to –VBS. Please refer to Design Tip DT97-3 for more details. Operational for transient negative VS of VSS - 50 V with a 50 ns pulse width. Guaranteed by design. Refer to the Application Information section of this datasheet for more details. www.irf.com © 2009 International Rectifier 7 IRS2336x(D) Family Static Electrical Characteristics (VCC-COM) = (VB-VS) = 15 V. TA = 25 C unless otherwise specified. The VIN and IIN parameters are referenced to VSS and are applicable to all six channels. The VO and IO parameters are referenced to respective VS and COM and are applicable to the respective output leads HO or LO. The VCCUV parameters are referenced to VSS. The VBSUV parameters are referenced to VS. Symbol VCCUV+ VCCUVVCCUVHY VBSUV+ VBSUVVBSUVHY ILK IQBS IQCC VOH VOL Io+ IoVIH VIL VIN,CLAMP IHIN+ IHINILIN+ ILINVRCIN,TH VRCIN,HY IRCIN RON,RCIN Definition VCC supply undervoltage positive IRS2336(D) IRS23364D going threshold VCC supply undervoltage negative IRS2336(D) IRS23364D going threshold IRS2336(D) VCC supply undervoltage hysteresis IRS23364D VBS supply undervoltage positive IRS2336(D) IRS23364D going threshold VBS supply undervoltage negative IRS2336(D) IRS23364D going threshold IRS2336(D) VBS supply undervoltage hysteresis IRS23364D High-side floating well offset supply leakage Quiescent VBS supply current IRS2336 Quiescent VCC supply current IR2336(4)D High level output voltage drop, VBIAS-VO Low level output voltage drop, VO Output high short circuit pulsed current Output low short circuit pulsed current Logic “0” input voltage Logic “1” input voltage Logic “1” input voltage Logic “0” input voltage Input voltage clamp (HIN, LIN, ITRIP and EN) Input bias current (HO = High) Input bias current (HO = Low) Input bias current (LO = High) Input bias current (LO = Low) RCIN positive going threshold RCIN hysteresis RCIN input bias current RCIN low on resistance Min 8 10.4 7.4 10.2 0.3 — 8 10.4 7.4 10.2 0.3 — — — — — — — 120 250 2.5 — IRS2336(D) IRS2336(D) IRS23364D IRS2336(D) IRS23364D IRS2336(D) IRS23364D IRS2336(D) IRS23364D 4.8 — — — — — — — — — — — — Typ 8.9 11.1 8.2 10.9 0.7 0.2 8.9 11.1 8.2 10.9 0.7 0.2 — 70 2 3 0.90 0.40 200 350 — — 5.2 150 120 110 — 150 120 110 — 8 3 — 50 Max 9.8 11.6 9 11.4 — — 9.8 11.6 9 11.4 — — 50 120 3 4 1.4 0.6 — mA — — NA 0.8 5.65 200 165 150 1 200 165 150 1 — — 1 100 V IIN = 100 µA VIN = 0 V VIN = 4 V µA VIN = 0 V VIN = 4 V VIN = 0 V V µA NA VRCIN = 0 V or 15 V I = 1.5 mA Units Test Conditions o V NA µA mA V V VB = VS = 600 V All inputs are in the off state IO= 20 mA VO=0 V,VIN=0 V, PW ≤ 10 µs VO=15 V,VIN=5 V, PW ≤ 10 µs www.irf.com © 2009 International Rectifier 8 IRS2336x(D) Family Static Electrical Characteristics (continued) Symbol VIT,TH+ VIT,THVIT,HYS IITRIP+ IITRIPVEN,TH+ VEN,THIEN+ IENRON,FLT RBS Definition ITRIP positive going threshold ITRIP negative going threshold ITRIP hysteresis “High” ITRIP input bias current “Low” ITRIP input bias current Enable positive going threshold Enable negative going threshold “High” enable input bias current “Low” enable input bias current FAULT low on resistance Internal BS diode Ron (IRS2336(4)D) IRS2336(D) IRS23364D IRS2336(D) IRS23364D Min 0.37 — — — — — — 0.8 — — — — — Typ 0.46 0.4 0.07 5 5 — — — 5 120 — 50 200 Max 0.55 — — 20 40 1 2.5 — 20 165 1 100 — VIN = 4 V VIN = 0 V V NA VIN = 4 V VIN = 0 V I = 1.5 mA NA Units V Test Conditions NA µA µA www.irf.com © 2009 International Rectifier 9 IRS2336x(D) Family Dynamic Electrical Characteristics VCC= VB = 15 V, VS = VSS = COM, TA = 25 C, and CL = 1000 pF unless otherwise specified. Symbol tON tOFF tR tF tFIL,IN tEN tFILTER,EN tFLTCLR tITRIP tBL tFLT DT MDT MT PM † Definition Turn-on propagation delay Turn-off propagation delay Turn-on rise time Turn-off fall time † Input filter time (HIN, LIN, ITRIP) Enable low to output shutdown propagation delay Enable input filter time FAULT clear time RCIN: R = 2 M , C = 1 nF ITRIP to output shutdown propagation delay ITRIP blanking time ITRIP to FAULT propagation delay Deadtime †† DT matching Delay matching time (tON, tOFF) Pulse width distortion ††† †† o Min 400 400 — — 200 350 100 1.3 500 — 400 190 — — — Typ 530 530 125 50 350 460 200 1.65 750 400 600 275 — — — Max 750 750 190 75 510 650 — 2 1200 — 950 420 60 50 75 Units Test Conditions VIN = 0 V & 5 V ns VIN, VEN = 0 V or 5 V NA VIN = 0 V or 5 V VITRIP = 0 V VITRIP = 5 V VIN = 0 V or 5 V VITRIP = 5 V VIN = 0 V & 5 V without external deadtime VIN = 0 V & 5 V with external deadtime larger than DT PW input=10 µs ms ns The minimum width of the input pulse is recommended to exceed 500 ns to ensure the filtering time of the input filter is exceeded. †† This parameter applies to all of the channels. Please see the application section for more details. ††† PM is defined as PW IN - PW OUT. www.irf.com © 2009 International Rectifier 10 IRS2336x(D) Family Functional Block Diagram: IRS2336(D) Note: IRS2336 is without the “Integrated BootFET” www.irf.com © 2009 International Rectifier 11 IRS2336x(D) Family Functional Block Diagram: IRS23364D www.irf.com © 2009 International Rectifier 12 IRS2336x(D) Family Input/Output Pin Equivalent Circuit Diagrams: IRS2336(D) www.irf.com © 2009 International Rectifier 13 IRS2336x(D) Family Input/Output Pin Equivalent Circuit Diagrams: IRS23364D www.irf.com © 2009 International Rectifier 14 IRS2336x(D) Family Lead Definitions: IRS2336(D) Symbol VCC VSS VB1 VB2 VB3 VS1 VS2 VS3 HIN1/N HIN2/N HIN3/N LIN1/N LIN2/N LIN3/N HO1 HO2 HO3 LO1 LO2 LO3 COM FAULT/N EN ITRIP Description Low-side supply voltage Logic ground High-side gate drive floating supply (phase 1) High-side gate drive floating supply (phase 2) High-side gate drive floating supply (phase 3) High voltage floating supply return (phase 1) High voltage floating supply return (phase 2) High voltage floating supply return (phase 3) Logic inputs for high-side gate driver outputs (phase 1); input is out-of-phase with output Logic inputs for high-side gate driver outputs (phase 2); input is out-of-phase with output Logic inputs for high-side gate driver outputs (phase 3); input is out-of-phase with output Logic inputs for low-side gate driver outputs (phase 1); input is out-of-phase with output Logic inputs for low-side gate driver outputs (phase 2); input is out-of-phase with output Logic inputs for low-side gate driver outputs (phase 3); input is out-of-phase with output High-side driver outputs (phase 1) High-side driver outputs (phase 2) High-side driver outputs (phase 3) Low-side driver outputs (phase 1) Low-side driver outputs (phase 2) Low-side driver outputs (phase 3) Low-side gate drive return Indicates over-current, over-temperature (ITRIP), or low-side undervoltage lockout has occurred. This pin has negative logic and an open-drain output. The use of over-current and overtemperature protection requires the use of external components. Logic input to shutdown functionality. Logic functions when EN is high (i.e., positive logic). No effect on FAULT and not latched. Analog input for over-current shutdown. When active, ITRIP shuts down outputs and activates FAULT and RCIN low. When ITRIP becomes inactive, FAULT stays active low for an externally set time tFLTCLR, then automatically becomes inactive (open-drain high impedance). An external RC network input used to define the FAULT CLEAR delay (tFLTCLR) approximately equal to R*C. When RCIN > 8 V, the FAULT pin goes back into an open-drain high-impedance state. RCIN www.irf.com © 2009 International Rectifier 15 IRS2336x(D) Family Lead Definitions: IRS23364D Symbol VCC VSS VB1 VB2 VB3 VS1 VS2 VS3 HIN1 HIN2 HIN3 LIN1 LIN2 LIN3 HO1 HO2 HO3 LO1 LO2 LO3 COM FAULT/N EN ITRIP Description Low-side supply voltage Logic ground High-side gate drive floating supply (phase 1) High-side gate drive floating supply (phase 2) High-side gate drive floating supply (phase 3) High voltage floating supply return (phase 1) High voltage floating supply return (phase 2) High voltage floating supply return (phase 3) Logic inputs for high-side gate driver outputs (phase 1); input is in-phase with output Logic inputs for high-side gate driver outputs (phase 2); input is in-phase with output Logic inputs for high-side gate driver outputs (phase 3); input is in-phase with output Logic inputs for low-side gate driver outputs (phase 1); input is in-phase with output Logic inputs for low-side gate driver outputs (phase 2); input is in-phase with output Logic inputs for low-side gate driver outputs (phase 3); input is in-phase with output High-side driver outputs (phase 1) High-side driver outputs (phase 2) High-side driver outputs (phase 3) Low-side driver outputs (phase 1) Low-side driver outputs (phase 2) Low-side driver outputs (phase 3) Low-side gate drive return Indicates over-current, over-temperature (ITRIP), or low-side undervoltage lockout has occurred. This pin has negative logic and an open-drain output. The use of over-current and overtemperature protection requires the use of external components. Logic input to shutdown functionality. Logic functions when EN is high (i.e., positive logic). No effect on FAULT and not latched. Analog input for over-current shutdown. When active, ITRIP shuts down outputs and activates FAULT and RCIN low. When ITRIP becomes inactive, FAULT stays active low for an externally set time tFLTCLR, then automatically becomes inactive (open-drain high impedance). An external RC network input used to define the FAULT CLEAR delay (tFLTCLR) approximately equal to R*C. When RCIN > 8 V, the FAULT pin goes back into an open-drain high-impedance state. RCIN www.irf.com © 2009 International Rectifier 16 IRS2336x(D) Family Lead Assignments IRS2336(D) HO2 HO3 30 VB3 VB2 VS2 31 34 33 VS1 HO1 VB1 1 2 3 32 29 VS3 28 27 26 25 n.c. n.c. n.c. LO1 LO2 LO3 COM n.c. VSS n.c. VCC HIN1 HIN2 HIN3 n.c. 4 5 6 7 8 34 Lead MLPQ 24 23 22 21 20 19 14 15 16 17 RCIN 10 11 12 13 ITRIP n.c. EN n.c. www.irf.com FAULT LIN2 LIN1 LIN3 n.c. 18 9 © 2009 International Rectifier 17 IRS2336x(D) Family Application Information and Additional Details Information regarding the following topics are included as subsections within this section of the datasheet. • • • • • • • • • • • • • • • • • • • • IGBT/MOSFET Gate Drive Switching and Timing Relationships Deadtime Matched Propagation Delays Input Logic Compatibility Undervoltage Lockout Protection Shoot-Through Protection Enable Input Fault Reporting and Programmable Fault Clear Timer Over-Current Protection Over-Temperature Shutdown Protection Truth Table: Undervoltage lockout, ITRIP, and ENABLE Advanced Input Filter Short-Pulse / Noise Rejection Integrated Bootstrap Functionality Bootstrap Power Supply Design Separate Logic and Power Grounds Tolerant to Negative VS Transients PCB Layout Tips Additional Documentation IGBT/MOSFET Gate Drive The IRS2336xD HVICs are designed to drive up to six MOSFET or IGBT power devices. Figures 1 and 2 illustrate several parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to drive the gate of the power switch, is defined as IO. The voltage that drives the gate of the external power switch is defined as VHO for the high-side power switch and VLO for the low-side power switch; this parameter is sometimes generically called VOUT and in this case does not differentiate between the high-side or low-side output voltage. VB (or VCC) VB (or VCC) IO+ HO (or LO) + HO (or LO) VHO (or VLO) VS (or COM) VS (or COM) IO- Figure 1: HVIC sourcing current Figure 2: HVIC sinking current www.irf.com © 2009 International Rectifier 18 IRS2336x(D) Family Switching and Timing Relationships The relationship between the input and output signals of the IRS2336(D) and IRS23364D are illustrated below in Figures 3 and 4. From these figures, we can see the definitions of several timing parameters (i.e., PW IN, PW OUT, tON, tOFF, tR, and tF) associated with this device. LINx (or HINx) 50% 50% LINx (or HINx) 50% 50% PWIN PWIN tON tR 90% 10% tOFF PWOUT 90% tF tON tR 90% 10% tOFF PWOUT 90% tF LOx (or HOx) 10% LOx (or HOx) 10% Figure 3: Switching time waveforms (IRS2336(D)) Figure 4: Switching time waveforms (IRS23364D) The following two figures illustrate the timing relationships of some of the functionality of the IRS2336xD; this functionality is described in further detail later in this document. During interval A of Figure 5, the HVIC has received the command to turn-on both the high- and low-side switches at the same time; as a result, the shoot-through protection of the HVIC has prevented this condition and both the highand low-side output are held in the off state. Interval B of Figures 5 and 6 shows that the signal on the ITRIP input pin has gone from a low to a high state; as a result, all of the gate drive outputs have been disabled (i.e., see that HOx has returned to the low state; LOx is also held low), the voltage on the RCIN pin has been pulled to 0 V, and a fault is reported by the FAULT output transitioning to the low state. Once the ITRIP input has returned to the low state, the output will remain disabled and the fault condition reported until the voltage on the RCIN pin charges up to VRCIN,TH (see interval C in Figure 6); the charging characteristics are dictated by the RC network attached to the RCIN pin. During intervals D and E of Figure 5, we can see that the enable (EN) pin has been pulled low (as is the case when the driver IC has received a command from the control IC to shutdown); this results in the outputs (HOx and LOx) being held in the low state until the enable pin is pulled high. www.irf.com © 2009 International Rectifier 19 IRS2336x(D) Family Figure 5: Input/output timing diagram for the IRS2336xD family Interval B Interval C VIT,TH+ ITRIP VIT,TH- FAULT tFLT 50% 50% RCIN VRCIN,TH HOx tITRIP 90% tFLTCLR Figure 6: Detailed view of B & C intervals Deadtime This family of HVICs features integrated deadtime protection circuitry. The deadtime for these ICs is fixed; other ICs within IR’s HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts a time period (a minimum deadtime) in which both the high- and low-side power switches are held off; this is done to ensure that the power switch being turned off has fully turned off before the second power switch is turned on. This minimum deadtime is automatically inserted whenever the external deadtime is shorter than DT; external deadtimes larger than DT are not modified by the gate driver. Figure 7 illustrates the deadtime period and the relationship between the output gate signals. The deadtime circuitry of the IRS2336xD is matched with respect to the high- and low-side outputs of a given channel; additionally, the deadtimes of each of the three channels are matched. Figure 7 defines the two deadtime parameters (i.e., DT1 and DT2) of a specific channel; the deadtime matching parameter (MDT) associated with the IRS2336xD specifies the maximum difference between DT1 and DT2. The MDT parameter also applies when comparing the DT of one channel of the IRS2336xD to that of another. www.irf.com © 2009 International Rectifier 20 IRS2336x(D) Family Figure 7: Illustration of deadtime Matched Propagation Delays The IRS2336xD family of HVICs is designed with propagation delay matching circuitry. With this feature, the IC’s response at the output to a signal at the input requires approximately the same time duration (i.e., tON, tOFF) for both the low-side channels and the high-side channels; the maximum difference is specified by the delay matching parameter (MT). Additionally, the propagation delay for each low-side channel is matched when compared to the other low-side channels and the propagation delays of the high-side channels are matched with each other; the MT specification applies as well. The propagation turn-on delay (tON) of the IRS2336xD is matched to the propagation turn-on delay (tOFF). Input Logic Compatibility The inputs of this IC are compatible with standard CMOS and TTL outputs. The IRS2336xD family has been designed to be compatible with 3.3 V and 5 V logic-level signals. The IRS2336(D) features an integrated 5.2 V Zener clamp on the HIN, LIN, ITRIP, and EN pins; the IRS23364D does not offer this input clamp. Figure 8 illustrates an input signal to the IRS2336(D) and IRS23364D, its input threshold values, and the logic state of the IC as a result of the input signal. Figure 8: HIN & LIN input thresholds www.irf.com © 2009 International Rectifier 21 IRS2336x(D) Family Undervoltage Lockout Protection This family of ICs provides undervoltage lockout protection on both the VCC (logic and low-side circuitry) power supply and the VBS (high-side circuitry) power supply. Figure 9 is used to illustrate this concept; VCC (or VBS) is plotted over time and as the waveform crosses the UVLO threshold (VCCUV+/- or VBSUV+/-) the undervoltage protection is enabled or disabled. Upon power-up, should the VCC voltage fail to reach the VCCUV+ threshold, the IC will not turn-on. Additionally, if the VCC voltage decreases below the VCCUV- threshold during operation, the undervoltage lockout circuitry will recognize a fault condition and shutdown the high- and low-side gate drive outputs, and the FAULT pin will transition to the low state to inform the controller of the fault condition. Upon power-up, should the VBS voltage fail to reach the VBSUV threshold, the IC will not turn-on. Additionally, if the VBS voltage decreases below the VBSUV threshold during operation, the undervoltage lockout circuitry will recognize a fault condition, and shutdown the high-side gate drive outputs of the IC. The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is sufficient to fully enhance the power devices. Without this feature, the gates of the external power switch could be driven with a low voltage, resulting in the power switch conducting current while the channel impedance is high; this could result in very high conduction losses within the power device and could lead to power device failure. Figure 9: UVLO protection Shoot-Through Protection The IRS2336xD family of high-voltage ICs is equipped with shoot-through protection circuitry (also known as crossconduction prevention circuitry). Figure 10 shows how this protection circuitry prevents both the high- and low-side switches from conducting at the same time. Table 1 illustrates the input/output relationship of the devices in the form of a truth table. Note that the IRS2336(D) has inverting inputs (the output is out-of-phase with its respective input) while the IRS23364D has non-inverting inputs (the output is in-phase with its respective input). www.irf.com © 2009 International Rectifier 22 IRS2336x(D) Family Figure 10: Illustration of shoot-through protection circuitry IRS2336(D) HIN 0 0 1 1 LIN 0 1 0 1 HO 0 1 0 0 LO 0 0 1 0 HIN 0 0 1 1 IRS23364D LIN 0 1 0 1 HO 0 0 1 0 LO 0 1 0 0 Table 1: Input/output truth table for IRS2336D and IRS23364D Enable Input The IRS2336xD family of HVICs is equipped with an enable input pin that is used to shutdown or enable the HVIC. When the EN pin is in the high state the HVIC is able to operate normally (assuming no other fault conditions). When a condition occurs that should shutdown the HVIC, the EN pin should see a low logic state. The enable circuitry of the IRS2336xD features an input filter; the minimum input duration is specified by tFILTER,EN. Please refer to the EN pin parameters VEN,TH+, VEN,TH-, and IEN for the details of its use. Table 2 gives a summary of this pin’s functionality and Figure 11 illustrates the outputs’ response to a shutdown command. EN VEN,TH- Enable Input tEN Enable input high Enable input low Outputs enabled * Outputs disabled HOx (or LOx) 90% Table 2: Enable functionality truth table (*assumes no other fault condition) Figure 11: Output enable timing waveform www.irf.com © 2009 International Rectifier 23 IRS2336x(D) Family Fault Reporting and Programmable Fault Clear Timer The IRS2336xD family provides an integrated fault reporting output and an adjustable fault clear timer. There are two situations that would cause the HVIC to report a fault via the FAULT pin. The first is an undervoltage condition of VCC and the second is if the ITRIP pin recognizes a fault. Once the fault condition occurs, the FAULT pin is internally pulled to VSS and the fault clear timer is activated. The fault output stays in the low state until the fault condition has been removed and the fault clear timer expires; once the fault clear timer expires, the voltage on the FAULT pin will return to VCC. The length of the fault clear time period (tFLTCLR) is determined by exponential charging characteristics of the capacitor where the time constant is set by RRCIN and CRCIN. In Figure 12 where we see that a fault condition has occurred (UVLO or ITRIP), RCIN and FAULT are pulled to VSS, and once the fault has been removed, the fault clear timer begins. Figure 13 shows that RRCIN is connected between the VCC and the RCIN pin, while CRCIN is placed between the RCIN and VSS pins. Figure 12: RCIN and FAULT pin waveforms The design guidelines for this network are shown in Table 3. Figure 13: Programming the fault clear timer ≤1 nF CRCIN Ceramic 0.5 M RRCIN to 2 M >> RON,RCIN Table 3: Design guidelines The length of the fault clear time period can be determined by using the formula below. vC(t) = Vf(1-e -t/RC ) tFLTCLR = -(RRCINCRCIN)ln(1-VRCIN,TH/VCC) www.irf.com © 2009 International Rectifier 24 IRS2336x(D) Family Over-Current Protection The IRS2336xD HVICs are equipped with an ITRIP input pin. This functionality can be used to detect over-current events in the DC- bus. Once the HVIC detects an over-current event through the ITRIP pin, the outputs are shutdown, a fault is reported through the FAULT pin, and RCIN is pulled to VSS. The level of current at which the over-current protection is initiated is determined by the resistor network (i.e., R0, R1, and R2) connected to ITRIP as shown in Figure 14, and the ITRIP threshold (VIT,TH+). The circuit designer will need to determine the maximum allowable level of current in the DC- bus and select R0, R1, and R2 such that the voltage at node VX reaches the over-current threshold (VIT,TH+) at that current level. VIT,TH+ = R0IDC-(R1/(R1+R2)) Figure 14: Programming the over-current protection For example, a typical value for resistor R0 could be 50 m . The voltage of the ITRIP pin should not be allowed to exceed 5 V; if necessary, an external voltage clamp may be used. Over-Temperature Shutdown Protection The ITRIP input of the IRS2336xD can also be used to detect over-temperature events in the system and initiate a shutdown of the HVIC (and power switches) at that time. In order to use this functionality, the circuit designer will need to design the resistor network as shown in Figure 15 and select the maximum allowable temperature. This network consists of a thermistor and two standard resistors R3 and R4. As the temperature changes, the resistance of the thermistor will change; this will result in a change of voltage at node VX. The resistor values should be selected such the voltage VX should reach the threshold voltage (VIT,TH+) of the ITRIP functionality by the time that the maximum allowable temperature is reached. The voltage of the ITRIP pin should not be allowed to exceed 5 V. When using both the over-current protection and over-temperature protection with the ITRIP input, OR-ing diodes (e.g., DL4148) can be used. This network is shown in Figure 16; the OR-ing diodes have been labeled D1 and D2. www.irf.com © 2009 International Rectifier 25 IRS2336x(D) Family Figure 15: Programming over-temperature protection Figure 16: Using over-current protection and overtemperature protection Truth Table: Undervoltage lockout, ITRIP, and ENABLE Table 4 provides the truth table for the IRS2336xD. The first line shows that the UVLO for VCC has been tripped; the FAULT output has gone low and the gate drive outputs have been disabled. VCCUV is not latched in this case and when VCC is greater than VCCUV, the FAULT output returns to the high impedance state. The second case shows that the UVLO for VBS has been tripped and that the high-side gate drive outputs have been disabled. After VBS exceeds the VBSUV threshold, HO will stay low until the HVIC input receives a new falling (IRS2336(D)) or rising (IRS23364D) transition of HIN. The third case shows the normal operation of the HVIC. The fourth case illustrates that the ITRIP trip threshold has been reached and that the gate drive outputs have been disabled and a fault has been reported through the fault pin. In the last case, the HVIC has received a command through the EN input to shutdown; as a result, the gate drive outputs have been disabled. VCC