IRS26072DSTRPBF

Data Sheet No. PD 97408A August 18, 2009 IRS26072DSPbF HIGH AND LOW SIDE DRIVER Features • • • • • • • • • • • • • Floating channel designed for bootstrap operation Integrated bootstrap diode suitable for Complimentary PWM switching schemes only IRS26072DSPBF is suitable for sinusoidal motor control applications IRS26072DSPBF is NOT recommended for Trapezoidal motor control applications Fully operational to 600 V Tolerant to negative transient voltage, dV/dt immune Gate drive supply range from 10 V to 20 V Under-Voltage lockout for both channels 3.3 V, 5 V, and 15 V input logic compatible Matched propagation delay for both channels Lower di/dt gate driver for better noise immunity Outputs in phase with inputs RoHS compliant Product Summary Topology VOFFSET VOUT Io+ & I o- (typical) tON & tOFF (typical) high and low side driver ≤ 600 V 10 V – 20 V 200 mA & 350 mA 200 ns Package Options Typical Applications • • • • Motor Control Air Conditioners/ Washing Machines General Purpose Inverters Micro/Mini Inverter Drivers 8-Lead SOIC Typical Connection Diagram Up to 600 V Vcc HIN LIN Vcc HIN LIN COM VB HO VS LO IRS26072D TO LOAD www.irf.com 13-Jul-09 © 2009 International Rectifier 1 IRS26072DSPbF Table of Contents Description Simplified Block Diagram Typical Application Diagram Qualification Information Absolute Maximum Ratings Recommended Operating Conditions Static Electrical Characteristics Dynamic Electrical Characteristics Functional Block Diagram Input/Output Pin Equivalent Circuit Diagram Lead Definitions Lead Assignments Application Information and Additional Details Parameter Temperature Trends Package Details Tape and Reel Details Part Marking Information Ordering Information Page 3 3 4 5 6 6 7 7 8 9 10 10 11 21 25 26 27 28 www.irf.com © 2009 International Rectifier 2 IRS26072DSPbF Description The IRS26072D is a high voltage, high speed power MOSFET and IGBT driver with independent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic inputs are compatible with CMOS or LSTTL outputs, down to 3.3 V. The output drivers feature a high-pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive N-channel power MOSFETs or IGBTs in the high side configuration up to 600 V. Simplified Block Diagram www.irf.com © 2009 International Rectifier 3 IRS26072DSPbF Typical Application Diagram www.irf.com © 2009 International Rectifier 4 IRS26072DSPbF Qualification Information† Industrial Qualification Level †† Comments: This IC has passed JEDEC industrial qualification. IR consumer qualification level is granted by extension of the higher Industrial level. MSL2 , 260°C (per IPC/JEDEC J-STD-020) Human Body Model Class 2 (per JEDEC standard JESD22-A114) Class B (per EIA/JEDEC standard EIA/JESD22-A115) Class I, Level A (per JESD78) Yes Moisture Sensitivity Level ESD Machine Model IC Latch-Up Test RoHS Compliant † †† Qualification standards can be found at International Rectifier’s web site http://www.irf.com/ Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. www.irf.com © 2009 International Rectifier 5 IRS26072DSPbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM unless otherwise specified. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VB VS VHO VCC VLO VIN PW HIN dVS/dt PD RthJA TJ TS TL † Definition High side floating supply voltage High side floating supply offset voltage High side floating output voltage Low side and logic fixed supply voltage Low side output voltage Logic and analog input voltages High-side input pulse width Allowable offset supply voltage slew rate Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) Min. -0.3 † VB - 20 VS - 0.3 -0.3 -0.3 -0.3 500 — — — — -50 — Max. 620 VB + 0.3 VB + 0.3 † 20 VCC + 0.3 VCC + 0.3 — 50 0.625 200 150 150 300 Units V ns V/ns W ° C/W ° C All supplies are fully tested at 25 V. An internal 20 V clamp exists for each supply. Recommended Operating Conditions For proper operation, the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to COM unless otherwise specified. The VS offset ratings are tested with all supplies biased at 15 V. Symbol VB VS VS(t) VHO VCC VLO VIN TA † †† Definition High side floating supply voltage † Static high side floating supply offset voltage †† Transient high side floating supply offset voltage High side floating output voltage Low side and logic fixed supply voltage Low side output voltage Logic input voltage Ambient temperature Min. VS +10 -8 -50 VS 10 0 0 -40 Max. VS + 20 600 600 VB 20 VCC VCC 125 Units Logic operation for VS of –8 V to 600 V. Logic state held for VS of –8 V to –VBS. Operational for transient negative VS of -50 V with a 50 ns pulse width. Guaranteed by design. Refer to the Application Information section of this datasheet for more details. www.irf.com ≤ Package power dissipation @ TA +25° C V ° C © 2009 International Rectifier 6 IRS26072DSPbF Static Electrical Characteristics (VCC-COM) = (VB-VS) = 15 V and TA = 25 C unless otherwise specified. The VIN and IIN parameters are referenced to COM. The VO and IO parameters are referenced to COM and VS and are applicable to the output leads LO and HO respectively. The VCCUV and VBSUV parameters are referenced to COM and VS respectively. Symbol Definition Min. Typ. Max. Units Test Conditions o VIH Logic “1” input voltage 2.5 — — VIL Logic “0” input voltage — — 0.8 VIN,TH+ Input positive going threshold — 1.9 — VIN,THInput negative going threshold — 1 — VOH High level output voltage — 0.8 1.4 IO = 20 mA V VOL Low level output voltage — 0.2 0.6 VCCUV+ VCC and VBS supply under-voltage positive 8.0 8.9 9.8 VBSUV+ going threshold VCCUVVCC and VBS supply under-voltage negative 6.9 7.7 8.5 VBSUVgoing threshold VCCUVH VCC and VBS supply under-voltage hysteresis 0.35 1.2 — VBSUVH ILK Offset supply leakage current — 1 50 VB =VS = 600 V µA IQBS Quiescent VBS supply current — 45 70 VIN = 0 V or 5 V IQCC Quiescent VCC supply current — 1.1 1.8 mA IIN+ Logic “1” input bias current — 5 20 VIN = 5 V µA IINLogic “0” input bias current — — 2 VIN = 0 V Io+ Output high short circuit pulsed current 120 200 — VO = 0 V or 15 V mA PW ≤ 10 µs IoOutput low short circuit pulsed current 250 350 — †† RBS — 200 — Bootstrap resistance †† Integrated bootstrap diode is suitable for Complimentary PWM schemes only. IRS26072D is suitable for sinusoidal motor control applications. IRS26072D is NOT recommended for Trapezoidal motor control applications. Refer to the Integrated Bootstrap Functionality section of this datasheet for more details. Dynamic Electrical Characteristics VCC = VB = 15 V, VS = COM, TA = 25 C and CL = 1000 pF unless otherwise specified. Symbol ton toff tr tf MT PM † Definition Turn-on propagation delay Turn-off propagation delay Turn-on rise time Turn-off fall time ton, toff propagation delay matching time † PW pulse width distortion Min. 100 100 — — — — Typ. 200 200 150 50 — — Max. 300 300 220 80 50 75 Units Test Conditions o ns VIN = 0V and 5V PW input =10µs PM is defined as PW IN - PW OUT. www.irf.com © 2009 International Rectifier 7 IRS26072DSPbF Functional Block Diagram VB UV DETECT R HV LEVEL SHIFTER HIN PULSE GENERATOR PULSE FILTER R S Q HO VS Integrated BS DIODE VCC UV DETECT LO LIN DELAY COM www.irf.com © 2009 International Rectifier 8 IRS26072DSPbF Input/Output Pin Equivalent Circuit Diagrams www.irf.com © 2009 International Rectifier 9 IRS26072DSPbF Lead Definitions Symbol VCC VB VS HIN LIN HO LO COM Description Low side and logic power supply High side floating power supply High side floating supply return Logic input for high side gate driver output HO, input is in-phase with output Logic input for low side gate driver output LO, input is in-phase with output High side gate driver output Low side gate driver output Low side supply return Lead Assignments www.irf.com © 2009 International Rectifier 10 IRS26072DSPbF Application Information and Additional Details • • • • • • • • • • • IGBT/MOSFET Gate Drive Switching and Timing Relationships Matched Propagation Delays Input Logic Compatibility Under-Voltage Lockout Protection Truth Table: Under-Voltage lockout Integrated Bootstrap Functionality Bootstrap Power Supply Design Tolerant to Negative VS Transients PCB Layout Tips Additional Documentation IGBT/MOSFET Gate Drive The IRS26072D HVIC is designed to drive high side and low side MOSFET or IGBT power devices. Figures 1 and 2 show the definition of some of the relevant parameters associated with the gate driver output functionality. The output current that drives the gate of the external power switches is defined as IO. The output voltage that drives the gate of the external power switches is defined as VHO for the high side and VLO for the low side; this parameter is sometimes generically called VOUT and in this case the high side and low side output voltages are not differentiated. VB (or VCC) VB (or VCC) IO+ HO (or LO) + HO (or LO) VHO (or VLO) VS (or COM) VS (or COM ) IO - Figure 1: HVIC sourcing current Figure 2: HVIC sinking current www.irf.com © 2009 International Rectifier 11 IRS26072DSPbF Switching and Timing Relationships The relationship between the input and output signals of the IRS26072D HVIC is shown in Figure 3. The definitions of some of the relevant parameters associated with the gate driver input to output transmission are given. LIN or HIN 50% PWIN 50% t ON tR 90% 10% PWOUT tOFF 90% tF LO or HO 10% Figure 3: Switching time waveforms During interval A of Figure 4 the HVIC receives the command to turn on both the high and low side switches at the same time; correspondingly, the high and low side signals HO and LO turn on simultaneously. Figure 4: Input/output timing diagram Matched Propagation Delays The IRS26072D HVIC is designed for propagation delay matching. With this feature, the input to output propagation delays tON, tOFF are the same for the low side and the high side channels; the maximum difference being specified by the delay matching parameter MT as defined in Figure 6. www.irf.com © 2009 International Rectifier 12 IRS26072DSPbF Figure 6: Delay Matching Waveform Definition Input Logic Compatibility The IRS26072D HVIC is designed with inputs compatible with standard CMOS and TTL outputs with 3.3 V and 5 V logic level signals. Figure 7 shows how an input signal is logically interpreted. Figure 7: HIN & LIN input thresholds Under-Voltage Lockout Protection The IRS26072D HVIC provides under-voltage lockout protection on both the VCC low side and logic fixed power supply and the VBS high side floating power supply. Figure 8 illustrates this concept by considering the VCC (or VBS) plotted over time: as the waveform crosses the UVLO threshold, the under-voltage protection is entered or exited. Upon power up, should the VCC voltage fail to reach the VCCUV+ threshold, the gate driver outputs LO and HO will remain disabled. Additionally, if the VCC voltage decreases below the VCCUV- threshold during normal operation, the under-voltage lockout circuitry will shutdown the gate driver outputs LO and HO. Upon power up, should the VBS voltage fail to reach the VBSUV threshold, the gate driver output HO will remain disabled. Additionally, if the VBS voltage decreases below the VBSUV threshold during normal operation, the undervoltage lockout circuitry will shutdown the high side gate driver output HO. www.irf.com © 2009 International Rectifier 13 IRS26072DSPbF The UVLO protection ensures that the HVIC drives external power devices only with a gate supply voltage sufficient to fully enhance them. Without this protection, the gates of the external power switches could be driven with a low voltage, which would result in power switches conducting current while with a high channel impedance, which would produce very high conduction losses possibly leading to power device failure. VCC (or V BS ) V CCUV + ( or V BSUV + ) VCCUV (or V BSUV - ) Time UVLO Protection ( Gate Driver Outputs Disabled ) Normal Operation Normal Operation Figure 8: UVLO protection Truth Table: Under-Voltage lockout Table 2 provides the truth table for the IRS26072D HVIC. The 1 line shows that for VCC below the UVLO threshold both the gate driver outputs LO and HO are disabled. After VCC returns above VCCUV, the gate driver outputs return functional. The 2 line shows that for VBS below the UVLO threshold, the gate driver output HO is disabled. After VBS returns above VBSUV, HO remains low until a new rising transition of HIN is received. The last line shows the normal operation of the HVIC. nd st VCC UVLO VCC UVLO VBS Normal operation