IRU3046CF

Data Sheet No. PD94251 IRU3046 DUAL SYNCHRONOUS PWM CONTROLLER WITH CURRENT SHARING CIRCUITRY AND LDO CONTROLLER PRELIMINARY DATA SHEET FEATURES Dual Synchronous Controller in 24-Pin Package with 1808 out-of-phase operation LDO Controller with Independent Bias Supply Can be configured as 2-Independent or 2-Phase PWM Controller Programmable Current Sharing in 2-Phase Configuration Flexible, Same or Separate Supply Operation Operation from 4V to 25V Input Programmable Switching Frequency up to 400KHz Soft-Start controls all outputs Precision Reference Voltage Available 500mA Peak Output Drive Capability Short Circuit Protection for all outputs Power Good Output Synchronizable with External Clock DESCRIPTION The IRU3046 IC combines a Dual synchronous Buck controller and a linear regulator controller, providing a cost-effective, high performance and flexible solution for multi-output applications. The Dual synchronous controller can be configured as 2-independent or 2-phase controller. In 2-phase configuration, the IRU3046 provides a programmable current sharing which is ideal when the output power exceeds any single input power budget. IRU3046 provides a separate adjustable output by driving a switch as a linear regulator. This device features programmable switching frequency up to 400KHz per phase, under-voltage lockout for all input supplies, an external programmable soft-start function as well as output under-voltage detection that latches off the device when an output short is detected. APPLICATIONS Dual-Phase Power Supply DDR Memory Source Sink Vtt Application Graphic Card Hard Disk Drive Power supplies requiring multiple outputs TYPICAL APPLICATION 12V L1 5V C1 C2 C3 C4 VCL C5 3.3V C6 VOUT2 C7 R2 C8 C9 R3 R4 Comp2 HDrv2 Q1 R1 Vcc VccLDO V SEN33 V OUT3 Fb3 IRU3046 Rt Sync Comp1 VcH1 VcH2 HDrv1 Q2 C13 C12 L2 D1 D2 C11 C14 L3 R5 VOUT1 C16 LDrv1 Q3 C15 R6 U1 PGnd V REF Vp2 Fb1 Fb2 Q4 C17 R7 R8 L4 R9 PGood C10 PGood SS LDrv2 Gnd Q5 C18 R10 Figure 1 - Typical application of IRU3046 configured as 2-phase converter with current sharing. PACKAGE ORDER INFORMATION TA (°C) 0 To 70 Rev. 1.9 09/27/02 DEVICE IRU3046CF PACKAGE 24-Pin Plastic TSSOP (F) www.irf.com FREQUENCY 200-400KHz 1 IRU3046 ABSOLUTE MAXIMUM RATINGS Vcc Supply Voltage .................................................. VccLDO, VcH1, VcH2 and VCL Supply Voltage ........... Storage Temperature Range ...................................... Operating Junction Temperature Range ..................... 25V 30V (not rated for inductive load) -65°C To 150°C 0°C To 125°C PACKAGE INFORMATION 24-PIN PLASTIC TSSOP (F) TOP VIEW VREF 1 Vp2 2 Fb2 3 Vcc 4 Comp1 5 Comp2 6 Rt 7 Sync 8 VcH2 9 HDrv2 10 LDrv2 11 PGnd 12 24 Gnd 23 PGood 22 VSEN33 21 Fb1 20 SS 19 Fb3 18 VOUT3 17 VccLDO 16 VcH1 15 HDrv1 14 LDrv1 13 VCL θJA = 84°C/W ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over Vcc=5V, VcH1=VcH2=VCL=VccLDO=12V and TA=0 to 70°C. Typical values refer to TA=25°C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature. PARAMETER Reference Voltage Section Fb Voltage Fb Voltage Line Regulation UVLO Section UVLO Threshold - Vcc UVLO Hysteresis - Vcc UVLO Threshold - VccLDO UVLO Hysteresis - VccLDO UVLO Threshold - VcH1 UVLO Hysteresis - VcH1 UVLO Threshold - VcH2 UVLO Hysteresis - VcH2 UVLO Threshold - Fb UVLO Hysteresis - Fb UVLO Threshold - VSEN33 UVLO Hysteresis - VSEN33 Supply Current Section Vcc Dynamic Supply Current VcH1 Dynamic Supply Current VcH2 Dynamic Supply Current Vcc Static Supply Current VcH1 Static Supply Current VcH2 Static Supply Current VccLDO Static Supply Current SYM VFB LREG TEST CONDITION MIN 1.225 5 FESR and FO1 [ (1/5 ~ 1/10)3 fS Use the following equation to calculate R4: R4 = 1 VOSC FO13FESR R5 + R6 3 3 3 VIN(MASTER) FLC2 R5 gm ---(13) ---(9) Where: VIN(MASTER) = Maximum Input Voltage VOSC = Oscillator Ramp Voltage FO1 = Crossover Frequency for the master E/A FESR = Zero Frequency of the Output Capacitor FLC(MASTER) = Resonant Frequency of Output Filter gm = Error Amplifier Transconductor R5 and R6 = Resistor Dividers for Output Voltage Programming For: VIN(MASTER) = 5V VOSC = 1.25V FO1 = 30KHz FESR = 25.26KHz FLC(MASTER) = 3.57KHz R5 = 1K R6 = 200V gm = 600mmho This results to: R4=29.7K V. Choose: R4=29.4K V To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: FZ ≅ 75%FLC(MASTER) FZ ≅ 0.75 3 1 2p LO 3 CO ---(14) V e C9 R4 H(s) dB FZ Frequency Figure 6 - Compensation network without local feedback and its asymptotic gain plot. The transfer function (Ve / VOUT) is given by: H(s) = gm3 ( R5 R6 + R5 sR ) 3 1 +sC C 4 9 9 ---(10) The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: |H(s)| = gm 3 R5 3 R4 R6 3 R5 ---(12) ---(11) For: Lo = 2.2m H Co = 900m F Fz = 2.67KHz R4 = 24.9K V Using equations (12) and (14) to calculate C9, we get: C9 = 2003pF Choose: C9 = 2200pF One more capacitor is sometimes added in parallel with C9 and R4. This introduces one more pole which is mainly used to suppress the switching noise. The additional pole is given by: 1 FP = C9 3 CPOLE 2p 3 R4 3 C9 + CPOLE 1 FZ = 2p 3 R4 3 C9 The gain is determined by the voltage divider and E/A's transconductance gain. Rev. 1.9 09/27/02 www.irf.com 9 IRU3046 The pole sets to one half of switching frequency which results in the capacitor CPOLE: 1 1 CPOLE = ≅ p 3 R4 3 fS 1 p 3 R4 3 fS C9 fS For FP < < 2 For a general solution for unconditionally stability for any type of output capacitors, in a wide range of ESR values we should implement local feedback with a compensation network. The typically used compensation network for voltage-mode controller is shown in Figure 7. ZIN C10 R8 R6 Fb1 R5 VREF VOUT C12 R7 C11 Zf As known, transconductance amplifier has high impedance (current source) output, therefore, consider should be taken when loading the E/A output. It may exceed its source/sink output current capability, so that the amplifier will not be able to swing its output voltage over the necessary range. The compensation network has three poles and two zeros and they are expressed as follows: FP1 = 0 FP2 = FP3 = 1 2p3R83C10 1 2p3R73 FZ1 = FZ2 = (CC 3C ) +C 12 11 12 11 ≅ 1 2p3R73C12 1 2p3R73C11 1 1 ≅ 2p3C103(R6 + R8) 2p3C103R6 E/A1 Comp1 V e Gain(dB) Cross Over Frequency: VIN 1 FO1 = R73C103 3 VOSC 2p3Lo3Co Where: VIN = Maximum Input Voltage VOSC = Oscillator Ramp Voltage Lo = Output Inductor Co = Total Output Capacitors ---(16) H(s) dB FZ1 FZ2 FP2 FP3 Frequency Figure 7 - Compensation network with local feedback and its asymptotic gain plot. In such configuration, the transfer function is given by: 1Ve = VOUT 1 + gmZf gmZIN The stability requirement will be satisfied by placing the poles and zeros of the compensation network according to following design rules. The consideration has been taken to satisfy condition (15) regarding transconductance error amplifier. 1) Select the crossover frequency: Fo < FESR and Fo [ (1/10 ~ 1/6)3 fS 2) Select R7, so that R7 > > 2 gm The error amplifier gain is independent of the transconductance under the following condition: gmZf >> 1 and gmZIN >>1 ---(15) By replacing ZIN and Zf according to figure 7, the transformer function can be expressed as: (1+sR7C11)3[1+sC10(R6+R8)] 3 H(s)= sR6(C12+C11) 1+sR7 C12C11 3(1+sR8C10) C12+C11 1 3) Place first zero before LC’s resonant frequency pole. FZ1 ≅ 75% FLC C11 = 1 2p 3 FZ1 3 R7 [ ( )] 10 www.irf.com Rev. 1.9 09/27/02 IRU3046 4) Place third pole at the half of the switching frequency. FP3 = C12 = fS 2 1 2p 3 R7 3 FP3 The transfer function of power stage is expressed by: IL2(s) VIN - VOUT G(s) = = ---(17) Ve(s) sL2 3 VOSC Where: VIN = Input Voltage VOUT = Output Voltage L2 = Output Inductor VOSC = Oscillator Peak Voltage As shown the transfer function is a function of inductor current. The transfer function for the compensation network is given by equation (18), when using a series RC circuit as shown in Figure 8: D(s) = Ve(s) = RS2 3 IL2(s) sC (g 3 R )3(1 +sC R ) ---(18) R S1 S2 m 2 2 2 C12 > 50pF If not, change R7 selection. 5) Place R7 in (16) and calculate C10: C10 [ 2p 3 Lo 3 FO 3 Co VOSC 3 R7 VIN 6) Place second pole at ESR zero. FP2 = FESR R8 = 1 2p 3 C10 3 FP2 1 gm Check if R8 > IL2 L2 Fb2 Comp2 Vp2 RS1 L1 IL1 E/A2 R2 C2 V e If R8 is too small, increase R7 and start from step 2. 7) Place second zero around the resonant frequency. FZ2 = FLC R6 = 1 - R8 2p 3 C10 3 FZ2 RS2 8) Use equation (1) to calculate R5: R5 = VREF 3 R6 VOUT - VREF These design rules will give a crossover frequency approximately one-tenth of the switching frequency. The higher the band width, the potentially faster the load transient speed. The gain margin will be large enough to provide high DC-regulation accuracy (typically -5dB to 12dB). The phase margin should be greater than 458 for overall stability. The slave error amplifier is a differential-input transconductance amplifier as well, the main goal for the slave feed back loop is to control the inductor current to match the masters inductor current as well provides highest bandwidth and adequate phase margin for overall stability. Figure 8 - The PI compensation network for slave channel. The loop gain function is: H(s)=[G(s) 3 D(s) 3 RS2] H(s)=RS23 V -V (g 3 R )3 (1+sR C ) 3(sL 3V ) R sC S1 S2 m 2 2 IN 2 OUT 2 OSC Select a zero crossover frequency (FO2) one-tenth of the switching frequency: FO2 = fS 10 FO2 = 20KHz Rev. 1.9 09/27/02 www.irf.com 11 IRU3046 H(Fo) = gm3RS13R23 VIN - VOUT =1 2p3Fo3L23VOSC ---(19) LDO Power MOSFET Selection The first step in selecting the power MOSFET for the linear regulator is to select the maximum RDS(ON) based on the input to the dropout voltage and the maximum load current. RDS(ON) = VIN3 - VOUT2 IOUT2 From (18), R2 can be express as: R2 = 1 2p 3 FO2 3 L2 3 VOSC 3 VIN(SLAVE) - VOUT gm 3 RS1 ---(20) Set the zero of compensator to be half of FLC(SLAVE) , the compensator capacitor, C2, can be calculated as: FLC(SLAVE) = Fz = C2 = 1 2p L23COUT For: VIN3 = 3.3V VOUT2 = 2.5V IOUT2 = 2A Results to: RDS(ON)(MAX) = 0.4V Note that since the MOSFET RDS(ON) increases with temperature, this number must be divided by ~1.5 in order to find the RDS(ON)(MAX) at room temperature. The IRLR2703 has a maximum of 0.065V RDS(ON) at room temperature, which meets our requirements. Layout Consideration The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Start to place the power components, make all the connection in the top layer with wide, copper filled areas. The inductor, output capacitor and the MOSFET should be close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place input capacitor directly to the drain of the high-side MOSFET, to reduce the ESR replace the single input capacitor with two parallel units. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. In multilayer PCB use one layer as power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. FLC(SLAVE) 2 1 2p 3 R2 3 Fz ---(21) Using equations (20) and (21) we get the following values for R2 and C2. R2=16.45K; Choose: R2=16.5K C2=6606pF; Choose: C2=6800pF LDO Section Output Voltage Programming Output voltage for LDO is programmed by reference voltage and external voltage divider. The Fb3 pin is the inverting input of the error amplifier, which is internally referenced to 1.25V. The divider is ratioed to provide 1.25V at the Fb3 pin when the output is at its desired value. The output voltage is defined by using the following equation: R7 VOUT2 = VREF3 1+ R10 For: VOUT2 = 2.5V VREF = 1.25V R10 = 1K V ( ) Results to R7=1K V VOUT3 IRU3046 Fb3 R10 R7 Figure 9 - Programming the output voltage for LDO. 12 www.irf.com Rev. 1.9 09/27/02 IRU3046 TYPICAL APPLICATION D1 12V C2 33uF L2 1uH C11 0.1uF D2 L1 5V C1 33uF 1uH C3 1uF C5 1uF 3.3V C6 47uF 2.5V @ 2A Q1 IRLR2703 R1 Fb3 C7 47uF 1K R2 1K R3 C8 2200pF Comp1 22K LDrv2 R4 C9 25K 1500pF PGood C10 0.1uF Comp2 PGood SS R5 1K R9 1K Q5 IRF7457 Rt Sync C4 1uF C13 VC L Vcc VccLDO VSEN33 VOUT3 LDrv1 PGnd Q3 IRF7457 VcH1 VcH2 HDrv1 1uF C14 2x 47uF Q2 IRF7460 L3 4.7uH 1.8V @ 8A C16 2x 150uF R7 442V C17 2x 150uF Q4 IRF7457 L4 3.9uH 2.5V @ 8A C12 2x 150uF R8 1K U1 IRU3046 Fb1 VREF Vp2 HDrv2 Fb2 Gnd Figure 10 - Typical application for IRU3046 configured as two independent controllers. Switching Frequency vs. Rt 400 370 340 Fs (KHz) 310 280 250 220 190 0 100 200 300 Rt Figure 11 - Switching frequency per phase vs. Rt 400 500 600 Rev. 1.9 09/27/02 www.irf.com 13 IRU3046 TYPICAL APPLICATION 12V L1 5V C1 33uF 1uH C3 1uF C5 1uF 3.3V C6 47uF 1.8V @ 2A Q1 IRLR2703 R1 Fb3 C7 47uF 442 R2 1K R3 C8 16.2K 3900pF R4 C9 10K 5600pF PGood C10 0.1uF Comp2 Fb2 PGood SS Vp2 Gnd R9 1K R5 VDDQ 1K Comp1 LDrv2 Rt Sync C4 1uF C13 1uF VCL Vcc VccLDO VSEN33 VOUT3 LDrv1 PGnd VcH1 VcH2 HDrv1 1/2 of D1 BAT54A 1/2 of Q2 IRF7313 1/2 of Q2 IRF7313 R7 1K R8 1K L2 5.6uH VDDQ 2.5V @ 4A C16 330uF C14 150uF U1 IRU3046 Fb1 C17 2x 150uF 1/2 of Q3 IRF7313 1/2 of Q3 IRF7313 L3 4.7uH VTT 1.25V @ 4A C12 330uF VREF HDrv2 1/2 of D1 BAT54A Figure 12 - Typical application for IRU3046 configured for DDR memory application. 14 www.irf.com Rev. 1.9 09/27/02 IRU3046 DEMO-BOARD APPLICATION Dual Input: 5V and 12V to 1.5V @ 16A 5V 12V L2 1uH C2 33uF L1 1uH C1 33uF D1 BAT54S C3 0.1uF C7 1uF C9 1uF C4 47uF C32 47uF C5 330uF C31 330uF C6 1uF VCL C8 1uF 3.3V Vcc VccLDO VSEN33 VOUT3 VH c1 VH c2 HDrv1 D2 BAT54A Q1 IRF7460 L3 2.2uH R3 C14 470pF R5 4.7V 5m V C10,C11,C12 3x 150uF C15 1uF 1.5V @ 16A R6 10V C13 47uF Q3 IRLR2703 R7 1K C18 47uF R10 1K LDrv1 PGnd VREF Vp2 Fb1 Fb2 Q2 IRF7457 2.5V @ 2A C30 1uF Fb3 U1 IRU3046 R8 200 Rt Sync R13 15K R16 29.4K R21 16.5K C24 2200pF C34 6.8nF Comp1 Comp2 HDrv2 D4 BAT54A Q4 IRF7460 C23 1uF L4 3.3uH C26 470pF R19 4.7V R17 5mV R12 1K C19,C20,C21 3x 150uF PGood PGood SS C29 0.1uF LDrv2 Gnd Q5 IRF7457 Figure 13 - Demo-board application of IRU3046. Rev. 1.9 09/27/02 www.irf.com 15 IRU3046 DEMO-BOARD APPLICATION Application Parts List Ref Desig Q1,Q4 Q2,Q5 Q3 U1 D1 D2,D4 L1,L2 L3 L4 C1,C2 C4,C32 C5,C31 C10,11,12, 19,20,21 C3,C29 C9 C24 C34 C14,C26 C6,7,8, 15,23,30 C13,C18 R2,4,15,18 R16 R21 R5,R19 R8 R7,10,12 R3,R17 R13 R6 Description MOSFET MOSFET MOSFET Controller Diode Diode Inductor Inductor Inductor Cap, Tantalum Cap, Poscap Cap, Poscap Cap, Poscap Cap, Cap, Cap, Cap, Cap, Cap, Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Value Qty Part# 20V, 10mV, 12A 2 IRF7460 20V, 7mV, 15A 2 IRF7457 30V, 0.045V, 23A 1 IRLR2703 Synchronous PWM 1 IRU3046 Fast Switching 1 BAT54S Fast Switching 2 BAT54A or 1N4148 1m H, 6.8A 2 D03316P-102 2.2m H, 12A 1 D05022P-222HC 3.3m H, 10A 1 D05022P-332HC 33m F, 16V 2 ECS-T1CD336R 47m F, 16V 2 16TPB47M 330m F, 6.3V 2 6TPB330M 150m F, 6.3V, 40mV 6 6TPC150M 0.1m F, Y5V, 25V 1m F, X7R, 25V 2200pF, X7R, 50V 6800pF, X7R, 50V 470pF, X7R, 50V 1m F, Y5V, 16V 47m F, 10V 2.15V 29.4K 16.5K 4.7V 200, 1% 1K, 1% 5mV, 1W, 1% 15K 10V 2 1 1 1 2 6 2 4 1 1 2 1 3 2 1 1 ECJ-2VF1E104Z ECJ-3YB1E105K ECJ-2VB1H222K ECJ-2VB1H682K ECJ-2VC1H471J ECJ-2VF1C105Z ECS-T1AD476R Manuf IR IR IR IR IR IR Any Coilcraft Coilcraft Coilcraft Panasonic Sanyo Sanyo Sanyo Web site (www.) irf.com coilcraft.com maco.panasonic.co.jp sanyo.com/industrial Panasonic maco.panasonic.co.jp Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Cap, Tantalum Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor ERJ-M1WSF5MOU Panasonic 16 www.irf.com Rev. 1.9 09/27/02 IRU3046 WAVEFORMS Figure 14 - Gate signals vs. inductor currents. Ch1: Gate signal for control FET(master) (10V/div). Ch2: Gate signal for control FET(slave) (20V/div). Ch3: Inductor current for master channel (5A/div). Ch4: Inductor current for slave channel (5A/div). VMASTER =5V, VSLAVE=12V, IOUT=10A Figure 15 - Inductors current matching. Ch1: Gate signal for sync FET(master) (10V/div). Ch2: Gate signal for sync FET(slave) (10V/div). Ch3: Inductor current for master channel (5A/div). Ch4: Inductor current for slave channel (5A/div). VMASTER =5V, VSLAVE=12V, IOUT=10A Figure 16 - Gate signals. Ch1: Gate signal for control FET(master) (10V/div). Ch2: Gate signal for sync FET(master) (10V/div). Ch3: Gate signal for control FET(slave) (20V/div). Ch4: Gate signal for sync FET(slave) (10V/div). Rev. 1.9 09/27/02 www.irf.com 17 IRU3046 WAVEFORMS V IN=5V Vss 10A V OUT 0A Figure 17 - Start-up @ IOUT = 10A. Figure 18 - Transient response @ IOUT = 0 to 10A. 2A 0A Figure 19 - Transient response for LDO @ IOUT = 0 to 2A. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 02/01 18 www.irf.com Rev. 1.9 09/27/02 IRU3046 (F) TSSOP Package 24-Pin A L Q R1 1.0 DIA B C R E M O PIN NUMBER 1 F D DETAIL A P N G DETAIL A J H K SYMBOL DESIG A B C D E F G H J K L M N O P Q R R1 MIN 4.30 0.19 7.70 --0.85 0.05 08 0.50 0.09 0.09 24-PIN NOM 0.65 BSC 4.40 6.40 BSC --1.00 1.00 7.80 --0.90 --128 REF 128 REF --1.00 REF 0.60 0.20 ----- MAX 4.50 0.30 7.90 1.10 0.95 0.15 88 0.75 ----- NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS. Rev. 1.9 09/27/02 www.irf.com 19 IRU3046 PACKAGE SHIPMENT METHOD PKG DESIG F PACKAGE DESCRIPTION TSSOP Plastic PIN COUNT 24 PARTS PER TUBE 74 PARTS PER REEL 2500 T&R Orientation Fig A 1 1 1 Feed Direction Figure A IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 02/01 20 www.irf.com Rev. 1.9 09/27/02