JANTX2N6782U

PD - 91699B IRFE110 REPETITIVE A ALANCHE AND dv/dt RATED V JANTX2N6782U  HEXFET TRANSISTORS JANTXV2N6782U SURFACE MOUNT (LCC-18) [REF:MIL-PRF-19500/556] 100V, N-CHANNEL Product Summary Part Number IRFE110 BVDSS 100V RDS(on) 0.60Ω ID 3.5A The leadless chip carrier (LCC) package represents the logical next step in the continual evolution of surface mount technology. Desinged to be a close replacement for the TO-39 package, the LCC will give designers the extra flexibility they need to increase circuit board density. International Rectifier has engineered the LCC package to meet the specific needs of the power market by increasing the size of the bottom source pad, thereby enhancing the thermal and electrical performance. The lid of the package is grounded to the source to reduce RF interference. LCC-18 Features: ! ! ! ! ! ! ! ! Surface Mount Small Footprint Alternative to TO-39 Package Hermetically Sealed Dynamic dv/dt Rating Avalanche Energy Rating Simple Drive Requirements Light Weight A bsolute Maximum Ratings Parameter ID @ VGS = 10V, TC = 25°C ID @ VGS = 10V, TC = 100°C I DM PD @ TC = 25°C VGS EAS IAR EAR dv/dt TJ T STG Continuous Drain Current Continuous Drain Current Pulsed Drain Current ➀ Max. Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy ➁ Avalanche Current ➀ Repetitive Avalanche Energy ➀ Peak Diode Recovery dv/dt ➂ Operating Junction Storage Temperature Range Pckg. Mounting Surface Temp. Weight For footnotes refer to the last page 3.5 2.25 14 15 0.09 ±20 7.0 9.0 -55 to 150 300 (for 5 S) 0.42(typical) Units A W W/°C V mJ A mJ V/ns o C g www.irf.com 1 1/17/01 I RFE110 Electrical Characteristics Parameter BVDSS ∆BV DSS/∆TJ RDS(on) VGS(th) gfs IDSS @ Tj = 25°C (Unless Otherwise Specified) Min 100 — — — 2.0 0.8 — — — — — — — — — — — — Typ Max Units — 0.12 — — — — — — — — — — — — — — — 6.1 — — 0.60 0.69 4.0 — 25 250 100 -100 6.6 1.7 3.5 15 25 25 20 — V V/°C Ω V S( ) µA nA nC Ω Test Conditions VGS = 0V, ID = 1.0mA Reference to 25°C, ID = 1.0mA VGS = 10V, ID =2.25A➃ VGS =10V, ID =3.5A ➃ VDS = VGS, ID =250µA VDS > 15V, IDS =2.25A➃ VDS=80V, VGS=0V VDS =80V VGS = 0V, TJ = 125°C VGS =20V VGS =-20V VGS =10V, ID= 3.5A VDS =50V VDD =50V, ID =3.5A, RG =7.5Ω Drain-to-Source Breakdown Voltage Temperature Coefficient of Breakdown Voltage Static Drain-to-Source On-State Resistance Gate Threshold Voltage Forward Transconductance Zero Gate Voltage Drain Current IGSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LS + LD Gate-to-Source Leakage Forward Gate-to-Source Leakage Reverse Total Gate Charge Gate-to-Source Charge Gate-to-Drain (‘Miller’) Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Inductance ns nH Measured from the center of drain pad to center of source pad VGS = 0V, VDS =25V f = 1.0MHz Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance — — — 190 86 13 — — pF Source-Drain Diode Ratings and Characteristics Parameter IS ISM VSD t rr QRR ton Continuous Source Current (Body Diode) Pulse Source Current (Body Diode) ➀ Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time Min Typ Max Units — — — — — — — — — — 3.5 14 1.5 180 2.0 Test Conditions A V nS µc Tj = 25°C, IS =3.5A, VGS = 0V ➃ Tj = 25°C, IF = 3.5A, di/dt ≤100A/µs VDD ≤50V ➃ Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD. Thermal Resistance Parameter RthJC RthJ-PCB Junction to Case Junction to PC Board Min Typ Max Units — — — — 8.3 °C/W 27" " " Test Conditions Soldered to a copper clad PC board For footnotes refer to the last page 2 www.irf.com IRFE110 100 I D , Drain-to-Source Current (A) 10 I D , Drain-to-Source Current (A) VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP 100 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP 10 1 1 4.5V 20µs PULSE WIDTH TJ = 25 °C 1 10 100 4.5V 0.1 0.1 VDS , Drain-to-Source Voltage (V) 0.1 0.1 20µs PULSE WIDTH TJ = 150 °C 1 10 100 VDS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 100 2.5 RDS(on) , Drain-to-Source On Resistance (Normalized) ID = 3.1A I D , Drain-to-Source Current (A) 2.0 10 T = 25 °C J T = 150 °C J 1.5 1.0 1 0.5 0.1 V DS= 50V 20µs PULSE WIDTH 4 5 6 7 8 9 10 0.0 -60 -40 -20 V GS = 10V 0 20 40 60 80 100 120 140 160 V GS, Gate-to-Source Voltage (V) TJ , Junction Temperature ( °C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3 I RFE110 400 VGS , Gate-to-Source Voltage (V) VGS = 0V, f = 1MHz Ciss = Cgs + Cgd , Cds SHORTED Crss = Cgd Coss = Cds + Cgd 20 ID = 3.5 A V DS = 80V V DS = 50V V DS = 20V 16 C, Capacitance (pF) 300 12 200 Ciss 8 100 Coss 4 0 Crss 1 10 100 0 FOR TEST CIRCUIT SEE FIGURE 13 0 2 4 6 8 VDS , Drain-to-Source Voltage (V) Q G , Total Gate Charge (nC) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 100 100 ISD , Reverse Drain Current (A) OPERATION IN THIS AREA LIMITED BY RDS(on) 10 TJ = 150 ° C ID , Drain Current (A) 10 100us TJ = 25 ° C 1 1ms 1 10ms 0.1 0.0 V GS = 0 V 0.5 1.0 1.5 2.0 0.1 TC = 25 °C TJ = 150 °C Single Pulse 1 10 100 1000 VSD ,Source-to-Drain Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRFE110 4.0 V DS RD I D , Drain Current (A) 3.0 VGS RG D.U.T. + -V DD 2.0 10V Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % 1.0 Fig 10a. Switching Time Test Circuit VDS 0.0 90% 25 50 75 100 125 150 TC , Case Temperature ( °C) 10% VGS Fig 9. Maximum Drain Current Vs. Case Temperature td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms 100 Thermal Response (Z thJC ) 10 D = 0.50 0.20 1 0.10 0.05 0.02 0.01 0.1 PDM SINGLE PULSE (THERMAL RESPONSE) t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak TJ = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1 10 0.01 0.00001 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 I RFE110 20 EAS , Single Pulse Avalanche Energy (mJ) TOP 15 15V BOTTOM ID 1.6A 2.2A 3.5A VDS L DRIVER 10 RG D.U.T IAS tp + V - DD A 10V 20V 0.01Ω 5 Fig 12a. Unclamped Inductive Test Circuit 0 25 50 75 100 125 150 V(BR)DSS tp Starting TJ , Junction Temperature ( °C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ QG 12V .2µF .3µF 10 V QGS VG QGD VGS 3mA D.U.T. + V - DS Charge IG ID Current Sampling Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit 6 www.irf.com IRFE110 ➀ Repetitive Rating; Pulse width limited by maximum junction temperature. ➁ VDD =25V, starting TJ = 25°C, Peak IL = 3.1A, F oot Notes: ➂ ISD ≤ 3.1A, di/dt ≤75A/µs, VDD≤ 100V, TJ ≤ 150°C Suggested RG =7.5 Ω ➃ Pulse width ≤ 300 µs; Duty Cycle ≤ 2% Case Outline and Dimensions — LCC-18 IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 IR EUROPEAN REGIONAL CENTRE: 439/445 Godstone Rd, Whyteleafe, Surrey CR3 OBL, UK Tel: ++ 44 (0)20 8645 8000 IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) 453 2200 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 (0) 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 011 451 0111 IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo 171 Tel: 81 (0)3 3983 0086 IR SOUTHEAST ASIA: 1 Kim Seng Promenade, Great World City West Tower, 13-11, Singapore 237994 Tel: ++ 65 (0)838 4630 IR TAIWAN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 10673 Tel: 886-(0)2 2377 9936 Data and specifications subject to change without notice. 1/01 www.irf.com 7