RIC7113A4

PD - 94703 RIC7113A4 RADIATION HARDENED HIGH AND LOW SIDE GATE DRIVER Features n Total dose capability to 100K Rad (Si) n Floating channel designed for bootstrap operation n Fully operational to +400V n Tolerant to negative transient voltage n dV/dt immune n Gate drive supply range from 10 to 20V n Undervoltage lockout for both channels n Separate logic supply range from 5 to 20V Logic and power ground ±5V offset n CMOS Schmitt-triggered inputs with pull-down n Cycle by cycle edge-triggered shutdown logic n Matched propagation delay for both channels n Outputs in phase with inputs n Hermetically Sealed n Lightweight Product Summary VOFFSET IO+/VOUT ton/off (typ.) Delay Matching(typ.) 400V max. 2A / 2A 10 - 20V 120 & 100 ns 5 ns Description The RIC7113A4 is a high voltage, high speed power MOSFET and IGBT driver with independent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL outputs. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 400 volts. Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Symbol VB VS V HO V CC VLO V DD VSS V IN dV s/dt PD RthJA TJ TS TL Parameter High Side Floating Supply Voltage High Side Floating Supply Offset Voltage High Side Floating Output Voltage Low Side Fixed Supply Voltage Low Side Output Voltage Logic Supply Voltage Logic Supply Offset Voltage Logic Input Voltage (HIN, LIN & SD) Allowable Offset Supply Voltage Transient (Figure 2) Package Power Dissipation @ TA ≤ +25°C Thermal Resistance, Junction to Ambient Junction Temperature Storage Temperature Lead Temperature (Soldering, 10 seconds) Weight Min. -0.5 — VS - 0.5 -0.5 -0.5 -0.5 VCC - 20 VSS - 0.5 — — — -55 -55 — Max. VS + 20 400 VB + 0.5 20 VCC + 0.5 VSS + 20 VCC + 0.5 VDD + 0.5 50 0.6 210 125 150 300 Units V V/ns W °C/W °C g 0.6(typical) www.irf.com 1 6/25/03 RIC7113A4 Pre-Irradiation Recommended Operating Conditions The Input/Output logic timing diagram is shown in Figure 1. The VS and VSS offset ratings are tested with all supplies biased at 15V differential. Symbol VB VS VHO VCC VLO VDD VSS VIN Parameter High Side Floating Supply Absolute Voltage High Side Floating Supply Offset Voltage High Side Floating Output Voltage Low Side Fixed Supply Voltage Low Side Output Voltage Logic Supply Voltage Logic Supply Offset Voltage Logic Input Voltage (HIN, LIN & SD) Min. VS + 10 -4 VS 10 0 VSS + 5 -5 VSS Max. VS + 20 400 VB 20 VCC VSS + 20 5 VDD Units V Dynamic Electrical Characteristics VBIAS (VCC, VBS, VDD) = 15V, and VSS = COM unless otherwise specified. The dynamic electrical characteristics are measured using the test circuit shown in Figure 3. Tj = 25°C Symbol ton t off tsd tr tf MT Parameter Turn-On Propagation Delay Turn-Off Propagation Delay Shutdown Propagation Delay Turn-On Rise Time Turn-Off Fall Time Delay Matching, HS & LS Turn-On/Off Min. — — — — — — Tj = -55 to 125°C Typ. Max. Min. Max. Units 120 100 110 25 17 5 150 125 140 35 25 20 — — — — — — 260 220 235 50 40 — Test Conditions VS = 0V VS = 400V VS = 400V CL = 1000pf CL = 1000pf |Hton-Lton| or|Htoff-Ltoff| ns Typical Connection 400 up to 500V HO VDD HIN SD LIN V SS VCC VDD HIN SD LIN VSS VCC COM LO VB VS TO LOAD 2 www.irf.com Pre-Irradiation RIC7113A4 Static Electrical Characteristics VBIAS (VCC, VBS, VDD) = 15V, unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are applicable to all three logic input pins: HIN, LIN and SD. The VO and IO parameters are referenced to COM or VS and are applicable to the respective output pins: HO or LO. Tj = 25°C Symbol VIH Parameter Logic “1” Input Voltage Min. 3.1 6.4 9.5 12.5 Typ. — — — — 1.8 3.8 6.0 8.3 1.2 0.1 50 230 340 30 40 1.0 9.7 9.4 9.6 9.4 — — Tj = -55 to 125°C Min. Max. Units 3.3 6.8 10 13.3 — — — — — — — — — — — — — — — — — — — — — — 1.7 3.6 5.7 7.9 1.5 0.1 250 500 600 60 70 10 — — — — — A — V µA V V Test Conditions V DD = 5V VDD = 10V VDD = 15V VDD = 20V VDD = 5V VDD = 10V VDD = 15V VDD = 20V VIN =VIH, IO = 0A VIN =VIH, IO = 0A VB = VS = 400V VIN =0V or VDD VIN =0V, or VDD VIN =0V, or VDD VIN = VDD VIN = 0V VIL Logic “0” Input Voltage — — — — VOH VOL ILK IQBS IQCC IQDD IIN+ IINVBSUV+ VBSUVVCCUV+ VCCUVIO+ IO- High Level Output Voltage, VBIAS - VO Low Level Output Voltage, VO Offset Supply Leakage Current Quiescent VBS Supply Current Quiescent VCC Supply Current Quiescent VDD Supply Current Logic “1” Input Bias Current Logic “0” Input Bias Current VBS Supply Undervoltage Positive Going Threshold VBS Supply Undervoltage Negative Going Threshold VCC Supply Undervoltage Positive Going Threshold VCC Supply Undervoltage Negative Going Threshold Output High Short Circuit Pulsed Current Output Low Short Circuit Pulsed Current — — — — — — — — 7.5 7.0 7.4 7.0 2.0 2.0 VO = 0V, VIN = VDD PW < 10 µs VO = 15V, VIN = 0V PW < 10 µs www.irf.com 3 RIC7113A4 Radiation Performance Radiation characteristics International Rectifier Radiation Hardened gate drivers are tested to verify their hardness capability. The hardness assurance program at International rectifier uses a Cobalt-60 (60 Co) source and heavy ion irradiation. Every wafer shall be tested per MIL-STD-883, Method 1019, test condition A “Ionizing Radiation (Total Dose) Test Procedure”. Both pre- and post- irradiation performances are tested and specified using the same drive circuitry and test conditions to provide a direct comparison. For Static Irradiation Test Conditions refer to figure 7. Static Electrical Characteristics Symbol VIH Tj = 25°C 100K Rads (Si) Parameter Logic “1” Input Voltage Units Test Conditions VDD = 5V VDD = 10V VDD = 15V VDD = 20V VDD = 5V VDD = 10V VDD = 15V VDD = 20V VIN =VIH, IO = 0A VIN =VIH, IO = 0A VB =VS = 400A VIN =0V or VDD VIN =0V or VDD VIN =0V or VDD VIN =VDD VIN =0V Min 3.1 6.4 9.5 12.5 — — — VOH VOL ILK IQBS IQCC IQDD IIN+ IINVBSUV+ VBSUVVCCUV+ VCCUVIO+ IOHigh Level Output Voltage, VBIAS - VO Low Level Output Voltage, VO Offset Supply Leakage Current Quiescent VBS Supply Current Quiescent VCC Supply Current Quiescent VDD Supply Current Logic “1” Input Bias Current Logic “0” Input Bias Current VBS Supply Undervoltage Positive Going Threshold VBS Supply Undervoltage Negative Going Threshold VCC Supply Undervoltage Positive Going Threshold VCC Supply Undervoltage Negative Going Threshold Output High Short Circuit Pulsed Current Output Low Short Circuit Pulsed Current — Max — — — — 1.8 3.8 6.0 8.3 1.2 0.1 50 230 340 30 40 1.0 9.7 9.4 9.9 9.6 V µA V VIL Logic “0” Input Voltage V — — — — — — — 7.5 7.0 7.4 7.0 2.0 2.0 — — A VO =0V, VIN =VDD PW < 10 µs VO =15V, VIN =0V PW < 10 µs 4 www.irf.com Radiation characteristics RIC7113A4 International Rectifier radiation hardened Gate Drivers have been characterized in heavy ion environment for Single Event Effects (SEE). Single Event Effects characterization data is illustrated below. For Static Bias Test Conditions refer to figure 8. Single Event Effect Safe Operating Area Ion Br I Au I Au LET MeV/(mg/cm2)) 37 60 82 85 100 Energy (MeV) 284 344 346 344 346 Angle (degrees) 0 0 0 45 35 VS (V) @VBS=-10V 400 325 250 400 400 @VBS=-15V 400 250 200 400 400 @VBS=-17.5V 400 200 175 350 350 Note: VCC/VDD = 20V, except for LET=100, then VCC/VDD = 17.5V STATIC BIAS 450 400 350 300 250 200 150 100 50 0 -10 -15 VB (V) -17.5 Br, 0° angle I, 0° angle Au, 0° angle I, 45° angle Au, 35° angle VS (V) Single Event Effect, Safe Operating Area www.irf.com 5 RIC7113A4 HV = 10 to 400V RIC7113 IRF820A Figure 1. Input/Output Logic Timing Diagram Figure 2. Floating Supply Voltage Transient Test Circuit ( t 40) 0 o 0V RIC7113 HIN LIN ton 50% 50% tr 90% toff 90% tf HO LO Figure 3. Switching Time Test Circuit 10% 10% Figure 4. Switching Time Waveform Definition HIN LIN 50% 50% SD 50% LO HO 10% tsd MT MT 90% HO LO 90% LO Figure 5. Shutdown Waveform Definitions HO Figure 6. Delay Matching Waveform Definitions 6 www.irf.com RIC7113A4 RIC7113 4K VDD VB 4K HO HIN VS Logic LIN 50 SD COM VCC LO 1 nF 20V 20V 2.4K 1 nF 400V VSS 4K Figure 7. Static Bias Conditions for Total Ionizing DoseTest RIC7113L4 SCHEMATIC 2 Figure 8. Static Bias Conditions for Single Event Effect Test www.irf.com 7 RIC7113A4 Functional Block Diagram V V DD R HIN S Q V /V DD CC LEVEL SHIFT HV LEVEL S HIFT B UV DETECT PULSE FILTER R R S Q HO PULSE GEN VS SD UV DETECT V CC LIN S R V SS Q V /V DD CC LEVEL SHIFT LO DELAY COM Lead Definitions Symbol Description VDD HIN SD LIN VSS VB HO VS VCC LO COM Logic supply Logic input for high side gate driver output (HO), in phase Logic input for shutdown Logic input for low side gate driver output (LO), in phase Logic ground High side floating supply High side gate drive output High side floating supply return Low side supply Low side gate drive output Low side return 8 www.irf.com RIC7113A4 Case Outline and Dimensions — 14 Lead FlatPack IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. Data and specifications subject to change without notice. 06/03 www.irf.com 9