IS21/22TF08G
IS21TF08G
IS22TF08G
8GB eMMC
With eMMC 5.1 Interface & pSLC Mode NAND
DATA SHEET
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. A
04/26/2022
1
IS21/22TF08G
8GB eMMC with eMMC 5.1 Interface & pSLC Mode NAND
FEATURES
•
Packaged NAND flash memory with eMMC 5.1 interface
- IS21/22TF08G: 8Gigabyte
•
•
•
•
•
•
•
•
•
•
•
Compliant with eMMC Specification Ver.4.3, 4.4, 4.41,4.5, 4.51, 5.0, 5.1
Device can be converted to eMMC 4.3, 4.41, 4.51, 5.0 via initializing
Bus mode
High-speed eMMC protocol
Clock frequency: 0-200MHz.
Ten-wire bus (clock, 1 bit command, 8 bit data bus) and a hardware reset.
Supports three different data bus widths : 1 bit(default), 4 bits, 8 bits
Data transfer rate: up to 52Mbyte/s (using 8 parallel data lines at 52 MHz)
Single data rate : up to 200Mbyte/s @ 200MHz (HS200)
Dual data rate : up to 400Mbyte/s @ 200MHz (HS400)
Operating voltage range :
VCCQ = 1.8 V/3.3 V (Automotive A2 Grade only supports 1.8V VCCQ)
VCC = 2.7 – 3.6V
Error free memory access
Internal error correction code (ECC) to protect data communication
Internal enhanced data management algorithm
Solid protection from sudden power failure, safe-update operations for data content
Security
Support secure erase and trim commands
Enhanced write protection with permanent and partial protection options
Key Features :
HS400, Field Firmware Update (FFU), Power Off Notification, Pre EOL information, Enhanced Device Life
time, Optimal Size
eMMC 5.1 Features:
Command Queuing, Enhanced Strobe, Cache Flushing Report, BKOPS Control, Cache Barrier, RPMB
Throughput Improve, Secure Write Protection.
Temperature range
Industrial Grade (I): -40 ℃ ~ 85 ℃
Automotive Grade (A1): -40 ℃ ~ 85 ℃
Automotive Grade (A2): -40 ℃ ~ 105 ℃ (The Surface Temperature of Tc cannot be over 115 ℃)
Package
153 FBGA (11.5mm x 13mm x 1.0mm)
100 FBGA (14.0mm x 18.0mm x 1.4mm)
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. A
04/26/2022
2
IS21/22TF08G
GENERAL DESCRIPTION
ISSI eMMC products follow the JEDEC eMMC 5.1 standard. It is ideal for embedded storage solutions for Industrial
application and automotive application, which require high performance across a wide range of operating
temperatures.
eMMC encloses the pSLC Mode NAND and eMMC controller inside as one JEDEC standard package, providing a
standard interface to the host. The eMMC controller directly manages NAND flash, including ECC, wear-leveling,
IOPS optimization and read sensing.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. A
04/26/2022
3
IS21/22TF08G
TABLE OF CONTENTS
FEATURES ............................................................................................................................................................ 2
GENERAL DESCRIPTION .................................................................................................................................... 3
TABLE OF CONTENTS ......................................................................................................................................... 4
1.
PERFORMANCE SUMMARY ................................................................................................................... 6
1.1
Typical Sequential Burst Performance (PSA Pseudo-SLC Burst Status) .......................................... 6
1.2
Typical Sequential Sustained Performance (Normal Status) .............................................................. 6
1.3
Typical Random Burst Performance (PSA Pseudo SLC Burst Status) .............................................. 7
1.4
Typical Random Sustained Performance (Normal Status) .................................................................. 7
1.5
Device Power Consumption RMS VCC/VCCQ (TA = 25 ℃ @ 3.3V/1.8V) ................................................. 8
1.6
Device Power Consumption Standby VCC/VCCQ (TA = 25 ℃ @ 3.3V/1.8V) ........................................... 8
1.7
BOOT PARTITION AND RPMB (REPLAY PROTECTED MEMORY BLOCK) ....................................... 9
1.8
USER DENSITY ...................................................................................................................................... 10
2.
PIN CONFIGURATION and DDESCRIPTIONS ...................................................................................... 11
3.
OPERATING and STORAGE TEMPERATURE...................................................................................... 14
4.
eMMC Device and System ...................................................................................................................... 15
4.1 Memory Addressing..................................................................................................................................... 15
5.
REGISTER SETTINGS ........................................................................................................................... 16
5.1 OCR Register ................................................................................................................................................ 16
5.2
CID Register ........................................................................................................................................... 16
5.3
CSD Register .......................................................................................................................................... 16
5.4
Extended CSD Register......................................................................................................................... 19
6.
The eMMC BUS ....................................................................................................................................... 25
7.
eMMC Device Overview .......................................................................................................................... 26
7.1
Clock (CLK) ............................................................................................................................................ 26
7.2
Data Strobe ............................................................................................................................................. 26
7.3
Command (CMD) .................................................................................................................................... 26
7.4
Input/Outputs (DAT0-DAT7) .................................................................................................................. 26
8.
eMMC Functional Description.................................................................................................................. 27
8.1
Pseudo Technology (pSLC) .................................................................................................................. 27
8.2
Field Firmware Update (FFU) ................................................................................................................ 27
8.3
Power Off Notification for Sleep........................................................................................................... 28
8.4
Enhanced User Data Area ..................................................................................................................... 29
8.5
Write Cache ............................................................................................................................................ 29
8.6
Cache Enhancement Barrier................................................................................................................. 29
8.7
Cache Flushing Policy .......................................................................................................................... 30
8.8
Command Queuing (Disable by default) ............................................................................................. 31
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IS21/22TF08G
8.9
Production State Awareness (PSA) ..................................................................................................... 32
9.
PACKAGE TYPE INFORMATION ........................................................................................................... 33
9.1 100-ball FBGA Package (Q) .......................................................................................................................... 33
9.2 153-BALL FBGA Package (C) ....................................................................................................................... 34
10.
ORDERING INFORMATION – Valid Part Numbers ................................................................................ 35
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IS21/22TF08G
1. PERFORMANCE SUMMARY
1.1 Typical Sequential Burst Performance (PSA Pseudo-SLC Burst Status)
Speed Mode & Operation
Write
Cache On
8GB
Unit
Read
320
MB/s
Write
135
MB/s
Read
320
MB/s
Write
130
MB/s
Read
175
MB/s
Write
140
MB/s
Read
175
MB/s
Write
120
MB/s
HS400
Write
Cache Off
Write
Cache On
HS200
Write
Cache Off
Notes:
1. Values for an 8-bit bus width, running ISSI proprietary tool, VCC=3.3V, VCCQ=1.8V.
2. Performance numbers might be subject to changes without notice.
3. The write cache size is 1536KB.
1.2 Typical Sequential Sustained Performance (Normal Status)
Speed Mode & Operation
Write
Cache On
8GB
Unit
Read
320
MB/s
Write
135
MB/s
Read
320
MB/s
Write
125
MB/s
Read
175
MB/s
Write
135
MB/s
Read
175
MB/s
Write
120
MB/s
HS400
Write
Cache Off
Write
Cache On
HS200
Write
Cache Off
Notes:
1. Values for an 8-bit bus width, running HS400 mode, VCC=3.3V, VCCQ=1.8V.
2. Performance numbers might be subject to changes without notice.
3. The write cache size is 1536KB.
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IS21/22TF08G
1.3 Typical Random Burst Performance (PSA Pseudo SLC Burst Status)
Speed Mode & Operation
Write
Cache On
8GB
Unit
Read
24,000
IOPS
Write
28,000
IOPS
Read
24,000
IOPS
Write
2,400
IOPS
Read
24,000
IOPS
Write
28,000
IOPS
Read
24,000
IOPS
Write
2,300
IOPS
HS400
Write
Cache Off
Write
Cache On
HS200
Write
Cache Off
Notes:
1. Values for an 8-bit bus width, running ISSI proprietary tool, VCC=3.3V, VCCQ=1.8V.
2. Performance numbers might be subject to changes without notice.
3. The write cache size is 1536KB.
1.4 Typical Random Sustained Performance (Normal Status)
Speed Mode & Operation
Write
Cache On
8GB
Unit
Read
24,000
IOPS
Write
28,400
IOPS
Read
24,000
IOPS
Write
2,400
IOPS
Read
24,000
IOPS
Write
28,500
IOPS
Read
24,000
IOPS
Write
2,300
IOPS
HS400
Write
Cache Off
Write
Cache On
HS200
Write
Cache Off
Notes:
1. Values for an 8-bit bus width, running ISSI proprietary tool, VCC=3.3V, VCCQ=1.8V.
2. Performance numbers might be subject to changes without notice.
3. The write cache size is 1536KB.
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Rev. A
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IS21/22TF08G
1.5 Device Power Consumption RMS VCC/VCCQ (TA = 25 ℃ @ 3.3V/1.8V)
Speed Mode & Operation
8GB
Unit
ICC
55
mA
ICCQ
220
mA
ICC
55
mA
ICCQ
120
mA
ICC
40
mA
ICCQ
220
mA
ICC
55
mA
ICCQ
120
mA
Read
HS400
Write
Read
HS200
Write
Notes:
1. The measurement for RMS current is done as average RMS current consumption over a period of 100ms.
2. Current numbers might be subject to changes without notice.
1.6 Device Power Consumption Standby VCC/VCCQ (TA = 25 ℃ @ 3.3V/1.8V)
Speed Mode & Operation
HS400
HS200
8GB
Unit
CMD5 Sleep
190
uA
Standby ICCQ
240
uA
Standby ICC
30
uA
CMD5 Sleep
190
uA
Standby ICCQ
240
uA
Standby ICC
30
uA
Notes:
1. The current is measured at VCC = 3.3V + 5%, VCCQ = 1.8V + 5%, 8-bit bus width without clock frequency..
2. Current numbers might be subject to changes without notice.
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Rev. A
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IS21/22TF08G
1.7 BOOT PARTITION AND RPMB (REPLAY PROTECTED MEMORY BLOCK)
Option
Boot partition 1
Boot partition 2
RPMB
J
4,096 KB
4,096 KB
4,096 KB
B
16,384 KB
16,384 KB
4,096 KB
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9
IS21/22TF08G
1.8 USER DENSITY
Total user density depends on device type (Flash Mode).
Part Number
Capacity
Flash Mode
User Density Size
IS/2122TF08G
8GB
pSLC
7,817,134,080 Bytes
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IS21/22TF08G
2. PIN CONFIGURATION and DDESCRIPTIONS
153 FBGA Top View (Ball Down)
3
4
DAT
DAT
DAT
0
1
DAT
DAT
3
4
6
7
8
9
2
VSS
RFU
NC
NC
DAT
DAT
DAT
5
6
7
NC
NC
NC
NC
11
12
13
14
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RFU
NC
NC
NC
VCC
RFU
NC
NC
NC
RFU
VSS
RFU
NC
NC
NC
NC
NC
DS
VSS
NC
NC
NC
NC
NC
NC
VSS
VCC
NC
NC
NC
K
NC
NC
NC
RFU
NC
NC
NC
L
NC
NC
NC
NC
NC
NC
M
NC
NC
NC
N
NC
P
NC
NC
1
2
1
2
A
NC
NC
B
NC
C
NC
I
NC
D
NC
NC
NC
E
NC
NC
NC
RFU
F
NC
NC
NC
G
NC
NC
H
NC
J
VDD
5
VSS
VCC
NC
Q
Q
NC
VCC
VSS
RFU
RFU
RST
_n
RFU
RFU
VSS
VCC
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q
RFU
NC
NC
RFU
NC
NC
NC
NC
6
7
8
9
10
11
12
CMD
VCC
VSS
Q
Q
VCC
VSS
VCC
VSS
Q
Q
Q
3
4
5
VSS
Q
CLK
Q
NC
eMMC
Note:
1.
10
SUPPLY
GROUND
NC
13
14
RFU
H5 (DS), A6 (VSS) and J5 (VSS) can be left floating if HS400 mode is not used.
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IS21/22TF08G
100 FBGA Top View (Ball Down)
1
2
A
NC
NC
B
NC
4
3
5
6
8
7
9
10
NC
NC
NC
C
D
RFU
RFU
E
RFU
RFU
F
VCC
G
RFU
RFU
RFU
RFU
RFU
RFU
I
RFU
RFU
RFU
RFU
RFU
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VSS
Q
Q
RFU
RFU
RFU
RFU
Q
Q
RFU
RFU
RFU
VSS
RFU
RFU
RFU
RFU
DAT
DAT
DAT
DAT
0
2
RFU
DS
RFU
RFU
5
7
VCC
VSS
VCC
RFU
RFU
Q
Q
Q
RFU
RFU
DAT
DAT
4
6
VCC
VSS
Q
Q
VDD
H
J
K
VCC
VSS
VCC
L
Q
Q
Q
M
RFU
RFU
DAT
DAT
1
3
VSS
VCC
Q
Q
N
P
VSS
RST
Q
_n
RFU
RFU
RFU
RFU
RFU
CMD
CLK
RFU
VSS
RFU
Q
R
T
NC
U
NC
1
NC
NC
2
eMMC
Note:
1.
NC
3
4
SUPPLY
5
6
GROUND
8
7
NC
9
NC
10
RFU
K5 (DS) and J5 (VSS) can be left floating if HS400 mode is not used.
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IS21/22TF08G
PIN DESCRIPTIONS
Pin Name
CLK
Clock Signal
DAT0~DAT7 Data Bus
Description
CMD
Command Signal
RST#
DS
Hardware Reset Signal
Data Strobe Signal, used in HS400 mode.
VDDI
Connect capacitor from VDDI to GND for stabilize internal power.
VCC
Supply voltage for controller and Flash memory power.
VCCQ
Supply voltage for controller and Flash memory I/O power.
VSS
Supply voltage ground for controller and Flash memory. Can be short with VSSQ.
VSSQ
Supply voltage ground for controller and Flash memory I/O. Can be short with
VSSQ.
RFU
Reserved For Future Use. Left it floating for future use.
NC
In eMMC chip is no connect. Left it floating.
Note:
1.
I: input; O: output; PP: push-pull; OD: open-drain; NC: Not connected (or logical high); S: power
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IS21/22TF08G
3. OPERATING and STORAGE TEMPERATURE
Grade
Condition
Minimum and Maximum Ambient Temperature
Industrial
Maximum Case Temperature
Temperature
(1)
(1)
Minimum and Maximum Non-operating Temperature (2)
Minimum and Maximum Ambient Temperature (1)
Auto (A1)
Maximum Case Temperature (1)
Minimum and Maximum Non-operating Temperature (2)
Minimum and Maximum Ambient Temperature (1)
Auto (A2)
Maximum Case Temperature (1)
Minimum and Maximum Non-operating Temperature (2)
-40 ℃ to 85 ℃
95 ℃
-40 ℃ to 85 ℃
-40 ℃ to 85 ℃
95 ℃
-40 ℃ to 85 ℃
-40 ℃ to 105 ℃
115 ℃
-40 ℃ to 105 ℃
Notes:
1.
To achieve optimized and performance, case temperature should not exceed maximum ambient operating
temperature.
2.
After being soldered onto PCBA.
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IS21/22TF08G
4. eMMC Device and System
eMMC consists of a single chip MMC controller and NAND flash memory module. The micro-controller interfaces with a host
system allowing data to be written to and read from the NAND flash memory module. The controller allows the host to be
independent from details of erasing and programming the flash memory.
Figure 4.1 eMMC System Overview
4.1 Memory Addressing
Previous implementations of the eMMC specification are following byte addressing with 32-bit field. This addressing
mechanism permitted for eMMC densities up to and including 2 GB.
To support larger density, the addressing mechanism was update to support sector addresses (512 B sectors). The
sector addresses shall be used for all devices with capacity larger than 2 GB.
To determine the addressing mode, use the host should read bit [30:29] in the OCR register.
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IS21/22TF08G
5. REGISTER SETTINGS
Within the Device interface six registers are defined: OCR, CID, CSD, EXT_CSD, RCA and DSR. These can be
accessed only by corresponding commands (see Section 6.10 of JESD84-B51).
5.1 OCR Register
The 32-bit operation conditions register (OCR) stores the VDD voltage profile of the Device and the access mode
indication. In addition, this register includes a status information bit. This status bit is set if the Device power up
procedure has been finished. The OCR register shall be implemented by all Devices.
Table 5.1 OCR Register
VCCQ Voltage Window
Device power up status bit (busy)
Width (Bits)
OCR Bit
OCR Value
(1)
1
[31]
Note 1
Access Mode
2
[30:29]
10b (sector mode)
Reserved
5
[28:24]
0 0000b
VCCQ: 2.7 – 3.6V
9
[23:15]
1 1111 1111b
VCCQ: 2.0 – 2.6V
VCCQ: 1.7 – 1.95V
Reserved
7
1
7
[14:8]
[7]
[6:0]
000 0000b
1b
000 0000b
Note:
1.
This bit is set to LOW if the device has not finished the power up routine.
5.2 CID Register
The Card Identification (CID) register is 128 bits wide. It contains the Device identification information used during
the Device identification phase (eMMC protocol).
Table 5.2 CID Register
CID Bits
CID Value
MID
Width
(Bits)
8
[127:120]
9Dh
-
6
[119:114]
0h
CBX
2
[113:112]
1h
Name
Field
Manufacturer ID
Reserved
Device/BGA
OEM/application ID
Product name
OID
PNM
8GB
8
[111:104]
1h
48
[103:56]
IS008G
Product Revision
PRV
8
[55:48]
51h
Product Serial Number
PSN
32
[47:16]
Random by Production
Manufacturing Date
MDT
8
[15:8]
Month, Year
CRC7 Checksum
CRC
7
[7:1]
Not used, always “1”
-
1
[0]
-
(1)
1h
Note:
1. The description is same as e.MMC ™ JEDEC standard.
5.3 CSD Register
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IS21/22TF08G
The Card-Specific Data (CSD) register provides information on how to access the contents stored in eMMC. The
CSD registers are used to define the error correction type, maximum data access time, data transfer speed, data
format…etc. For details, refer to section 7.3 of the JEDEC Standard Specification No.JESD84-B51.
Table 5.3 CSD Register
2
4
2
8
Cell
Type
R
R
R
R
CSDslice
[127:126]
[125:122]
[121:120]
[119:112]
NSAC
8
R
[111:104]
1h
TRAN_SPEED
CCC
READ_BL_LEN
8
12
4
[103:96]
[95:84]
[83:80]
32h
8F5h
9h
READ_BL_PARTIAL
1
R
R
R
R
[79:79]
0h
WRITE_BLK_MISALIGN
READ_BLK_MISALIGN
DSR_IMP
C_SIZE
1
1
1
2
12
[78:78]
[77:77]
[76:76]
[75:74]
[73:62]
0h
0h
0h
0h
FFFh
VDD_R_CURR_MIN
3
R
R
R
R
R
R
[61:59]
7h
VDD_R_CURR_MAX
3
[58:56]
7h
VDD_W_CURR_MIN
3
[55:53]
7h
VDD_W_CURR_MAX
3
[52:50]
7h
C_SIZE_MULT
ERASE_GRP_SIZE
ERASE_GRP_MULT
WP_GRP_SIZE
WP_GRP_ENABLE
DEFAULT_ECC
R2W_FACTOR
WRITE_BL_LEN
3
5
5
5
1
2
3
4
[49:47]
[46:42]
[41:37]
[36:32]
[31:31]
[30:29]
[28:26]
[25:22]
7h
1Fh
1Fh
0Fh
1h
0h
2h
9h
WRITE_BL_PARTIAL
1
R
R
R
R
R
R
R
R
R
[21:21]
0h
-
4
R
[20:17]
0h
Name
Field
Width
CSD structure
System specification version
Reserved
Data read access-time 1
Data read access-time 2 in
CLK
cycles (NSAC*100)
Max. bus clock frequency
Device command classes
Max. read data block length
Partial blocks for read
allowed
Write block misalignment
Read block misalignment
DSR implemented
Reserved
Device size
Max. read current @ VDD
min
Max. read current @ VDD
max
Max. write current @ VDD
min
Max. write current @ VDD
max
Device size multiplier
Erase group size
Erase group size multiplier
Write protect group size
Write protect group enable
Manufacturer default ECC
Write speed factor
Max. write data block length
Partial blocks for write
allowed
Reserved
CSD_STRUCTURE
SPEC_VERS
TAAC
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R
R
R
Value
3h
4h
0h
4Fh
17
IS21/22TF08G
Name
Content protection
application
File format group
Copy flag (OTP)
Permanent write protection
Temporary write protection
File format
ECC code
CRC
Not used, always’1’
Field
Width
CONTENT_PROT_APP
1
FILE_FORMAT_GRP
COPY
PERM_WRITE_PROTECT
TMP_WRITE_PROTECT
FILE_FORMAT
ECC
CRC
-
1
1
1
1
2
2
7
1
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Cell
Type
R
CSDslice
Value
[16:16]
0h
R/W
R/W
R/W
R/W/E
R/W
R/W/E
R/W/E
-
[15:15]
[14:14]
[13:13]
[12:12]
[11:10]
[9:8]
[7:1]
[0:0]
0h
0h
0h
0h
0h
0h
2Eh
1h
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IS21/22TF08G
5.4 Extended CSD Register
The Extended CSD register defines the Device properties and selected modes. It is 512 bytes long. The most
significant 320 bytes are the Properties segment, which defines the Device capabilities and cannot be modified
by the host. The lower 192 bytes are the Modes segment, which defines the configuration the Device is working
in. These modes can be changed by the host by means of the SWITCH command.
Table 5.4 ECSD Register
Name
Properties Segment
Reserved
Extended Security Commands
Error
Supported Command Sets
HPI features
Background operations support
Max packed read commands
Max packed write commands
Data Tag Support
Tag Unit Size
Tag Resources Size
Context management
capabilities
Large Unit size
Extended partitions attribute
support
Supported modes
FFU features
Operation codes timeout
FFU Argument
Barrier support
Reserved
CMDQ support
CMDQ depth
Reserved
Number of FW sectors correctly
programmed
Vendor proprietary health report
Device life time estimation type
B
Device life time estimation type
A
Pre EOL information
Optimal read size
Optimal write size
Field
Size
(Bytes)
CSD-slice
Value
–
6
[511:506]
0h
EXT_SECURITY_ERR
1
[505]
0h
S_CMD_SET
HPI_FEATURES
BKOPS_SUPPORT
MAX_PACKED_READS
MAX_PACKED_WRITES
DATA_TAG_SUPPORT
TAG_UNIT_SIZE
TAG_RES_SIZE
1
1
1
1
1
1
1
1
[504]
[503]
[502]
[501]
[500]
[499]
[498]
[497]
1h
1h
1h
20h
20h
1h
3h
0h
CONTEXT_CAPABILITIES
1
[496]
5h
LARGE_UNIT_SIZE_M1
1
[495]
18h
EXT_SUPPORT
1
[494]
3h
SUPPORTED_MODES
FFU_FEATURES
OPERATION_CODE_TIME_
OUT
FFU_ARG
BARRIER_SUPPORT
Reserved
CMDQ_SUPPORT
CMDQ_DEPTH
Reserved
NUMBER_OF_FW_SECTOR
S_CORRECTLY_PROGRAM
MED
VENDOR_PROPRIETARY_H
EALTH_REPORT
DEVICE_LIFE_TIME_EST_T
YP_B
DEVICE_LIFE_TIME_EST_T
YP_A
PRE_EOL_INFO
OPTIMAL_READ_SIZE
OPTIMAL_WRITE_SIZE
1
1
[493]
[492]
3h
0h
1
[491]
0h
4
1
177
1
1
1
[490:487]
[486]
[485:309]
[308]
[307]
[306]
0h
0h
0h
1h
1Fh
0h
4
[305:302]
0h
32
[301:270]
–
1
[269]
1h
1
[268]
1h
1
1
1
[267]
[266]
[265]
1h
1h
8h
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IS21/22TF08G
Name
Field
Optimal trim unit size
Device version
Firmware version
Power class for 200MHz,
DDR at VCC=3.6V
Cache size
Generic CMD6 timeout
Power off notification(long)
timeout
Background operations status
Number of correctly
programmed sectors
1st initialization time after
partitioning
Cache Flushing Policy
Power class for 52MHz, DDR at
3.6V
Power class for 52MHz, DDR at
1.95V
Power class for 200MHz at 3.6V
Power class for 200MHz, at
1.95V
Minimum Write Performance for
8bit at 52MHz in DDR mode
Minimum Read Performance for
8bit at 52MHz in DDR mode
Reserved
TRIM Multiplier
Secure Feature support
Secure Erase Multiplier
Secure TRIM Multiplier
Boot information
Reserved
OPTIMAL_TRIM_UNIT_SIZE
DEVICE_VERSION
FIRMWARE_VERSION
Size
(Bytes)
1
2
8
PWR_CL_DDR_200_360
Boot partition size
BOOT_SIZE_MULTI
Access size
High-capacity erase unit size
High-capacity erase timeout
Reliable write sector count
High-capacity write protect
group size
Sleep current (VCC)
CSD-slice
Value
[264]
[263:262]
[261:254]
1h
0h
– (note 5)
1
[253]
0h
CACHE_SIZE
GENERIC_CMD6_TIME
4
1
[252:249]
[248]
600h
Ah
POWER_OFF_LONG_TIME
1
[247]
32h
BKOPS_STATUS
CORRECTLY_PRG_SECTOR
S_NUM
1
[246]
0h
4
[245:242]
0h
INI_TIMEOUT_AP
1
[241]
1Eh
CACHE_FLUSH_POLICY
1
[240]
1h
PWR_CL_DDR_52_360
1
[239]
0h
PWR_CL_DDR_52_195
1
[238]
0h
PWR_CL_200_360
1
[237]
0h
PWR_CL_200_195
1
[236]
0h
MIN_PERF_DDR_W_8_52
1
[235]
4Bh
MIN_PERF_DDR_R_8_52
1
[234]
0h
–
TRIM_MULT
SEC_FEATURE_SUPPORT
SEC_ERASE_MULT
SEC_TRIM_MULT
BOOT_INFO
–
1
1
1
1
1
1
1
[233]
[232]
[231]
[230]
[229]
[228]
[227]
1
[226]
ACC_SIZE
HC_ERASE_GRP_SIZE
ERASE_TIMEOUT_MULT
REL_WR_SEC_C
1
1
1
1
[225]
[224]
[223]
[222]
0h
12h
55h
64h
64h
7h
0h
20h
80h
7h
1h
12h
1h
HC_WP_GRP_SIZE
1
[221]
10h
S_C_VCC
1
[220]
8h
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. A
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J-option
B-option
20
IS21/22TF08G
Name
Field
Sleep current (VCCQ)
Production state awareness
Timeout
Sleep/awake timeout
S_C_VCCQ
PRODUCTION_STATE_AW
ARENESS_TIMEOUT
S_A_TIMEOUT
SLEEP_NOTIFICATION_TI
ME
SEC_COUNT
Sleep Notification timeout
Sector Count
Security write protect
information
Minimum Write Performance
for 8bit at 52MHz
Minimum Read Performance
for 8bit at 52MHz
Minimum Write Performance
for 8bit at 26MHz, for 4bit at
52MHz
Minimum Read Performance
for 8bit at 26MHz, for 4bit at
52MHz
Minimum Write Performance
for 4bit at 26MHz
Minimum Read Performance
for 4bit at 26MHz
Reserved
Power class for 26MHz at 3.6V
1R
Power class for 52MHz at 3.6V
1R
Power class for 26MHz at
1.95V 1 R
Power class for 52MHz at
1.95V 1 R
Partition switching timing
Out-of-interrupt busy timing
I/O Driver Strength
Device type
Reserved
CSD structure version
Reserved
Extended CSD revision
Modes Segment
Command set
Reserved
Size
(Bytes)
1
CSD-slice
Value
[219]
8h
1
[218]
0h
1
[217]
15h
1
[216]
Fh
4
[215:212]
15267840
SECURE_WP_INFO
1
[211]
1h
MIN_PERF_W_8_52
1
[210]
4Bh
MIN_PERF_R_8_52
1
[209]
0h
MIN_PERF_W_8_26_4_52
1
[208]
2Bh
MIN_PERF_R_8_26_4_52
1
[207]
0h
MIN_PERF_W_4_26
1
[206]
1Eh
MIN_PERF_R_4_26
1
[205]
0h
–
1
[204]
0h
PWR_CL_26_360
1
[203]
0h
PWR_CL_52_360
1
[202]
0h
PWR_CL_26_195
1
[201]
0h
PWR_CL_52_195
1
[200]
0h
PARTITION_SWITCH_TIME
OUT_OF_INTERRUPT_TIM
E
DRIVER_STRENGTH
CARD_TYPE
–
–
–
EXT_CSD_REV
1
[199]
3h
1
[198]
Ah
1
1
1
1
1
1
[197]
[196]
[195]
[194]
[193]
[192]
1Fh
57h
0h
2h
0h
8h
CMD_SET
–
1
1
[191]
[190]
0h
0h
Name
Field
Command set revision
Reserved
CMD_SET_REV
–
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Size
(Bytes)
1
1
CSD-slice
Value
[189]
[188]
0h
0h
21
IS21/22TF08G
Power class
Reserved
High-speed interface timing
Strobe support
Bus width mode
Reserved
Erased memory content
Reserved
Partition configuration
Boot config protection
Boot bus Conditions
Reserved
High-density erase group
definition
Boot write protection status
registers
Boot area write protection
register
Reserved
User area write protection
register
Reserved
FW configuration
RPMB Size
Write reliability setting register
Write reliability parameter
register
Start Sanitize operation
Manually start background
operations
Enable background operations
handshake
H/W reset function
HPI management
Partitioning Support
Max Enhanced Area Size
Partitions attribute
Partitioning Setting
POWER_CLASS
–
HS_TIMING
STROBE_SUPPORT
BUS_WIDTH
–
ERASED_MEM_CONT
–
PARTITION_CONFIG
BOOT_CONFIG_PROT
BOOT_BUS_CONDITIONS
–
1
1
1
1
1
1
1
1
1
1
1
1
[187]
[186]
[185]
[184]
[183]
[182]
[181]
[180]
[179]
[178]
[177]
[176]
0h
0h
1h (note 3)
1h
2h (note 4)
0h
0h
0h
0h
0h
0h
0h
ERASE_GROUP_DEF
1
[175]
0h
BOOT_WP_STATUS
1
[174]
0h
BOOT_WP
1
[173]
0h
–
1
[172]
0h
USER_WP
1
[171]
0h
–
FW_CONFIG
RPMB_SIZE_MULT
WR_REL_SET
1
1
1
1
[170]
[169]
[168]
[167]
1Eh
0h
20h
1Fh
WR_REL_PARAM
1
[166]
15h
SANITIZE_START
1
[165]
0h
BKOPS_START
1
[164]
0h
BKOPS_EN
1
[163]
2h
RST_n_FUNCTION
HPI_MGMT
PARTITIONING_SUPPORT
MAX_ENH_SIZE_MULT
PARTITIONS_ATTRIBUTE
PARTITION_SETTING_COM
PLETED
1
1
1
3
1
[162]
[161]
[160]
[159:157]
[156]
0h
0h
7h
3A8h
1h
1
[155]
1h
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IS21/22TF08G
Name
Field
General Purpose Partition Size
General Purpose Partition Size
General Purpose Partition Size
General Purpose Partition Size
Enhanced User Data Area Size
Enhanced User Data Start
Address
Reserved
Bad Block Management mode
GP_SIZE_MULT 4
GP_SIZE_MULT3
GP_SIZE_MULT2
GP_SIZE_MULT1
ENH_SIZE_MULT
Size
(Bytes)
3
3
3
3
3
ENH_START_ADDR
Production state awareness
Package Case Temperature is
controlled
Periodic Wake-up
Program CID/CSD in DDR mode
support
Reserved
Vendor Specific Fields
Error code
Error type
Native sector size
Sector size emulation
Sector size
1st initialization after disabling
sector size emulation
Class 6 commands control
Number of addressed group
to be Released
Exception events control
Exception events status
Extended Partitions Attribute
Context configuration
Packed command status
Packed command failure index
Power Off Notification
Control to turn the Cache
ON/OFF
Flushing of the cache
Reserved
Mode config
CSD-slice
Value
[154:152]
[151:149]
[148:146]
[145:143]
[142:140]
0h
0h
0h
0h
3A8h
4
[139:136]
0h
–
SEC_BAD_BLK_MGMNT
PRODUCTION_STATE_AWA
RENESS
1
1
[135]
[134]
0h
0h
1
[133]
0h
TCASE_SUPPORT
1
[132]
0h
PERIODIC_WAKEUP
PROGRAM_CID_CSD_DDR_
SUPPORT
–
VENDOR_SPECIFIC_FIELD
ERROR_CODE
ERROR_TYPE
NATIVE_SECTOR_SIZE
USE_NATIVE_SECTOR
DATA_SECTOR_SIZE
1
[131]
0h
1
[130]
1h
2
61
2
1
1
1
1
[129:128]
[127:67]
[66:65]
[64]
[63]
[62]
[61]
0h
–
0h
0h
0h
0h
0h
INI_TIMEOUT_EMU
1
[60]
0h
CLASS_6_CTRL
1
[59]
0h
DYNCAP_NEEDED
1
[58]
0h
2
[57:56]
0h
2
[55:54]
0h
2
[53:52]
0h
15
[51:37]
-
1
[36]
0h
1
[35]
0h
1
[34]
0h
CACHE_CTRL
1
[33]
0h
FLUSH_CACHE
Reserved
MODE_CONFIG
1
1
1
[32]
[31]
[30:30]
0h
0h
0h
EXCEPTION_EVENTS_CTR
L
EXCEPTION_EVENTS_STAT
US
EXT_PARTITIONS_ATTRIBU
TE
CONTEXT_CONF
PACKED_COMMAND_STAT
US
PACKED_FAILURE_INDEX
POWER_OFF_NOTIFICATIO
N
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23
IS21/22TF08G
Size
(Bytes)
1
2
1
4
CSDslice
[29:29]
[28:27]
[26:26]
[25:22]
4
[21:18]
4843520
1
[17:17]
1h
1
[16:16]
01h
CMQ_MODE_EN
1
[15:15]
0h
Reserved
15
[14:0]
0h
Name
Field
Mode operation codes
Reserved
FFU status
Per loading data size
MODE_OPERATION_CODES
Reserved
FFU_STATUS
PRE_LOADING_DATA_SIZE
MAX_PRE_LOADING_DATA_
SIZE
PRODUCT_STATE_AWAREN
ESS_ENABLEMENT
SECURE_REMOVAL_TYPE
Max pre loading data size
Product state awareness
enablement
Secure removal type
Command Queue Mode
enable
Reserved
Value
0h
0h
0h
0h
Notes:
1.
Reserved bits should read as “0”.
2.
Obsolete values should be don’t care.
3.
This field is 0 after power-on, H/W reset or software reset, thus selecting the backwards compatible interface timing for
the Device. If the host sets 1 to this field, the Device changes the timing to high speed interface timing (see Section
10.6.1 of JESD84-B50). If the host sets value 2, the Device changes its timing to HS200 interface timing (see Section
10.8.1 of JESD854-B50). If the host sets HS_TIMING [3:0] to 0x3, the device changes it’s timing to HS400 interface
timing (see 10.10).
4.
It is set to “0” (1bit data bus) after power up and can be changed by a SWITCH command.
5.
Could be changed by Firmware release note.
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Rev. A
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IS21/22TF08G
6. The eMMC BUS
The eMMC bus has ten communication lines and three supply lines:
• CMD： Command is a bidirectional signal. The host and Device drivers are operating in two
modes, open drain and push/pull.
• DAT0-7： Data lines are bidirectional signals. Host and Device drivers are operating in push-pull
mode
• CLK： Clock is a host to Device signal. CLK operates in push-pull mode
• Data Strobe: Data Strobe is a Device to host signal. Data Strobe operates in push-pull mode.
Figure 6.1 BUS Circuitry Diagram
The ROD is switched on and off by the host synchronously to the open-drain and push-pull mode transitions. The host
does not have to have open drain drivers, but must recognize this mode to switch on the ROD. RDAT and RCMD are pullup resistors protecting the CMD and the DAT lines against bus floating device when all device drivers are in a highimpedance mode.
A constant current source can replace the ROD by achieving a better performance (constant slopes for the signal
rising and falling edges). If the host does not allow the switchable ROD implementation, a fixed RCMD can be
used).Consequently the maximum operating frequency in the open drain mode has to be reduced if the used RCMD
value is higher than the minimal one given in.
RData strobe is pull-down resistor used in HS400 device.
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IS21/22TF08G
7. eMMC Device Overview
The eMMC device transfers data via a configurable number of data bus signals. The communication signals are:
7.1 Clock (CLK)
Each cycle of this signal directs a one-bit transfer on the command and either a one bit (1x) or a two bits transfer
(2x) on all the data lines. The frequency may vary between zero and the maximum clock frequency.
7.2 Data Strobe
This signal is generated by the device and used for output in HS400 mode. The frequency of this signal follows the
frequency of CLK. For data output each cycle of this signal directs two bits transfer(2x) on the data - one bit for
positive edge and the other bit for negative edge. For CRC status response output and CMD response output
(enabled only HS400 enhanced strobe mode), the CRC status is latched on the positive edge only, and don't care
on the negative edge.
7.3 Command (CMD)
This signal is a bidirectional command channel used for Device initialization and transfer of commands. The CMD
signal has two operation modes: open-drain for initialization mode, and push-pull for fast command transfer.
Commands are sent from the eMMC host controller to the eMMC Device and responses are sent from the Device
to the host.
7.4 Input/Outputs (DAT0-DAT7)
These are bidirectional data channels. The DAT signals operate in push-pull mode. Only the Device or the host is
driving these signals at a time. By default, after power up or reset, only DAT0 is used for data transfer. A wider data
bus can be configured for data transfer, using either DAT0-DAT3 or DAT0-DAT7, by the eMMC host controller. The
eMMC Device includes internal pull-ups for data lines DAT1-DAT7. Immediately after entering the 4-bit mode, the
Device disconnects the internal pull ups of lines DAT1, DAT2, and DAT3. Correspondingly, immediately after
entering to the 8-bit mode the Device disconnects the internal pull-ups of lines DAT1–DAT.
Table 5.1 Communication Interface
Name
CLK
DAT0
DAT1
DAT2
DAT3
DAT4
DAT5
DAT6
DAT7
CMD
RST_n
VCC
VCCQ
VSS
VSSQ
DS
Note:
1.
Type1
I
I/O/PP
I/O/PP
I/O/PP
I/O/PP
I/O/PP
I/O/PP
I/O/PP
I/O/PP
I/O/PP/OD
I
S
S
S
S
O/PP
Description
Clock
Data
Data
Data
Data
Data
Data
Data
Data
Command/Response
Hardware reset
Supply voltage for Core
Supply voltage for I/O
Supply voltage ground for Core
Supply voltage ground for I/O
Data strobe
I: input, O: output, PP: push-pull, OD: open-drain, NC: Not connected (or logical high), S: power supply.
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IS21/22TF08G
8. eMMC Functional Description
8.1 Pseudo Technology (pSLC)
Each cell in a TLC NAND can be programmed to store 3 bits of data with 8 total voltage states. In Pseudo-SLC
mode, the memory cell is used in 1-bit mode, thus resulting in higher endurance, lower error rates and extended
temperature range. The firmware optimizes the eMMC device with Pseudo technology to achieve industrial and
automotive level reliability. For ISSI eMMC device, Pseudo SLC (pSLC) mode provides one third capacity of TLC
mode.
8.2 Field Firmware Update (FFU)
Field Firmware Updates (FFU) enables features enhancement in the field. Using this mechanism, the host downloads
a new version of the firmware to the eMMC device and, following a successful download, instructs the eMMC device
to install the new downloaded firmware into the device.
In order to start the FFU process the host first checks if the eMMC device supports FFU capabilities by reading
SUPPPORTED_MODES and FW_CONFIG fields in the EXT_CSD. If the eMMC device supports the FFU feature the
host may start the FFU process. The FFU process starts by switching to FFU Mode in MODE_CONFIG field in the
EXT_CSD. In FFU Mode host should use closed-ended or open ended commands for downloading the new firmware
and reading vendor proprietary data. In this mode, the host should set the argument of these commands to be as
defined in FFU_ARG field. In case these commands have a different argument the device behavior is not defined and
the FFU process may fail. The host should set Block Length to be DATA_SECTOR_SIZE. Downloaded firmware
bundle must be DATA_SECTOR_SIZE size aligned (internal padding of the bundle might be required). Once in FFU
Mode the host may send the new firmware bundle to the device using one or more write commands.
The host could regain regular functionality of write and read commands by setting MODE_CONFIG field in the
EXT_CSD back to Normal state. Switching out of FFU Mode may abort the firmware download operation. When
host switched back to FFU Mode, the host should check the FFU Status to get indication about the number of
sectors which were downloaded successfully by reading the
NUMBER_OF_FW_SECTORS_CORRECTLY_PROGRAMMED in the extended CSD. In case the number of
sectors which were downloaded successfully is zero the host should re-start downloading the new firmware bundle
from its first sector. In case the number of sectors which were downloaded successfully is positive the host should
continue the download from the next sector, which would resume the firmware download operation.
In case MODE_OPERATION_CODES field is not supported by the device the host sets to NORMAL state and
initiates a CMD0/HW_Reset/Power cycle to install the new firmware. In such case the device doesn’t need to use
NUMBER_OF_FW_SECTORS_CORRECTLY_PROGRAMMED.
In both cases occurrence of a CMD0/HW_Reset/Power occurred before the host successfully downloaded the new
firmware bundle to the device may cause the firmware download process to be aborted
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IS21/22TF08G
8.3 Power Off Notification for Sleep
The host should notify the device before it powers the device off. This allows the device to better prepare itself for
being powered off. Power the device off means to turn off all its power supplies. In particular, the host should issue
a power off notification (POWER_OFF_LONG, POWER_OFF_SHORT) if it intends to turn off both VCC and VCCQ
power I or it may use to a power off notification (SLEEP_NOTIFICATION) if it intends to turn-off VCC after moving
the device to Sleep state.
To indicate to the device that power off notification is supported by the host, a supporting host shall first set the
POWER_OFF_NOTIFICATION byte in EXT_CSD [34] to POWERED_ON (0x01). To execute a power off, before
powering the device down the host will changes the value to either POWER_OFF_SHORT (0x02) or
POWER_OFF_LONG (0x03). Host should wait for the busy line to be de-asserted. Once the setting has changed to
either 0x02 or 0x03, host may safely power off the device.
The host may issue SLEEP_AWAKE (CMD5) to enter or to exit from Sleep state if POWER_OFF_NOTIFICATION
byte is set to POWERED_ON. Before moving to Standby state and then to Sleep state, the host sets
POWER_OFF_NOTIFICATION to SLEEP_NOTIFICATION and waits for the DAT0 line de-assertion. While in Sleep
(slp) state VCC (Memory supply) may be turned off as defined in 4.1.6. Removing power supplies other than VCC
while the device is in the Sleep (slp) state may result in undefined device behavior. Before removing all power
supplies, the host should transition the device out of Sleep (slp) state back to Transfer state using CMD5 and CMD7
and then execute a power off notification setting POWER_OFF_NOTIFICATION byte to either
POWER_OFF_SHORT or POWER_OFF_LONG.
If host continues to send commands to the device after switching to the power off setting (POWER_OFF_LONG,
POWER_OFF_SHORT or SLEEP_NOTIFICATION) or performs HPI during its busy condition, the device shall
restore the POWER_OFF_NOTIFICATION byte to POWERED_ON.
If host tries to change POWER_OFF_NOTIFICATION to 0x00 after writing another value there, a SWITCH_ERROR
is generated.
The difference between the two power-off modes is how urgent the host wants to turn power off. The device should
respond to POWER_OFF_SHORT quickly under the generic CMD6 timeout. If more time is acceptable,
POWER_OFF_LONG may be used and the device shall respond to it within the POWER_OFF_LONG_TIME timeout.
While POWER_OFF_NOTIFICATION is set to POWERED_ON, the device expects the host to host shall:
•
•
•
Keep the device power supplies alive (both VCC and VCCQ) and in their active mode
Not power off the device intentionally before changing POWER_OFF_NOTIFICATION to either
POWER_OFF_LONG or POWER_OFF_SHORT
Not power off VCC intentionally before changing POWER_OFF_NOTIFICATION to SLEEP_NOTIFICATION
and before moving the device to Sleep state
Before moving to Sleep state hosts may set the POWER_OFF_NOTIFICATION byte to SLEEP_NOTIFICATION
(0x04) if aware that the device is capable of autonomously initiating background operations for possible
performance improvements. Host should wait for the busy line to be de-asserted. Busy line may be asserted up the
period defined in SLEEP_NOTIFICATION_TIME byte in EXT_CSD [216]. Once the setting has changed to 0x04
host may set the device into Sleep mode (CMD7+CMD5). After getting out from Sleep the
POWER_OFF_NOTIFICATION byte will restore its value to POWERED_ON. HPI may interrupt the
SLEEP_NOTIFICATION operation. In that case POWER_OFF_NOTIFICATION byte will restore to
POWERED_ON.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. A
04/26/2022
28
IS21/22TF08G
8.4 Enhanced User Data Area
ISSI eMMC supports Enhanced User Data Area feature which allows the User Data Area of eMMC to be configured
as SLC Mode. Therefore, when host set the Enhanced User Data Area, the area will occupy more size of original
set up size. The Max Enhanced User Data Area size is defined as - (MAX_ENH_SIZE_MULT x
HC_WP_GRP_SIZE x HC_ERASE_GRP_SIZE x 512 KBytes). The Enhanced use data area size is defined as (ENH_SIZE_MULT x HC_WP_GRP_SIZE x HC_ERASE_GRP_SIZE x 512 KBytes). The host shall follow the flow
chart of JEDEC spec for configuring the parameters of General Purpose Area Partitions and Enhanced User Data
Area.
8.5 Write Cache
Cache is a temporary storage space in an eMMC device. The cache should in typical case reduce the access time
and increase the speed (compared to an access to the main nonvolatile storage). The cache is not directly accessible
by the host. This temporary storage space may be utilized also for some implementation specific operations like as
an execution memory for the memory controller and/or as storage for an address mapping table etc. However, there
is data inconsistence risk when using nonvolatile cache. It’s recommend only turning on the cache for the application
which requires not too high reliability.
The cache shall be OFF by default after power up, RST_n assertion or CMD0. All accesses shall be directed to the
nonvolatile storage like defined elsewhere in this specification. The cache function can be turned ON and OFF by
writing to the CACHE_CTRL byte (EXT_CSD byte [33]). Turning the cache ON shall enable behavior model defined
in this section. Turning the cache OFF shall trigger flushing of the data to the nonvolatile storages
8.6 Cache Enhancement Barrier
Barrier function provides a way to perform a delayed in-order flushing of a cached data. The main motivation for using
barrier commands is to avoid the long delay that is introduced by flush commands. There are cases where the host
is not interested in flushing the data right away, however it would like to keep an order between different cached data
batches. The barrier command enables the host achieving the in-order goal but without paying the flush delay, since
the real flushing can be delayed by the device to some later idle time. The formal definition of the barrier rule is as
follows:
Denote a sequence of requests Ri, i=0,..,N. Assuming a barrier is set between requests Rx and Rx+1 (0
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