IS24L256-2PLI

IS24L128 IS24L256 128K-bit/ 256K-bit 2-WIRE SERIAL CMOS EEPROM FEATURES • Two-Wire Serial Interface, I2CTM compatible –Bi-directional data transfer protocol • Low Voltage and Standard Voltage Operation –Vcc = 1.8V to 3.6V • 400 KHz (1.8V) and 1 MHz (2.5V, 2.7V, 3.6V) compatibility • Low Power CMOS Technology –Active Current less than 3 mA (3.6V) –Stanby Current less than 3 µA (3.6V) –Standby Current less than 1 µA (1.8V) • Hardware Data Protection –Write Protect Pin • Sequential Read Feature • Filtered Inputs for Noise Suppression • Self time write cycle with auto clear –5 ms max @ 1.8V • Organization: IS24L128–16Kx8 (256 pages of 64 bytes) IS24L256–32Kx8 (512 pages of 64 bytes) • 64 Byte Page Write Buffer • High Reliability –Endurance: 1,000,000 Cycles –Data Retention: 40 Years • Industrial temperature range • 8-pin PDIP, 8-pin (JEDEC) SOIC, and 8-pin (EIAJ) SOIC packages • Lead-free available ISSI DESCRIPTION The IS24L128 and IS24L256 are electrically erasable PROM devices that use the standard 2-wire interface for communications. The IS24L128 and IS24CL256 contain a memory array of 128K-bits (16K x 8) and 256K-bits (32 x 8), respectively. Each device is organized into 64 byte pages for page write mode. This EEPROM operates in a voltage range of 1.8V to 3.6V for low voltage and standard voltage application levels. ISSI designed this device family to be a practical, low-power 2-wire EEPROM solution. The devices are available in 8-pin PDIP, 8-pin (JEDEC) SOIC, and 8-pin (EIAJ) SOIC packages. ® ADVANCED INFORMATION APRIL 2006 The IS24L128/256 maintains compatibility with the popular 2-wire bus protocol, so it is easy to design into applications implementing this bus type. The simple bus consists of the Serial Clock wire (SCL) and the Serial Data wire (SDA). Using the bus, a Master device such as a microcontroller is usually connected to one or more Slave devices such as the IS24L128/256. The bit stream over the SDA line includes a series of bytes, which identifies a particular Slave device, an instruction, an address within that Slave device, and a series of data, if appropriate. The IS24L128/256 has a Write Protect pin (WP) to allow blocking of any write instruction transmitted over the bus. Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00B 03/21/06 1 IS24L128 IS24L256 ISSI ® FUNCTIONAL BLOCK DIAGRAM Vcc HIGH VOLTAGE GENERATOR, TIMING & CONTROL SDA WP SLAVE ADDRESS REGISTER & COMPARATOR A0 A1 A2 WORD ADDRESS COUNTER X DECODER SCL CONTROL LOGIC EEPROM ARRAY Y DECODER GND nMOS ACK Clock DI/O > DATA REGISTER 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00B 03/21/06 IS24L128 IS24L256 PIN CONFIGURATION 8-Pin DIP and SOIC ISSI ® A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA PIN DESCRIPTIONS A0-A2 SDA SCL WP Vcc NC GND Address Inputs Serial Address/Data I/O Serial Clock Input Write Protect Input Power Supply No Connect Ground SCL This input clock pin is used to synchronize the data transfer to and from the device. A0, A1, A2 The A0, A1, and A2 are the device address inputs that are hardwired or left not connected for hardware compatibility with the IS24C32/64. When pins are hardwired, as many as eight IS24L128/256 devices may be addressed on a single bus system. When the pins are not hardwired, the default values of A0, A1, and A2 are zero. SDA The SDA is a Bi-directional pin used to transfer addresses and data into and out of the device. The SDA pin is an open drain output and can be wire Or'ed with other open drain or open collector outputs. The SDA bus requires a pullup resistor to Vcc. WP WP is the Write Protect pin. If the WP pin is tied to Vcc the entire array becomes Write Protected (Read only). When WP is tied to GND or left floating, normal read/write operations are allowed to the device. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00B 03/21/06 3 IS24L128 IS24L256 DEVICE OPERATION The IS24L128/256 features a serial communication and supports a bi-directional 2-wire bus transmission protocol called I2CTM. ISSI Standby Mode ® 2-WIRE BUS The two-wire bus is defined as a Serial Data line (SDA), and a Serial Clock line (SCL). The protocol defines any device that sends data onto the SDA bus as a transmitter, and the receiving devices as receivers. The bus is controlled by Master device which generates the SCL, controls the bus access and generates the Stop and Start conditions. The IS24L128/256 is the Slave device on the bus. Power consumption is reduced in standby mode. The IS24L128/256 will enter standby mode: a) At Power-up, and remain in it until SCL or SDA toggles; b) Following the Stop signal if no write operation is initiated; or c) Following any internal write operation DEVICE ADDRESSING The Master begins a transmission by sending a Start condition. The Master then sends the address of the particular Slave devices it is requesting. The Slave device (Fig. 5) address is 8 bits. The four most significant bits of the Slave device address are fixed as 1010 for the IS24L128/256. This device has three address bits (A2, A1, and A0), which allows up to eight IS24L128/256 devices to share the 2-wire bus. Upon receiving the Slave address, the device compares the three address bits with the hardwired A2, A1, and A0 input pins to determine if it is the appropriate Slave. The last bit of the Slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master transmits the Start condition and Slave address byte (Fig. 5), the appropriate 2-wire Slave (eg. IS24L128/256) will respond with ACK on the SDA line. The Slave will pull down the SDA on the ninth clock cycle, signaling that it received the eight bits of data. The selected EEPROM then prepares for a Read or Write operation by monitoring the bus. The Bus Protocol: – Data transfer may be initiated only when the bus is not busy – During a data transfer, the SDA line must remain stable whenever the SCL line is high. Any changes in the data line while the SCL line is high will be interpreted as a Start or Stop condition. The state of the SDA line represents valid data after a Start condition. The SDA line must be stable for the duration of the High period of the clock signal. The data on the SDA line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition. Start Condition The Start condition precedes all commands to the device and is defined as a High to Low transition of SDA when SCL is High. The EEPROM monitors the SDA and SCL lines and will not respond until the Start condition is met. Stop Condition The Stop condition is defined as a Low to High transition of SDA when SCL is High. All operations must end with a Stop condition. WRITE OPERATION Byte Write In the Byte Write mode, the Master device sends the Start condition and the Slave address information (with the R/W set to Zero) to the Slave device. After the Slave generates an ACK, the Master sends the two byte address that are to be written into the address pointer of the IS24L128/256. After receiving another ACK from the Slave, the Master device transmits the data byte to be written into the address memory location. The IS24L128/256 acknowledges once more and the Master generates the Stop condition, at which time the device begins its internal programming cycle. While this internal cycle is in progress, the device will not respond to any request from the Master device. Acknowledge (ACK) After a successful data transfer, each receiving device is required to generate an ACK. The Acknowledging device pulls down the SDA line. Reset The IS24L128/256 contains a reset function in case the 2-wire bus transmission is accidentally interrupted (eg. a power loss), or needs to be terminated mid-stream. The reset is caused when the Master device creates a Start condition. To do this, it may be necessary for the Master device to monitor the SDA line while cycling the SCL up to nine times. (For each clock signal transition to High, the Master checks for a High level on SDA.) 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00B 03/21/06 IS24L128 IS24L256 Page Write The IS24L128/256 is capable of 64-byte Page-Write operation. A Page-Write is initiated in the same manner as a Byte Write, but instead of terminating the internal Write cycle after the first data word is transferred, the Master device can transmit up to 63 more bytes. After the receipt of each data word, the EEPROM responds immediately with an ACK on SDA line, and the six lower order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. If a byte address is incremented from the last byte of a page, it returns to the first byte of that page. If the Master device should transmit more than 64 words prior to issuing the Stop condition, the address counter will “roll over,” and the previously written data will be overwritten. Once all 64 bytes are received and the Stop condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the IS24L128/256 in a single Write cycle. All inputs are disabled until completion of the internal Write cycle. ISSI Random Address Read ® should generate a Stop condition so the IS24L128/256 discontinues transmission. If 'n' is the last byte of the memory, the data from location '0' will be transmitted. (Refer to Figure 8. Current Address Read Diagram.) Selective Read operations allow the Master device to select at random any memory location for a Read operation. The Master device first performs a 'dummy' Write operation by sending the Start condition, Slave address and word address of the location it wishes to read. After the IS24L128/256 acknowledges the word address, the Master device resends the Start condition and the Slave address, this time with the R/W bit set to one. The EEPROM then responds with its ACK and sends the data requested. The Master device does not send an ACK but will generate a Stop condition. (Refer to Figure 9. Random Address Read Diagram.) Sequential Read Sequential Reads can be initiated as either a Current Address Read or Random Address Read. After the IS24L128/256 sends the initial byte sequence, the Master device now responds with an ACK indicating it requires additional data from the IS24L128/256. The EEPROM continues to output data for each ACK received. The Master device terminates the sequential Read operation by pulling SDA High (no ACK) indicating the last data word to be read, followed by a Stop condition. The data output is sequential, with the data from address n followed by the data from address n+1, ... etc. The address counter increments by one automatically, allowing the entire memory contents to be serially read during sequential Read operation. When the memory address boundary 16383 for IS24L128, or 32767 for IS24L256 is reached, the address counter “rolls over” to address 0, and the device continues to output data for each ACK received. (Refer to Figure 10. Sequential Read Diagram.) Acknowledge (ACK) Polling The disabling of the inputs can be used to take advantage of the typical Write cycle time. Once the Stop condition is issued to indicate the end of the host's Write operation, the IS24L128/256 initiates the internal Write cycle. ACK polling can be initiated immediately. This involves issuing the Start condition followed by the Slave address for a Write operation. If the EEPROM is still busy with the Write operation, no ACK will be returned. If the IS24L128/256 has completed the Write operation, an ACK will be returned and the host can then proceed with the next Read or Write operation. READ OPERATION Read operations are initiated in the same manner as Write operations, except that the (R/W) bit of the Slave address is set to “1”. There are three Read operation options: current address read, random address read, and sequential read. Current Address Read The IS24L128/256 contains an internal address counter which maintains the address of the last byte accessed, incremented by one. For example, if the previous operation is either a Read or Write operation addressed to the address location n, the internal address counter would increment to address location n+1. When the EEPROM receives the Slave Device Addressing Byte with a Read operation (R/W bit set to “1”), it will respond an ACK and transmit the 8-bit data word stored at address location n+1. The Master should not acknowledge the transfer but Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00B 03/21/06 5 IS24L128 IS24L256 Figure 1. Typical System Bus Configuration Vcc ISSI SDA SCL Master Transmitter/ Receiver ® IS24L128/256 Figure 2. Output Acknowledge SCL from Master 1 8 9 Data Output from Transmitter tAA tAA Data Output from Receiver ACK Figure 3. Start and Stop Conditions STOP Condition SDA START Condition SCL 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00B 03/21/06 IS24L128 IS24L256 Figure 4. Data Validity Protocol ISSI Data Change ® SCL Data Stable Data Stable SDA Figure 5. Slave Address BIT 7 6 5 4 3 2 1 0 1 0 1 0 A2 A1 A0 R/W Figure 6. Byte Write S T A R T W R I T E S T O P A C K Device Address SDA Bus Activity M S B Word Address Word Address A A A C*† C C K K K L M S * = Don't care bit S B B † = Don't care bit for IS24L128 R/W Data Figure 7. Page Write S T A R T W R I T E S T O P A C K Device Address SDA Bus Activity Word Address (n) Word Address (n) A A A C C*† C K K K * = Don't care bit † = Don't care bit for IS24L128 Data (n) A C K Data (n+1) A C K Data (n+63) M S B L S B R/W Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00B 03/21/06 7 IS24L128 IS24L256 Figure 8. Current Address Read S T A R T SDA Bus Activity M S B L S B R/W ISSI R E A D A C K N O A C K S T O P ® Device Address Data Figure 9. Random Address Read S T A R T SDA Bus Activity M S B W R I T E S T A R T A C K Device Address Word Address (n) A C*† K A C K Word Address (n) Device Address R E A D A C K Data n S T O P L S B R/W DUMMY WRITE N O * = Don't care bit † = Don't care bit for IS24L128 A C K Figure 10. Sequential Read R E A D A C K S T O P Device Address SDA Bus Activity Data Byte n A C K Data Byte n+1 A C K Data Byte n+2 A C K Data Byte n+X N O R/W A C K 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00B 03/21/06 IS24L128 IS24L256 ABSOLUTE MAXIMUM RATINGS(1) Symbol VS VP TBIAS TSTG IOUT Parameter Supply Voltage Voltage on Any Pin Temperature Under Bias Storage Temperature Output Current Value –0.5 to +4.3 –0.1 to +5.0 –55 to +125 –65 to +150 5 Unit V V °C °C mA ISSI ® Notes: 1. Stresses violating the conditions listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only. Functional operation of the device outside these conditions or those indicated in the operational sections of this specification is not implied. Exposure to these conditions for extended periods may affect reliability. OPERATING RANGE Range Industrial Ambient Temperature –40°C to +85°C VCC 1.8V to 3.6V CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.6V. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00B 03/21/06 9 IS24L128 IS24L256 DC ELECTRICAL CHARACTERISTICS Industrial (TA = -40oC to +85oC) Symbol VOL1 VOL2 VIH V IL I LI ILO Parameter Output Low Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Test Conditions VCC = 1.8V, IOL = 0.15 mA VCC = 3.0V, IOL = 2.1 mA ISSI Min. Max. — 0.2 — 0.4 VCC X 0.7 VCC + 0.5 –0.6 VCC X 0.3 — 3 — 3 Unit V V V V µA µA ® VIN = VCC max. Notes: VIL min and VIH max are reference only and are not tested. POWER SUPPLY CHARACTERISTICS Industrial (TA = -40oC to +85oC) Symbol ICC1 ICC2 ISB1 ISB2 Parameter Vcc Operating Current Vcc Operating Current Standby Current Standby Current Test Conditions Read at 400 KHz (Vcc = 3.6V) Write at 400 KHz (Vcc = 3.6V) Vcc = 1.8V Vcc = 3.6V Min. — — — — Max. 2.0 3.0 1 3 Unit mA mA µA µA AC ELECTRICAL CHARACTERISTICS Industrial (TA = -40oC to +85oC) 1.8V ≤ Vcc < 2.5V Symbol Parameter Min. Max. fSCL SCL Clock Frequency 0 400 T Noise Suppression Time(1) — 50 tLow Clock Low Period 1.2 — tHigh Clock High Period 0.6 — tBUF Bus Free Time Before New Transmission(1) 1.2 — tSU:STA Start Condition Setup Time 0.6 — tSU:STO Stop Condition Setup Time 0.6 — tHD:STA Start Condition Hold Time 0.6 — tHD:STO Stop Condition Hold Time 0.6 — tSU:DAT Data In Setup Time 100 — tHD:DAT Data In Hold Time 0 — tSU:WP WP pin Setup Time 0.6 — tHD:WP WP pin Hold Time 1.2 — tDH Data Out Hold Time (SCL Low to SDA Data Out Change) 50 — tAA Clock to Output (SCL Low to SDA Data Out Valid) 50 900 tR SCL and SDA Rise Time(1) — 300 tF SCL and SDA Fall Time(1) — 300 tWR Write Cycle Time — 5 Notes: 1. This parameter is characterized but not 100% tested. 2.5V ≤ Vcc ≤ 3.6V Min. Max. 0 1000 — 50 0.6 — 0.4 — 0.5 — 0.25 — 0.25 — 0.25 — 0.25 — 100 — 0 — 0.6 — 1.2 — 50 — 50 400 — 300 — 100 — 5 Unit KHz ns µs µs µs µs µs µs µs ns ns µs µs ns ns ns ns ms 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00B 03/21/06 IS24L128 IS24L256 AC WAVEFORMS Figure 11. Bus Timing ISSI ® tR tF tHIGH tLOW tSU:STO SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tBUF SDAIN tAA tDH SDAOUT tSU:WP tHD:WP WP Figure 12. Write Cycle Timing SCL SDA 8th BIT WORD n ACK tWR STOP Condition START Condition Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00B 03/21/06 11 IS24L128 IS24L256 ISSI ® ORDERING INFORMATION: IS24L256 Industrial Range: -40°C to +85°C Voltage Range 1.8V to 3.6V Part Number IS24L256-2PI IS24L256-2PLI IS24L256-2GI IS24L256-2GLI IS24L256-2WI IS24L256-2WLI Package 300-mil Plastic DIP (8-pin) 300-mil Plastic DIP (8-pin), Lead-free Small Outline (JEDEC STD) (8-pin) Small Outline (JEDEC STD) (8-pin), Lead-free Small Outline (EIAJ STD) (8-pin) Small Outline (EIAJ STD) (8-pin), Lead-free ORDERING INFORMATION: IS24L128 Industrial Range: -40°C to +85°C Voltage Range 1.8V to 3.6V Part Number IS24L128-2PI IS24L128-2PLI IS24L128-2GI IS24L128-2GLI IS24L128-2WI IS24L128-2WLI Package 300-mil Plastic DIP (8-pin) 300-mil Plastic DIP (8-pin), Lead-free Small Outline (JEDEC STD) (8-pin) Small Outline (JEDEC STD) (8-pin), Lead-free Small Outline (EIAJ STD) (8-pin) Small Outline (EIAJ STD) (8-pin), Lead-free 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00B 03/21/06 PACKAGING INFORMATION 300-mil Plastic DIP Package Code: N,P ISSI E1 ® N 1 D SEATING PLANE B1 S S A E L FOR 32-PIN ONLY A1 e B B2 C eA MILLIMETERS Sym. N0. Leads A A1 B B1 B2 C D E E1 eA e L S INCHES Min. Max. Min. 8 Max. Notes: 1. Controlling dimension: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. 3.68 0.38 0.36 1.14 0.81 0.20 9.12 7.62 6.20 8.13 4.57 — 0.56 1.52 1.17 0.33 9.53 8.26 6.60 9.65 — 0.762 0.145 0.015 0.014 0.045 0.032 0.008 0.359 0.300 0.244 0.320 0.180 — 0.022 0.060 0.046 0.013 0.375 0.325 0.260 0.380 — 0.030 2.54 BSC 3.18 0.64 0.100 BSC 0.125 0.025 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 02/14/03 PACKAGING INFORMATION 150-mil Plastic SOP Package Code: G, GR ISSI ® N E H 1 D SEATING PLANE A A1 e B L α C Symbol Ref. Std. No. Leads A A1 B C D E H e L 150-mil Plastic SOP (G, GR) Min Max Min Max Inches mm 8 8 — 0.068 — 1.73 0.004 0.009 0.1 0.23 0.013 0.020 0.33 0.51 0.007 0.010 0.18 0.25 0.189 0.197 4.8 5 0.150 0.157 3.81 3.99 0.228 0.245 5.79 6.22 0.050 BSC 1.27 BSC 0.020 0.035 0.51 0.89 Notes: 1. Controlling dimension: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 10/03/01 2 PACKAGING INFORMATION 200-mil Plastic SOP Package Code: W ISSI ® N E H 1 D SEATING PLANE A A1 e B L α C Notes: 1. Controlling dimension: mm, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 200-mil Plastic SOP (W) Symbol Ref. Std. No. Leads A A1 B C D E H e L Min Max Min mm 8 — 2.16 0.10 0.23 0.35 0.45 0.15 0.35 5.15 5.35 5.18 5.40 7.70 8.26 1.27 BSC 0.51 0.85 Max Inches 8 — 0.085 0.004 0.009 0.014 0.018 0.006 0.014 0.203 0.211 0.204 0.213 0.303 0.325 0.050 BSC 0.020 0.033 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 10/20/05 2