IS25C64A-3GLA1

IS25C32A IS25C64A 32K-BIT/64K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM AUGUST 2007 FEATURES • Serial Peripheral Interface (SPI) Compatible — Supports SPI Modes 0 (0,0) and 3 (1,1) • Wide-voltage Operation — Vcc = 1.8V to 5.5V • Low power CMOS — Active current less than 3.0 mA (2.5V) — Standby current less than 2.0 µA (2.5V) • Block Write Protection — Protect 1/4, 1/2, or Entire Array • 32 byte page write mode — Partial page writes allowed • 10 MHz Clock Rate (5V) • Self timed write cycles (5 ms Typical) • High-reliability — Endurance: 1 million cycles per byte — Data retention: 100 years • Industrial and Automotive temperature ranges • 8-pin PDIP, 8-pin SOIC, and 8-pin TSSOP Packages available • Lead-free available DESCRIPTION The IS25C32A and IS25C64A are electrically erasable PROM devices that use the Serial Peripheral Interface (SPI) for communications. The IS25C32A is 32Kbit (4096 x 8) and the IS25C64A is 64Kbit (8192 x 8). The IS25C32A/64A EEPROMs are offered in a wide operating voltage range of 1.8V to 5.5V to be compatible with most application voltages. ISSI designed the IS25C32A/64A to be an efficient SPI EEPROM solution. The devices are packaged in 8-pin PDIP, 8-pin SOIC, and 8-pin TSSOP. The functional features of the IS25C32A/64A allow them to be among the most advanced serial non-volatile memories available. Each device has a Chip-Select (CS) pin, and a 3-wire interface of Serial Data In (SI), Serial Data Out (SO), and Serial Clock (SCK). While the 3-wire interface of the IS25C32A/64A provides for high-speed access, a HOLD pin allows the memories to ignore the interface in a suspended state; later the HOLD pin re-activates communication without reinitializing the serial sequence. A Status Register facilitates a flexible write protection mechanism, and a device-ready bit (RDY). Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. Rev. A 08/14/07 1 IS25C32A IS25C64A PIN CONFIGURATION 8-Pin DIP, SOIC, and TSSOP PIN CONFIGURATION 8-Pin Rotated TSSOP CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI HOLD VCC CS SO 1 2 3 4 8 7 6 5 SCK SI GND WP PIN DESCRIPTIONS CS SCK SI SO GND VCC WP HOLD Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Write Protect Suspends Serial Input Chip Select (CS): The CS pin activates the device. Upon power-up, CS should follow Vcc. When the device is to be enabled for instruction input, the signal requires a High-to-Low transition. While CS is stable Low, the master and slave will communicate via SCK, SI, and SO signals. Upon completion of communication, CS must be driven High. At this moment, the slave device may start its internal write cycle. When CS is high, the device enters a power-saving standby mode, unless an internal write operation is underway. During this mode, the SO pin becomes high impedance. Write Protect (WP): The purpose of this input signal is to initiate Hardware Write Protection mode. This mode prevents the Block Protection bits and the WPEN bit in the Status Register from being altered. To cause Hardware Write Protection, WP must be Low at the same time WPEN is 1. WP may be hardwired to Vcc or GND. HOLD (HOLD): This input signal is used to suspend the device in the middle of a serial sequence and temporarily ignore further communication on the bus (SI, SO, SCK). Together with Chip Select, the HOLD signal allows multiple slaves to share the bus. The HOLD signal transitions must occur only when SCK is Low, and be held stable during SCK transitions. (See Figure 8 for Hold timing) To disable this feature, HOLD may be hardwired to Vcc. PIN DESCRIPTIONS Serial Clock (SCK): This timing signal provides synchronization between the microcontroller and IS25C32A/64A. Op-Codes, byte addresses, and data are latched on SI with a rising edge of the SCK. Data on SO is refreshed on the falling edge of SCK for SPI modes (0,0) and (1,1). Serial Data Input (SI): This is the input pin for all data that the IS25C32A/64A is required to receive. Serial Data Output (SO): This is the output pin for all data transmitted from the IS25C32A/64A. 2 Integrated Silicon Solution, Inc. Rev. A 08/14/07 IS25C32A IS25C64A SERIAL INTERFACE DESCRIPTION MASTER: The device that provides a clock signal. SLAVE: The IS25C32A/64A is a slave because the clock signal is an input. TRANSMITTER/RECEIVER: The IS25C32A/64A has both data input (SI) and data output (SO). MSB: The most significant bit. It is always the first bit transmitted or received. OP-CODE: The first byte transmitted to the slave following CS transition to LOW. If the OP-CODE is a valid member of the IS25C32A/64A instruction set (Table 3), then it is decoded appropriately. If the OP-CODE is not valid, and the SO pin remains in high impedance. BLOCK DIAGRAM VCC GND STATUS REGISTER 8192 x 8/4096 x 8 MEMORY ARRAY DATA REGISTER SI MODE DECODE LOGIC ADDRESS DECODER OUTPUT BUFFER CS WP SCK CLOCK SO HOLD Integrated Silicon Solution, Inc. Rev. A 08/14/07 3 IS25C32A IS25C64A STATUS REGISTER The status register contains 8-bits for write protection control and write status. (See Table 1). It is the only region of memory other than the main array that is accessible by the user. Block Protect (BP1, BP0), Bits 2-3: Together, these bits represent one of four block protection configurations implemented for the memory array. (See Table 2 for details.) BP0 and BP1 are non-volatile cells similar to regular array cells, and factory programmed to 0. The block of memory defined by these bits is always protected, regardless of the setting of WPEN, WP , or WEN. Table 1. Status Register Format Bit 7 WPEN Bit 6 Bit 5 Bit 4 X X X Bit 3 Bit 2 Bit1 Bit 0 BP1 BP0 WEN RDY Notes: 1. X = Don't care bit. 2. During internal write cycles, bits 0 to 7 are temporarily 1's. Table 2. Block Protection Status Register Bits Level 0 1(1/4) 2(1/2) 3(All) BP1 0 0 1 1 BP0 0 1 0 1 The Status Register is Read-Only if either: a) Hardware Write Protection is enabled or b) WEN is set to 0. If neither is true, it can be modified by a valid instruction. Ready (RDY), Bit 0: When RDY = 1, it indicates that the device is busy with a write cycle. RDY = 0 indicates that the device is ready for an instruction. If RDY = 1, the only command that will be handled by the device is Read Status Register. Write Enable (WEN), Bit 1: This bit represents the status of device write protection. If WEN = 0, the Status Register and the entire array is protected from modification, regardless of the setting of WPEN, WP pin, or block protection. The only way to set WEN to 1 is via the Write Enable command (WREN). WEN is reset to 0 upon power-up. Array Addresses Protected IS25C32A None 0C00h -0FFFh 0800h -0FFFh 0000h -0FFFh IS25C64A None 1800h -1FFFh 1000h -1FFFh 0000h -1FFFh Don’t Care, Bits 4-6: Each of these bits can receive either 0 or 1, but values will not be retained. When these bits are read from the register, they are always 0. Write Protect Enable (WPEN), Bit 7: This bit can be used in conjunction with WP pin to enable Hardware Write Protection, which causes the Status Register to be read-only. The memory array is not protected by this mode. Hardware Write Protection requires that WP = 0 and WPEN = 1; it is disabled otherwise. Note: WPEN cannot be changed from 1 to 0 if the WP pin is already set to Low. (See Table 4 for data protection relationship) 4 Integrated Silicon Solution, Inc. Rev. A 08/14/07 IS25C32A IS25C64A DEVICE OPERATION The operations of the IS25C32A/64A are controlled by a set of instructions that are clocked-in serially SI pin. (See Table 3). To begin an instruction, the chip select (CS) should be dropped Low. Subsequently, each Low-to-High transition of the clock (SK) will latch a stable value on the SI pin. After the 8-bit op-code, it may be appropriate to continue to input an address or data to SI, or to output data from SO. During data output, values appear on the falling edge of SK. All bits are transferred with MSB first. Upon the last bit of communication, but prior to any following Lowto-High transition of SK, CS should be raised High to end the transaction. The device then would enter Standby Mode if no internal programming were underway. Table 3. Instruction Set Name WREN WRDI RDSR WRSR READ WRITE Op-code 0000 X110 0000 X100 0000 X101 0000 X001 0000 X011 0000 X010 Operation Set Write Enable Latch Reset Write Enable Latch Read Status Register Write Status Register Read Data from Array Write Data to Array Address A15-A0 A15-A0 Data(SI) D7-D0 D7-D0,... Data (SO) D7-D0,... D7-D0,... - 1. X = Don’t care bit. For consistency, it is best to use “0”. 2. Some address bits are don’t care. See Table 5. 3. If the bits clocked-in for an op-code are invalid, SO remains high impedance, and upon CS going High there is no affect. A valid op-code with an invalid number of bits clocked-in for address or data will cause an attempt to modify the array or Status Register to be ignored. WRITE ENABLE (WREN) When Vcc is initially applied, the device powers up with both status register and entire array in a write-disabled state. Upon completion of Write Disable (WRDI), Write Status Register (WRSR), or Write Data to Array (WRITE), the device resets the WEN bit in the Status Register to 0. Prior to any data modification, a WREN instruction is necessary to set WEN to 1. (See Figure 2 for timing). WRITE DISABLE (WRDI) The device can be completely protected from modification by resetting WEN to 0 through the WRDI instruction. (See Figure 3 for timing). READ STATUS REGISTER (RDSR) The Read Status instruction tells the user the status of Write Protect Enable, the Block Protection setting (see Table 2), the Write Enable state, and the RDY status. RDSR is the only instruction accepted when a write cycle is underway. It is recommended that the status of Write Enable and RDY be checked, especially prior to an attempted modification of data. The 8 bits of the Status Register can be repeatedly output on SO after the initial Op-code. (See Figure 4 for timing). Integrated Silicon Solution, Inc. Rev. A 08/14/07 5 IS25C32A IS25C64A WRITE STATUS REGISTER (WRSR) This instruction lets the user choose a Block Protection setting, and set or reset the WPEN bit. The values of the other data bits incorporated into WRSR can be 0 or 1, and are not stored in the Status Register. WRSR will be ignored unless both the following are true: a) WEN = 1, due to a prior WREN instruction; and b) Hardware Write Protection is not enabled. (See Table 4 for details). Except for the RDY status, the values in the Status Register remain unchanged until the moment when the write cycle is complete and the register is updated. Note: WPEN can be changed from 1 to 0 only if WP is already set High. Once completed, WEN is reset for complete chip write protection. (See Figure 5 for timing). READ DATA (READ) This instruction begins with the op-code and the 16-bit address, and causes the selected data byte to be shifted out on SO. Following this first data byte, additional sequential bytes are output. If the data byte in the highest address is output, the address rolls-over to the lowest address in the array, and the output could loop indefinitely. At any time, a rising CS signal completes the operation. (See Figure 6 for timing). WRITE DATA (WRITE) The WRITE instruction begins with the op-code, the 16bit address of the first byte to be modified, and the first data byte. Additional data bytes may be written sequentially to the array after the first byte. Each WRITE instruction can affect the contents of a 32 byte page, but no more. The page begins at address XXXXXXXX XXX00000, and ends with XXXXXXXX XXX11111. If the last byte of the page is input, the address rolls over to the beginning of the same page. More than 32 data bytes can be input during the same instruction, but upon a completed write cycle, a page would only contain the last 32 bytes. The region of the array defined within Block Protection cannot be modified as long as that block configuration is selected. The region of the array outside the Block Protection can only be modified if Write Enable (WEN) is set to 1. Therefore, it may be necessary that a WREN instruction occur prior to WRITE. Hardware Write Protection has no affect on the memory array. Once Write is completed, WEN is reset for complete chip write protection. (See Figure 7 for timing). Table 5. Address Key Name AN Don't Care Bits IS25C32A A11-A0 A15-A12 IS25C64A A12-A0 A15-A13 Table 4. Write Protection WPEN 0 0 1 1 X X WP X X 0 0 1 1 Hardware Write Protection Not Enabled Not Enabled Enabled Enabled Not Enabled Not Enabled WEN 0 1 0 1 0 1 Inside Block Read-only Read-only Read-only Read-only Read-only Read-only Outside Block Read-only Unprotected Read-only Unprotected Read-only Unprotected Status Register (WPEN, BP1, BP0) Read-only Unprotected Read-only Read-only Read-only Unprotected Note: X = Don't care bit. 6 Integrated Silicon Solution, Inc. Rev. A 08/14/07 IS25C32A IS25C64A ABSOLUTE MAXIMUM RATINGS (1) Symbol VS VP TBIAS TSTG IOUT Parameter Supply Voltage Voltage on Any Pin Temperature Under Bias Storage Temperature Output Current Value -0.5 to + 6.5 –0.5 to Vcc + 0.5 –55 to +125 –65 to +150 5 Unit V V °C °C mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE (IS25C64A-2 and IS25C32A-2) Range Industrial Ambient Temperature –40°C to +85°C VCC 1.8V to 5.5V Note: ISSI offers Industrial grade for commerical applications (0oC to +70oC). OPERATING RANGE (IS25C64A-3 and IS25C32A-3) Range Automotive Ambient Temperature –40°C to +85°C VCC 2.5V to 5.5V CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters and not 100% tested. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V. Integrated Silicon Solution, Inc. Rev. A 08/14/07 7 IS25C32A IS25C64A DC ELECTRICAL CHARACTERISTICS TA = –40°C to +85°C for Industrial, TA = –40°C to +85°C for Automotive. Symbol Parameter VOL1 VOL2 VOL3 VOH1 VOH2 VOH3 VIH VIL ILI ILO Output LOW Voltage Output LOW Voltage Output LOW Voltage Output HIGH Voltage Output HIGH Voltage Output HIGH Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VIN = 0V TO VCC VOUT = 0V TO VCC, CS = VCC Test Conditions VCC = 5V, IOL = 2 mA VCC = 2.5V, IOL = 1.5 mA VCC = 1.8V, IOL = 0.15 mA VCC = 5V, IOH = -2 mA VCC = 2.5V, IOH = -0.4mA VCC = 1.8V, IOH = -0.1mA Min. — — — 0.8 X VCC 0.8 X VCC 0.8 X VCC 0.7X VCC -0.3 -2 -2 Max. 0.4 0.4 0.2 — — — VCC + 1 0.3 X VCC 2 2 Unit V V V V V V V V µA µA POWER SUPPLY CHARACTERISTICS TA = –40°C to +85°C for Industrial. Symbol Parameter ICC1 ICC2 ICC3 ISB1 ISB2 ISB3 Vcc Operating Current Vcc Operating Current Vcc Operating Current Standby Current Standby Current Standby Current Test Conditions Read/Write at 10 MHz (Vcc = 5V) Read/Write at 5 MHz (Vcc = 2.5V) Read/Write at 2 MHz (Vcc = 1.8V) Vcc = 5.0V, VIN = VCC or GND CS = Vcc Vcc = 2.5V, VIN = VCC or GND CS = Vcc Vcc = 1.8V, VIN = VCC or GND CS = Vcc Min. — — — — — — Max. 5.0 3.0 1.0 3.0 2.0 1.0 Unit mA mA mA µA µA µA POWER SUPPLY CHARACTERISTICS TA = –40°C to +85°C for Automotive. Symbol Parameter ICC1 ICC2 ISB1 ISB2 Vcc Operating Current Vcc Operating Current Standby Current Standby Current Test Conditions Read/Write at 5 MHz (Vcc = 5V) Read/Write at 5 MHz (Vcc = 2.5V) Vcc = 5.0V, VIN = VCC or GND CS = Vcc Vcc =2.5V, VIN = VCC or GND CS = Vcc Min. — — — — Max. 4.0 3.0 8.0 5.0 Unit mA mA µA µA 8 Integrated Silicon Solution, Inc. Rev. A 08/14/07 IS25C32A IS25C64A AC Characteristics TA = –40°C to +85°C for Industrial. 1.8V ≤ Vcc < 2.5V 2.5V ≤ Vcc < 4.5V 4.5V ≤ Vcc ≤ 5.5V Symbol fSCK tRI tFI tWH tWL tCS tCSS tCSH tSU tH tHD tCD tV tHO tLZ tHZ tDIS tWC CL = 100pF Parameter SCK Clock Frequency Input Rise Time Input Fall Time SCK High Time SCK Low Time CS High Time CS Setup Time CS Hold Time Data In Setup Time Data In Hold Time Hold Setup Time Hold Hold Time Output Valid Output Hold Time Hold to Output Low Z Hold to Output High Z Output Disable Time Write Cycle Time Min 0 — — 200 200 200 200 200 40 50 100 100 0 0 0 — — — Max 2 2 2 — — — — — — — — — 150 — 100 250 250 10 Min 0 — — 90 90 100 90 90 20 30 50 50 0 0 0 — — — Max 5 2 2 — — — — — — — — — 60 — 50 100 100 5 Min 0 — — 40 40 40 40 25 15 15 25 25 0 0 0 — — — Max 10 2 2 — — — — — — — — — 25 — 25 25 25 5 Units MHz µs µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms Integrated Silicon Solution, Inc. Rev. A 08/14/07 9 IS25C32A IS25C64A AC Characteristics TA = –40°C to +85°C for Automotive. 2.5V ≤ Vcc < 4.5V 4.5V ≤ Vcc ≤ 5.5V Symbol fSCK t RI t FI t WH tWL tCS tCSS tCSH tSU tH tHD tCD tV tHO tLZ tHZ tDIS tWC CL = 100pF Parameter SCK Clock Frequency Input Rise Time Input Fall Time SCK High Time SCK Low Time CS High Time CS Setup Time CS Hold Time Data In Setup Time Data In Hold Time Hold Setup Time Hold Hold Time Output Valid Output Hold Time Hold to Output Low Z Hold to Output High Z Output Disable Time Write Cycle Time Min 0 — — 90 90 100 90 90 20 30 50 50 0 0 0 — — — Max 5 2 2 — — — — — — — — — 60 — 50 100 100 5 Min 0 — — 40 40 40 40 25 15 15 25 25 0 0 0 — — — Max 10 2 2 — — — — — — — — — 25 — 25 25 25 5 Units MHz µs µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 10 Integrated Silicon Solution, Inc. Rev. A 08/14/07 IS25C32A IS25C64A TIMING DIAGRAMS Figure 1. Synchronous Data Timing CS VIH VIL tCSS tCSH tWH tSU tH tWL tCS SK VIH VIL VIH VIL DIN VALID IN tV tHO tDIS HIGH-Z DOUT VOH VOL HIGH-Z Figure 2. WREN Timing CS SK DIN WREN OP-CODE HIGH-Z DOUT Figure 3. WRDI Timing CS SK DIN WRDI OP-CODE HIGH-Z DOUT Integrated Silicon Solution, Inc. Rev. A 08/14/07 11 IS25C32A IS25C64A Figure 4. RDSR Timing CS SK Instruction DATA OUT 76543210 Din Dout Figure 5. WRSR Timing CS SK Instruction DATA IN 7654321 Din 0 Dout Figure 6. READ Timing CS SK Instruction Din BYTE Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA OUT 76543210 Integrated Silicon Solution, Inc. Rev. A 08/14/07 Dout 12 IS25C32A IS25C64A Figure 7. WRITE Timing CS SK Instruction Din BYTE Address DATA IN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Dout Figure 8. HOLD Timing HOLD CS tCD SCK tHD HOLD tHZ DOUT tLZ tHD tCD Integrated Silicon Solution, Inc. Rev. A 08/14/07 13 IS25C32A IS25C64A ORDERING INFORMATION Industrial Range: –40°C to +85°C Voltage Range 1.8V to 5.5V 1.8V to 5.5V Part Number IS25C32A-2PI IS25C32A-2GI IS25C32A-2ZI IS25C64A-2PI IS25C64A-2GI IS25C64A-2ZI Package 300-mil Plastic DIP Small Outline (JEDEC STD) 8-pin TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) 8-pin TSSOP Industrial Range: –40°C to +85°C, Lead-free Voltage Range 1.8V to 5.5V Part Number IS25C32A-2PLI IS25C32A-2GLI IS25C32A-2ZLI IS25C32A-2ZRLI IS25C64A-2PLI IS25C64A-2GLI IS25C64A-2ZLI IS25C64A-2ZRLI Package 300-mil Plastic DIP Small Outline (JEDEC STD) 8-pin TSSOP 8-pin TSSOP, rotated 300-mil Plastic DIP Small Outline (JEDEC STD) 8-pin TSSOP 8-pin TSSOP, rotated 1.8V to 5.5V Automotive Range: -40°C to +85°C, Lead-free Voltage Range 2.5V to 5.5V 2.5V to 5.5V Part Number IS25C32A-3PLA1 IS25C32A-3GLA1 IS25C32A-3ZLA1 IS25C64A-3PLA1 IS25C64A-3GLA1 IS25C64A-3ZLA1 Package 300-mil Plastic DIP Small Outline (JEDEC STD) 8-pin TSSOP 300-mil Plastic DIP Small Outline (JEDEC STD) 8-pin TSSOP 14 Integrated Silicon Solution, Inc. Rev. A 08/14/07 PACKAGING INFORMATION 300-mil Plastic DIP Package Code: N,P N E1 1 D SEATING PLANE B1 S S A E L FOR 32-PIN ONLY A1 e B B2 C eA MILLIMETERS Sym. N0. Leads A A1 B B1 B2 C D E E1 eA e L S INCHES Min. Max. Min. 8 Max. Notes: 1. Controlling dimension: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. 3.68 0.38 0.36 1.14 0.81 0.20 9.12 7.62 6.20 8.13 3.18 0.64 4.57 — 0.56 1.52 1.17 0.33 9.53 8.26 6.60 9.65 — 0.762 0.145 0.015 0.014 0.045 0.032 0.008 0.359 0.300 0.244 0.320 0.125 0.025 0.180 — 0.022 0.060 0.046 0.013 0.375 0.325 0.260 0.380 — 0.030 2.54 BSC 0.100 BSC Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 02/14/03 PACKAGING INFORMATION 300-mil Plastic DIP Package Code: N,P MILLIMETERS Sym. N0. Leads A A1 B B1 B2 C D E E1 eA e L S — INCHES Min. Max. Sym. N0. Leads MILLIMETERS Min. 20 INCHES Min. Max. Min. 16 Max. Max. 3.68 0.25 4.57 — 0.46 BSC 1.52 BSC — 0.38 0.145 0.180 0.010 — 0.018 BSC 0.060 BSC — — 0.015 A A1 B B1 B2 C D E E1 eA e L S 3.68 0.38 0.36 1.14 — 4.57 — 0.56 1.78 — 0.36 0.145 0.015 0.014 0.045 — 0.180 — 0.022 0.070 — 0.014 0.13 18.92 7.44 6.22 8.13 3.05 0.38 19.18 8.13 6.48 9.65 3.56 0.89 0.005 0.745 0.293 0.245 0.320 0.120 0.015 0.755 0.320 0.255 0.380 0.140 0.035 0.20 25.91 7.49 6.01 — 3.05 1.02 26.42 8.26 7.11 10.92 0.008 1.020 0.295 0.240 — 0.120 0.040 1.040 0.325 0.280 0.430 2.54 BSC 0.100 BSC 2.54 BSC 3.81 1.52 0.100 BSC 0.150 0.060 MILLIMETERS Sym. N0. Leads A A1 B B1 B2 C D E E1 eA e L S INCHES Min. Max. Sym. N0. Leads MILLIMETERS Min. 32 INCHES Min. Max. Min. 28 Max. Max. 3.68 0.25 0.41 1.27 4.57 — 0.56 1.78 0.81 0.20 35.05 7.49 6.99 7.87 3.05 0.51 1.17 0.38 35.56 8.00 7.49 10.16 3.81 1.06 0.145 0.010 0.016 0.050 0.032 0.008 1.380 0.295 0.275 0.310 0.120 0.020 0.180 — A A1 B B1 B2 C D E E1 eA e L S 0.022 0.070 0.046 0.015 3.56 0.38 0.38 1.02 — 4.57 — 0.53 1.78 — 0.38 0.140 0.015 0.015 0.040 — 0.180 — 0.021 0.070 — 0.015 1.400 0.315 0.295 0.400 0.150 0.042 0.13 40.51 7.75 7.24 8.38 3.05 1.65 40.77 8.26 7.22 9.40 3.81 2.16 0.005 1.595 0.305 0.285 0.33 0.120 0.065 1.605 0.325 0.292 0.370 0.150 0.085 2.54 BSC 0.100 BSC 2.54 BSC 0.100 BSC 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 02/14/03 PACKAGING INFORMATION 150-mil Plastic SOP Package Code: G, GR N E H 1 D SEATING PLANE A A1 e B L α C Symbol Ref. Std. No. Leads A A1 B C D E H e L 150-mil Plastic SOP (G, GR) Min Max Min Max Inches mm 8 8 — 0.068 — 1.73 0.004 0.009 0.1 0.23 0.013 0.020 0.33 0.51 0.007 0.010 0.18 0.25 0.189 0.197 4.8 5 0.150 0.157 3.81 3.99 0.228 0.245 5.79 6.22 0.050 BSC 1.27 BSC 0.020 0.035 0.51 0.89 Notes: 1. Controlling dimension: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 10/03/01 2 PACKAGING INFORMATION Thin Shrink Small Outline TSSOP Package Code: Z (8 pin, 14 pin) N E1 E 1 D N/2 A1 α L A2 A C e B TSSOP (Z) Ref. Std. JEDEC MO-153 No. Leads 8 Millimeters Inches Symbol Min Max Min Max A — 1.20 — 0.047 A1 0.05 0.15 0.002 0.006 A2 0.80 1.05 0.032 0.041 B 0.19 0.30 0.007 0.012 C 0.09 0.20 0.004 0.008 D 2.90 3.10 0.114 0.122 E1 4.30 4.50 0.169 0.177 E 6.40 BSC 0.252 BSC e 0.65 BSC 0.026 BSC L 0.45 0.75 0.018 0.030 α — 8° — 8° TSSOP (Z) Ref. Std. JEDEC MO-153 No. Leads 14 Millimeters Inches Symbol Min Max Min Max A — 1.20 — 0.047 A1 0.05 0.15 0.002 0.006 A2 0.80 1.05 0.031 0.041 B 0.19 0.30 0.007 0.012 C 0.09 0.20 0.0035 0.008 D 4.90 5.10 0.193 0.201 E1 4.30 4.50 0.170 0.177 E 6.40 BSC 0.252 BSC e 0.65 BSC 0.026 BSC L 0.45 0.75 0.0177 0.0295 α — 8° — 8° SSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2002, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. Rev B 02/01/02