IS25CD010-JDLE-TR

IS25CD512/010 & IS25LD020 512Kbit/1 Mbit / 2 Mbit Single Operating Voltage Serial Flash Memory With 100 MHz Dual-Output SPI Bus Interface Output SPI Bus Interface FEATURES • Low Power Consumption Memory With 100 MHz Dual• Single Power Operation - Typical 10Memory mA active read current Output SPISupply Bus Interface With 100 MHz Dual- Low voltage range: 2.70 V – 3.60 V (512Kbit / 1Mbit) - Typical 15 mA program/erase current Output SPI Bus Interface 2.30 V – 3.60 V (2Mbit) • Memory Organization - IS25CD512: 64K x 8 (512 Kbit) - IS25CD010: 128K x 8 (1 Mbit) - IS25LD020: 256K x 8 (2 Mbit) • Cost Effective Sector/Block Architecture - 512Kb : Uniform 4KByte sectors / Two uniform 32KByte blocks - 1Mb : Uniform 4KByte sectors / Four uniform 32KByte blocks - 2Mb : Uniform 4KByte sectors / Four uniform 64KByte blocks • Low standby current 1uA (Typ) • Serial Peripheral Interface (SPI) Compatible - Supports single- or dual-output - Supports SPI Modes 0 and 3 - Maximum 33 MHz clock rate for normal read - Maximum 100 MHz clock rate for fast read • Page Program (up to 256 Bytes) Operation - Typical 2 ms per page program • Sector, Block or Chip Erase Operation - Maximum 10 ms sector, block or chip erase • Hardware Write Protection - Protect and unprotect the device from write operation by Write Protect (WP#) Pin • Software Write Protection - The Block Protect (BP2, BP1, BP0) bits allow partial or entire memory to be configured as read-only • High Product Endurance - Guaranteed 200,000 program/erase cycles per single sector - Minimum 20 years data retention • Industrial Standard Pin-out and Package - 8-pin SOIC 150mil - 8-pin VVSOP 150mil (2Mb) - 8-pin USON (2x3 mm) (512Kb) - 8-pin WSON (5x6 mm) - 8-pin TSSOP - KGD (Call Factory) - Lead-free (Pb-free) package - Automotive Temperature Ranges Available • Security function - Built in Safe Guard function and sector unlock function to make the flash Robust (Appendix1&2) GENERAL DESCRIPTION The IS25CD512/010 and IS25LD020 are 512Kbit/ 1Mbit / 2Mbit Serial Peripheral Interface (SPI) Flash memories, providing single- or dual-output. The devices are designed to support a 33 MHz clock rate in normal read mode, and 100 MHz in fast read, the fastest in the industry. The devices use a single low voltage power supply, wide operating voltage ranging to perform read, erase and program operations. The devices can be programmed in standard EPROM programmers. The IS25CD512/010 and IS25LD020 are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output (SlO), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. They comply with all recognized command codes and operations. The dual-output fast read operation provides and effective serial data rate of 200MHz. The devices support page program mode, where 1 to 256 bytes data can be programmed into the memory in one program operation. These devices are divided into uniform 4 KByte sectors or uniform 32 KByte blocks.(IS25LD020 is uniform 4 KByte sectors or uniform 64 KByte). The IS25CD512/010 and IS25LD020 are manufactured on pFLASH™’s advanced non-volatile technology. The devices are offered in a variety of packages for all critical needs. The devices operate at wide temperatures between -40°C to +105°C. Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 1 IS25CD512/010 & IS25LD020 CONNECTION DIAGRAMS CE# 1 8 SO 2 7 WP# GND Vcc HOLD# 3 6 SCK 4 5 SIO CE# 1 8 Vcc SO 2 7 HOLD# WP# 3 6 SCK GND 4 5 SIO 8-pin WSON 8-Pin SOIC/VVSOP CE# SO WP# GND 1 2 3 4 8 7 6 5 Vcc HOLD# SCK SIO 8-Pin TSSOP CE# Vcc HOLD# SO WP# SCK GND SIO 8-Pin USON PIN DESCRIPTIONS SYMBOL TYPE DESCRIPTION CE# INPUT SCK SIO SO GND Vcc WP# INPUT INPUT/OUTPUT OUTPUT HOLD# INPUT Chip Enable: CE# low activates the devices internal circuitries for device operation. CE# high deselects the devices and switches into standby mode to reduce the power consumption. When a device is not selected, data will not be accepted via the serial input pin (SlO), and the serial output pin (SO) will remain in a high impedance state. Serial Data Clock Serial Data Input/Output Serial Data Output Ground Device Power Supply Write Protect: A hardware program/erase protection for all or part of a memory array. When the WP# pin is low, memory array write-protection depends on the setting of BP2, BP1 and BP0 bits in the Status Register. When the WP# is high, the devices are not write-protected. Hold: Pause serial communication by the master device without resetting the serial sequence. INPUT Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 2 IS25CD512/010 & IS25LD020 BLOCK DIAGRAM SIO Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 3 IS25CD512/010 & IS25LD020 SPI MODES DESCRIPTION Multiple IS25CD512/010 and IS25LD020 devices can be connected on the SPI serial bus and controlled by a SPI Master, i.e. microcontroller, as shown in Figure 1. The devices support either of two SPI modes: Mode 0 (0, 0) Mode 3 (1, 1) The difference between these two modes is the clock polarity when the SPI master is in Stand-by mode: the serial clock remains at “0” (SCK = 0) for Mode 0 and the clock remains at “1” (SCK = 1) for Mode 3. Please refer to Figure 2. For both modes, the input data is latched on the rising edge of Serial Clock (SCK), and the output data is available from the falling edge of SCK. Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices) SDIO SPI Interface with (0,0) or (1,1) SDI SCK SCK SPI Master (i.e. Microcontroller) CS3 CS2 SO SIO SCK SPI Memory Device CS1 CE# WP# SO SIO SCK CE# WP# CE# HOLD# SIO SPI Memory Device SPI Memory Device HOLD# SO WP# HOLD# Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as appropriate. Figure 2. SPI Modes Supported SCK Mode 0 (0, 0) SCK Mode 3 (1, 1) SIO MSb Input mode SO Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 MSb 4 IS25CD512/010 & IS25LD020 SYSTEM CONFIGURATION The IS25CD512/010 and IS25LD020 devices are designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of the Motorola MC68HCxx series of microcontrollers or any SPI interface-equipped system controllers. The devices have two superset features that can be enabled through specific software instructions and the Configuration Register: Memory Density Block No. Block Size Sector Size Sector No. (Kbytes) (Kbytes) Address Range Sector 0(1) 4 000000h - 000FFFh Sector 1 4 001000h - 001FFFh : : : Sector 7 4 007000h - 007FFFh Sector 8 4 008000h - 008FFFh Sector 9 4 009000h - 009FFFh : : 000000h - 006FFFh Sector 15 4 00F000h - 00FFFFh Block 0 32 512 Kbit 1 Mbit Block 1 Memory Density 32 Block 2 32 " " 010000h - 017FFFh Block 3 32 " " 018000h - 01FFFFh Block No. Block 0 Block Size (KBytes) 64 2 Mbit Block 1 : Block 3 64 : 64 Sector 0 Sector Size (KBytes) 4 000000h - 000FFFh Sector 1 : 4 : 001000h - 001FFFh : Sector 15 4 00F000h - 00FFFFh Sector 16 4 010000h - 010FFFh Sector 17 : 4 : 011000h - 011FFFh Sector 31 : : 4 : 4 01F000h - 01FFFFh : 030000h – 03FFFFh Sector No. Address Range : Table 1-1. Block/Sector Addresses of IS25CD512/010 and IS25LD020 Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 5 IS25CD512/010 & IS25LD020 REGISTERS (CONTINUED) STATUS REGISTER Refer to Tables 5 and 6 for Status Register Format and Status Register Bit Definitions. a Write Enable (WREN) instruction. Each write register, program and erase instruction must be preceded by a WREN instruction. The WEL bit can be reset by a Write Disable (WRDI) instruction. It will automatically be the reset after the completion of a write instruction. The BP0, BP1, BP2, and SRWD are volatile memory cells that can be written by a Write Status Register (WRSR) instruction. The default value of the BP2, BP1, BP0 were set to “0” and SRWD bits was set to “0” at factory. Once a “0” or “1”is written, it will not be changed by device power-up or power-down, and can only be altered by the next WRSR instruction. The Status Register can be read by the Read Status Register (RDSR). Refer to Table 10 for Instruction Set. BP2, BP1, BP0 bits: The Block Protection (BP2, BP1, BP0) bits are used to define the portion of the memory area to be protected. Refer to Tables 7, 8 and 9 for the Block Write Protection bit settings. When a defined combination of BP2, BP1 and BP0 bits are set, the corresponding memory area is protected. Any program or erase operation to that area will be inhibited. Note: a Chip Erase (CHIP_ER) instruction is executed successfully only if all the Block Protection Bits are set as “0”s. The function of Status Register bits are described as follows: WIP bit: The Write In Progress (WIP) bit is read-only, and can be used to detect the progress or completion of a program or erase operation. When the WIP bit is “0”, the device is ready for a write status register, program or erase operation. When the WIP bit is “1”, the device is busy. SRWD bit: The Status Register Write Disable (SRWD) bit operates in conjunction with the Write Protection (WP#) signal to provide a Hardware Protection Mode. When the SRWD is set to “0”, the Status Register is not write-protected. When the SRWD is set to “1” and the WP# is pulled low WEL bit: The Write Enable Latch (WEL) bit indicates the (VIL), the volatile bits of Status Register (SRWD, BP2, BP1, status of the internal write enable latch. When the WEL is “0”, BP0) become read-only, and a WRSR instruction will be the write enable latch is disabled, and all write operations, ignored. If the SRWD is set to “1” and WP# is pulled high including write status register, page program, sector erase, (VIH), the Status Register can be changed by a WRSR block and chip erase operations are inhibited. When the WEL instruction. bit is “1”, write operations are allowed. The WEL bit is set by Table 5. Status Register Format Bit 7 Default (flash bit) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SRWD1 Bit 6 Reserved Bit 5 BP2 BP1 BP0 WEL WIP 0 0 0 0 0 0 0 Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 6 IS25CD512/010 & IS25LD020 REGISTERS (CONTINUED) Table 6. Status Register Bit Definition Bit Name Bit 0 WIP Bit 1 WEL Bit 2 Bit 3 Bit 4 Bits 5 - 6 BP0 BP1 BP2 N/A Bit 7 SRWD Definition Write In Progress Bit: "0" indicates the device is ready "1" indicates a write cycle is in progress and the device is busy Write Enable Latch: "0" indicates the device is not write enabled "1" indicates the device is write enabled (default) Block Protection Bit: (See Table 7 and Table 8 for details) "0" indicates the specific blocks are not write-protected (default) "1" indicates the specific blocks are write-protected Reserved: Always "0"s Status Register Write Disable: (See Table 9 for details) "0" indicates the Status Register is not write-protected (default) "1" indicates the Status Register is write-protected Read/Write Non-Volatile bit R No R/W No R/W Yes N/A R/W Yes Table 8. Block Write Protect Bits for IS25CD512/010 and IS25LD020 Status Register Bits Protected Memory Area BP1 BP0 IS25CD512 IS25CD010 IS25LD020 0 0 None None None 0 1 None Upper quarter (Block 3) 01800h-01FFFFh Upper quarter (Block 3) 03000h-03FFFFh 1 0 None Upper half (Block 2 & 3) 010000h-01FFFFh Upper half (Block 2 & 3) 020000h-03FFFFh 1 1 All Blocks 000000h-00FFFFh All Blocks 000000h-01FFFFh All Blocks 000000h-03FFFFh Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 7 IS25CD512/010 & IS25LD020 REGISTERS (CONTINUED) PROTECTION MODE The IS25CD512/010 and IS25LD020 have two types of write- Table 9. Hardware Write Protection on Status protection mechanisms: hardware and software. These are Register used to prevent irrelevant operation in a possibly noisy environment and protect the data integrity. SRWD WP# Status Register HARDWARE WRITE-PROTECTION The devices provide two hardware write-protection features: 0 Low Writable 1 Low Protected 0 High Writable 1 High Writable a. When inputting a program, erase or write status register instruction, the number of clock pulse is checked to determine whether it is a multiple of eight before the executing. Any incomplete instruction command sequence will be ignored. b. The Write Protection (WP#) pin provides a hardware write protection method for BP2, BP1, BP0 and SRWD in the Status Register. Refer to the STATUS REGISTER description. c. All write sequences will be ignored when Vcc drop to VWI (see p.26) SOFTWARE WRITE PROTECTION The IS25CD512/010 and IS25LD020 also provides two software write protection features: a. Before the execution of any program, erase or write status register instruction, the Write Enable Latch (WEL) bit must be enabled by executing a Write Enable (WREN) instruction. If the WEL bit is not enabled first, the program, erase or write register instruction will be ignored. b. The Block Protection (BP2, BP1, BP0) bits allow part or the whole memory area to be write-protected. Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 8 IS25CD512/010 & IS25LD020 DEVICE OPERATION The IS25CD512/010 and IS25LD020 utilize an 8-bit instruction register. Refer to Table 10 Instruction Set for details of the Instructions and Instruction Codes. All instructions, addresses, and data are shifted in with the most significant bit (MSB) first on Serial Data Input (SI). The input data on SI is latched on the rising edge of Serial Clock (SCK) after Chip Enable (CE#) is driven low (VIL). Every instruction sequence starts with a one-byte instruction code and is followed by address bytes, data bytes, or both address bytes and data bytes, depending on the type of instruction. CE# must be driven high (VIH) after the last bit of the instruction sequence has been shifted in. The timing for each instruction is illustrated in the following operational descriptions. Table 10. Instruction Set Instruction Name Hex Code RDID JEDEC ID READ ABh 9Fh RDMDID WREN WRDI RDSR WRSR READ FAST_READ FRDO PAGE_ PROG 90h 06h 04h 05h 01h 03h 0Bh 3Bh 02h SECTOR_ER BLOCK_ER CHIP_ER D7h/20h D8h C7h/60h Operation Read Manufacturer and Product ID Read Manufacturer and Product ID by JEDEC ID Command Read Manufacturer and Device ID Write Enable Write Disable Read Status Register Write Status Register Read Data Bytes from Memory at Normal Read Mode Read Data Bytes from Memory at Fast Read Mode Fast Read Dual Output Page Program Data Bytes Into Memory Sector Erase Block Erase Chip Erase Command Cycle 4 Bytes 1 Byte Maximum Frequency 100 MHz 100 MHz 4 Bytes 1 Byte 1 Byte 1 Byte 2 Bytes 4 Bytes 5 Bytes 5 Bytes 4 Bytes + 256B 4 Bytes 4 Bytes 1 Byte 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 33 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz HOLD OPERATION HOLD# is used in conjunction with CE# to select the IS25CD512/010 and IS25LD020. When the devices are selected and a serial sequence is underway, HOLD# can be used to pause the serial communication with the master device without resetting the serial sequence. To Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 pause, HOLD# is brought low while the SCK signal is low. To resume serial communication, HOLD# is brought high while the SCK signal is low (SCK may still toggle during HOLD). Inputs to SlO will be ignored while SO is in the high impedance state. 9 IS25CD512/010 & IS25LD020 DEVICE OPERATION (CONTINUED) RDID COMMAND (READ PRODUCT IDENTIFICATION) OPERATION The Read Product Identification (RDID) instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not same as RDID or JEDEC ID instruction. It’s not recommended to use for new design. For new design, please use RDID or JEDEC ID instruction. The RDES instruction code is followed by three dummy bytes, each bit being latched-in on SI during the rising edge of SCK. Then the Device ID is shifted out on SO with the MSB first, each bit been shifted out during the falling edge of SCK. The RDES instruction is ended by CE# goes high. The Device ID outputs repeatedly if continuously send the additional clock cycles on SCK while CE# is at low. Table 11. Product Identification Product Identification Manufacturer ID Device ID: Data First Byte 9Dh Second Byte 7Fh Device ID 1 Device ID 2 IS25CD512 05h 20h IS25CD010 10h 21h IS25LD020 11h 22h Figure 3. Read Product Identification Sequence CE# 0 1 7 8 9 38 31 46 39 47 54 SCK INSTRUCTION SI SO 3 Dummy Bytes 1010 1011b HIGH IMPEDANCE Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 Device ID1 Device ID1 Device ID1 10 IS25CD512/010 & IS25LD020 DEVICE OPERATION (CONTINUED) JEDEC ID READ COMMAND (READ PRODUCT IDENTIFICATION BY JEDEC ID) OPERATION The JEDEC ID READ instruction allows the user to read the manufacturer and product ID of devices. Refer to Table 11 Product Identification for pFlash Manufacturer ID and Device ID. After the JEDEC ID READ command is input, the second Manufacturer ID (7Fh) is shifted out on SO with the MSB first, followed by the first Manufacturer ID (9Dh) and the Device ID (22h, in the case of the IS25LD020), each bit shifted out during the falling edge of SCK. If CE# stays low after the last bit of the Device ID is shifted out, the Manufacturer ID and Device ID will loop until CE# is pulled high. Figure 4. Read Product Identification by JEDEC ID READ Sequence CE# 0 15 16 7 8 23 24 31 SCK INSTRUCTION SI SO 1001 1111b HIGH IMPEDANCE Manufacture ID2 Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 Manufacture ID1 Device ID2 11 IS25CD512/010 & IS25LD020 DEVICE OPERATION (CONTINUED) RDMDID COMMAND (READ DEVICE MANUFACTURER AND DEVICE ID) OPERATION The RDMDID instruction allows the user to read the manufacturer and product ID of devices. Refer to Table 11 Product Identification for pFlash Manufacturer ID and Device ID. The RDMDID command is input, followed by a 24-bit address pointing to an ID table. The table contains the first Manufacturer ID (9Dh) and the Device ID (22h, in the case of the IS25LD020), and is shifted out on SO with the MSB first, each bit shifted out during the falling edge of SCK. If CE# stays low after the last bit of the Device ID is shifted out, the Manufacturer ID and Device ID will loop until CE# is pulled high. Figure 5. Read Product Identification by RDMDID READ Sequence CE# 0 1 2 3 4 5 6 7 8 9 10 11 SCK 28 29 30 31 1 A0 ... 3 - BYTE ADDRESS SIO INSTRUCTION = 1001 0000b 23 22 43 ... 3 21 2 HIGH IMPEDANCE SO CE# 32 33 34 35 36 37 38 39 40 41 42 7 6 5 44 45 46 47 2 1 0 SCK SIO Manufacturer ID1 SO 7 6 5 4 3 Device ID1 2 1 Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 0 4 3 12 IS25CD512/010 & IS25LD020 CE# 48 49 50 51 52 53 54 55 3 2 1 0 56 SCK SIO Manufacturer ID2 SO 7 6 5 4 Note : (1) ADDRESS A0 = 0, will output the 1st manufacture ID (9Dh) first -> device ID1 -> 2nd manufacture ID (7Fh) ADDRESS A0 = 1, will output the device ID1 -> 1st manufacture ID (9D) -> 2nd manufacture ID (7Fh) Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 13 IS25CD512/010 & IS25LD020 DEVICE OPERATION (CONTINUED) WRITE ENABLE OPERATION The Write Enable (WREN) instruction is used to set the Write Enable Latch (WEL) bit. The WEL bit of the IS25CD512/010 and IS25LD020 is reset to the write – protected state after power-up. The WEL bit must be write enabled before any write operation, including sector, block erase, chip erase, page program and write status register operations. The WEL bit will be reset to the write-protect state automatically upon completion of a write operation. The WREN instruction is required before any above operation is executed. Figure 6. Write Enable Sequence SIO WRDI COMMAND (WRITE DISABLE) OPERATION The Write Disable (WRDI) instruction resets the WEL bit and disables all write instructions. The WRDI instruction is not required after the execution of a write instruction, since the WEL bit is automatically reset. Figure 7. Write Disable Sequence SIO Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 14 IS25CD512/010 & IS25LD020 DEVICE OPERATION (CONTINUED) RDSR COMMAND (READ STATUS REGISTER) OPERATION The Read Status Register (RDSR) instruction provides access to the Status Register. During the execution of a program, erase or write status register operation, all other instructions will be ignored except the RDSR instruction, which can be used to check the progress or completion of an operation by reading the WIP bit of Status Register. Figure 8. Read Status Register Sequence SIO WRSR COMMAND (WRITE STATUS REGISTER) OPERATION The Write Status Register (WRSR) instruction allows the user to enable or disable the block protection and status register write protection features by writing “0”s or “1” s into the volatile BP2, BP1, BP0 and SRWD bits. Figure 9. Write Status Register Sequence SIO Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 15 IS25CD512/010 & IS25LD020 DEVICE OPERATION (CONTINUED) READ COMMAND (READ DATA) OPERATION The Read Data (READ) instruction is used to read memory data of a IS25CD512/010 and IS25LD020 under normal mode running up to 33 MHz. The READ instruction code is transmitted via the SlO line, followed by three address bytes (A23 - A0) of the first memory location to be read. A total of 24 address bits are shifted in, but only AMS (most significant address) - A0 are decoded. The remaining bits (A23 – AMS) are ignored. The first byte addressed can be at any memory location. Upon completion, any data on the Sl will be ignored. Refer to Table 12 for the related Address Key. The first byte data (D7 - D0) addressed is then shifted out on the SO line, MSb first. A single byte of data, or up to the whole memory array, can be read out in one READ instruction. The address is automatically incremented after each byte of data is shifted out. The read operation can be terminated at any time by driving CE# high (VIH) after the data comes out. When the highest address of the devices is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read in one continuous READ instruction. Table 12. Address Key Address IS25LD020 IS25CD010 IS25CD512 AN (AMS – A0) A17 - A0 A16 - A0 A15 - A0 Don't Care Bits A23 – A18 A23 – A17 A23 – A16 Figure 12. Read Data Sequence SIO Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 16 IS25CD512/010 & IS25LD020 DEVICE OPERATION (CONTINUED) FAST_READ COMMAND (FAST READ DATA) OPERATION The FAST_READ instruction is used to read memory data at up to a 100 MHz clock. The FAST_READ instruction code is followed by three address bytes (A23 - A0) and a dummy byte (8 clocks), transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out on the SO line, with each bit shifted out at a maximum frequency fCT, during the falling edge of SCK. The first byte addressed can be at any memory location. The address is automatically incremented after each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single FAST_READ instruction. The FAST_READ instruction is terminated by driving CE# high (VIH). Figure 13. Fast Read Data Sequence SIO SIO Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 17 IS25CD512/010 & IS25LD020 DEVICE OPERATION (CONTINUED) FRDO COMMAND (FAST READ DUAL OUTPUT) OPERATION The FRDO instruction is used to read memory data on two output pins each at up to a 100 MHz clock. The first bit (MSb) is output on SO, while simultaneously the second bit is output on SIO. The FRDO instruction code is followed by three address bytes (A23 - A0) and a dummy byte (8 clocks), transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out on the SO and SIO lines, with each pair of bits shifted out at a maximum frequency fCT, during the falling edge of SCK. The first byte addressed can be at any memory location. The address is automatically incremented after each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single FRDO instruction. FRDO instruction is terminated by driving CE# high (VIH). Figure 14. Fast Read Dual-Output Sequence CE# 0 1 2 3 4 5 6 7 8 9 10 11 SCK 28 30 31 2 1 0 29 ... 3 - BYTE ADDRESS SIO INSTRUCTION = 0011 1011b 23 22 21 ... 3 HIGH IMPEDANCE SO CE# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 6 4 2 0 6 4 2 0 6 1 7 SCK SIO DATA OUT 1 SO HIGH IMPEDANCE Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 7 5 3 DATA OUT 2 1 7 5 3 18 IS25CD512/010 & IS25LD020 DEVICE OPERATION (CONTINUED) PAGE_PROG COMMAND (PAGE PROGRAM) OPERATION The Page Program (PAGE_PROG) instruction allows up to 256 bytes data to be programmed into memory in a single operation. The destination of the memory to be programmed must be outside the protected memory area set by the Block Protection (BP2, BP1, BP0) bits. A PAGE_PROG instruction which attempts to program into a page that is write-protected will be ignored. Before the execution of PAGE_PROG instruction, the Write Enable Latch (WEL) must be enabled through a Write Enable (WREN) instruction. The PAGE_PROG instruction code, three address bytes and program data (1 to 256 bytes) are input via the SlO line. Program operation will start immediately after the CE# is brought high, otherwise the PAGE_PROG instruction will not be executed. The internal control logic automatically handles the programming voltages and timing. During a program operation, all instructions will be ignored except the RDSR instruction. The progress or completion of the program operation can be determined by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the program operation is still in progress. If WIP bit is “0”, the program operation has completed. If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the previously latched data are discarded, and the last 256 bytes data are kept to be programmed into the page. The starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s. A byte cannot be reprogrammed without first erasing the whole sector or block. Figure 15. Page Program Sequence SIO Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 19 IS25CD512/010 & IS25LD020 DEVICE OPERATION (CONTINUED) ERASE OPERATION The memory array of the IS25CD512/010 is organized into uniform 4 KByte sectors or 32 KByte uniform blocks (a block consists of eight adjacent sectors). IS25LD020 is organized into uniform 4 KByte sectors or 64 KByte uniform blocks (a block consists of sixteen adjacent sectors) Before a byte can be reprogrammed, the sector or block that contains the byte must be erased (erasing sets bits to “1”). In order to erase the devices, there are three erase instructions available: Sector Erase (SECTOR_ER), Block Erase (BLOCK_ER) and Chip Erase (CHIP_ER). A sector erase operation allows any individual sector to be erased without affecting the data in other sectors. A block erase operation erases any individual block. A chip erase operation erases the whole memory array of a device. A sector erase, block erase or chip erase operation can be executed prior to any programming operation. SECTOR_ER COMMAND (SECTOR ERASE) OPERATION A SECTOR_ER instruction erases a 4 KByte sector Before the execution of a SECTOR_ER instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is reset automatically after the completion of sector an erase operation. progress or completion of the erase operation can be determined by reading the WIP bit in the Status Register using a RDSR instruction. If the WIP bit is “1”, the erase operation is still in progress. If the WIP bit is “0”, the erase operation has been completed. BLOCK_ER COMMAND (BLOCK ERASE) OPERATION A Block Erase (BLOCK_ER) instruction erases a 64 KByte block of the IS25LD020, and 32 KByte block of the IS25CD512C/010C. Before the execution of a BLOCK_ER instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically after the completion of a block erase operation. The BLOCK_ER instruction code and three address bytes are input via SI. Erase operation will start immediately after the CE# is pulled high, otherwise the BLOCK_ER instruction will not be executed. The internal control logic automatically handles the erase voltage and timing. Refer to Figure 15 for Block Erase Sequence. CHIP_ER COMMAND (CHIP ERASE) OPERATION A Chip Erase (CHIP_ER) instruction erases the entire memory array of a IS25CD512/010 and IS25LD020. Before the execution of CHIP_ER instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. A SECTOR_ER instruction is entered, after CE# is pulled low The WEL is reset automatically after completion of a chip to select the device and stays low during the entire erase operation. instruction sequence The SECTOR_ER instruction code, and three address bytes are input via SI. Erase operation will The CHIP_ER instruction code is input via the SI. Erase start immediately after CE# is pulled high. The internal operation will start immediately after CE# is pulled high, control logic automatically handles the erase voltage and otherwise the CHIP_ER instruction will not be executed. The timing. Refer to Figure 14 for Sector Erase Sequence. internal control logic automatically handles the erase voltage and timing. Refer to Figure 16 for Chip Erase Sequence. During an erase operation, all instruction will be ignored except the Read Status Register (RDSR) instruction. The Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 20 IS25CD512/010 & IS25LD020 DEVICE OPERATION (CONTINUED) Figure 16. Sector Erase Sequence SIO Figure 17. Block Erase Sequence SIO Figure 18. Chip Erase Sequence SIO Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 21 IS25CD512/010 & IS25LD020 ABSOLUTE MAXIMUM RATINGS (1) -65oC to +125oC -65oC to +125oC 240oC 3 Seconds 260oC 3 Seconds -0.5 V to VCC + 0.5 V -0.5 V to VCC + 0.5 V -0.5 V to +6.0 V Temperature Under Bias Storage Temperature Standard Package Lead-free Package Input Voltage with Respect to Ground on All Pins (2) All Output Voltage with Respect to Ground VCC (2) Notes: 1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. The functional operation of the device conditions that exceed those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condition for extended periods may affect device reliability. Surface Mount Lead Soldering Temperature 2. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may overshoot VCC by + 2.0 V for a period of time not to exceed 20 ns. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may undershoot GND by -2.0 V for a period of time not to exceed 20 ns. DC AND AC OPERATING RANGE Part Number IS25CD512/010 IS25LD020 -40oC to 105oC -40oC to 85oC -40oC to 105oC 2.70 V – 3.60 V Operating Temperature (Extended Grade) Operating Temperature (Automotive, A1 Grade) Operating Temperature (Automotive, A2 Grade) Vcc Power Supply DC CHARACTERISTICS Applicable over recommended operating range from: VCC = 2.70 V to 3.60 V (unless otherwise noted). Symbol Parameter ICC1 Vcc Active Read Current ICC2 Vcc Program/Erase Current ISB1 Vcc Standby Current CMOS Condition VCC = 3.60V at 33 MHz, SO = Open VCC = 3.60V at 33 MHz, SO = Open VCC = 3.60V, CE# = VCC ISB2 Vcc Standby Current TTL VCC = 3.60V, CE# = VIH to VCC 3 mA ILI Input Leakage Current VIN = 0V to VCC 1 µA 1 µA o Min o VIN = 0V to VCC, TAC = 0 C to 85 C Typ Max Units 10 15 mA 15 30 mA 10 µA ILO Output Leakage Current VIL Input Low Voltage -0.5 0.8 V VIH Input HIgh Voltage 0.7VCC VCC + 0.3 V VOL Output Low Voltage 0.45 V VOH Output High Voltage 2.30V < VCC < 3.60V Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 IOL = 2.1 mA IOH = -100 µA VCC - 0.2 V 22 IS25CD512/010 & IS25LD020 AC CHARACTERISTICS Applicable over recommended operating range from, VCC = 2.70 V to 3.60 V CL = 1 TTL Gate and 10 pF (unless otherwise noted). Symbol Parameter fCT Clock Frequency for fast read mode fC Clock Frequency for read mode tRI Max Units 0 100 MHz 0 33 MHz Input Rise Time 8 ns tFI Input Fall Time 8 ns tCKH SCK High Time 4 ns tCKL SCK Low Time 4 ns tCEH CE# High Time 25 ns tCS CE# Setup Time 10 ns tCH CE# Hold Time 5 ns tDS Data In Setup Time 2 ns tDH Data in Hold Time 2 ns tHS Hold Setup Time 15 ns tHD Hold Time 15 ns tV Output Valid tOH Output Hold Time Normal Mode tLZ Hold to Output Low Z 200 ns tHZ Hold to Output High Z 200 ns tDIS Output Disable Time 100 ns tEC Sector/Block/Chip Erase Time 10 ms tPP Page Program Time 5 ms tVCS VCC Set-up Time tw Write Status Register time (flash bit) Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 Min Typ 8 0 ns ns 2 50 µs 10 ms 23 IS25CD512/010 & IS25LD020 AC CHARACTERISTICS (CONTINUED) SERIAL INPUT/OUTPUT TIMING (1) SIO Note: 1. For SPI Mode 0 (0,0) Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 24 IS25CD512/010 & IS25LD020 AC CHARACTERISTICS (CONTINUED) HOLD TIMING PIN CAPACITANCE (f = 1 MHz, T = 25°C ) Typ Max Units Conditions CIN 4 6 pF VIN = 0 V COUT 8 12 pF VOUT = 0 V Note: These parameters are characterized but not 100% tested. OUTPUT TEST LOAD Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL 25 IS25CD512/010 & IS25LD020 POWER-UP AND POWER-DOWN At Power-up and Power-down, the device must not be selected (CE# must follow the voltage applied on Vcc) until Vcc reaches the correct value: - Vcc(min) at Power-up, and then for a further delay of tVCE - Vss at Power-down Usually a simple pull-up resistor on CE# can be used to insure safe and proper Power-up and Power-down. To avoid data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while Vcc is less than the POR threshold value (Vwi) during power up, the device does not respond to any instruction until a time delay of tPUW has elapsed after the moment that Vcc rised above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, Vcc is still below Vcc(min). No Write Status Register, Program or Erase instructions should be sent until the later of: - tPUW after Vcc passed the VWI threshold - tVCE after Vcc passed the Vcc(min) level At Power-up, the device is in the following state: - The device is in the Standby mode - The Write Enable Latch (WEL) bit is reset At Power-down, when Vcc drops from the operating voltage, to below the Vwi, all write operations are disabled and the device does not respond to any write instruction. Vcc Vcc(max) All Write Commands are Rejected Chip Selection Not Allowed Vcc(min) Reset State V (write inhibit) tVCE Read Access Allowed Device fully accessible tPUW Time Symbol tVCE*1 tPUW*1 VWI*1 Parameter Vcc(min) to CE# Low Min. 10 Max. Unit µs Power-Up time delay to Write instruction IS25CD512/010 IS25LD020 1 1.6 1.9 10 2.1 2.4 ms V Note: *1. These parameters are characterized only. Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 26 IS25CD512/010 & IS25LD020 PROGRAM/ERASE PERFORMANCE Parameter Unit Sector Erase Time Block Erase Time Typ Max Remarks ms 10 From writing erase command to erase completion ms 10 From writing erase command to erase completion Chip Erase Time ms 10 From writing erase command to erase completion Page Programming Time ms 5 From writing program command to program completion 2 Note: These parameters are characterized and are not 100% tested. RELIABILITY CHARACTERISTICS Parameter Min Unit Endurance 200,000 Cycles JEDEC Standard A117 Data Retention ESD – Human Body Model ESD – Machine Model Latch-Up Test Method 20 Years JEDEC Standard A103 2,000 Volts JEDEC Standard A114 200 Volts JEDEC Standard A115 100 + ICC1 mA JEDEC Standard 78 Note: These parameters are characterized and are not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 27 IS25CD512/010 & IS25LD020 PACKAGE TYPE INFORMATION JN 8-Pin SOIC 150mil Broad Small Outline Integrated Circuit Package (Unit: millimeters) Note: Package dimensions are shown in mm. Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 28 IS25CD512/010 & IS25LD020 PACKAGE TYPE INFORMATION (CONTINUED) JD 8-pin TSSOP Package (Unit: millimeters) Pin1 6.2 6.6 4.3 4.5 0.127 Detail A 2.9 3.1 1.00 1.05 1.05 1.20 Detail A 0.25 0.30 GAGE PLANE 0.05 0.15 0.25 0.65 0.5 0.7 00 80 Unit : millimeters Note: Package dimensions are shown in mm. Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 29 IS25CD512/010 & IS25LD020 PACKAGE TYPE INFORMATION (CONTINUED) JK 8-pin Ultra-Thin Small Outline No-Lead (WSON) Package (Unit: millimeters) Note: Package dimensions are shown in mm. Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 30 IS25CD512/010 & IS25LD020 PACKAGE TYPE INFORMATION (CONTINUED) JV 8-pin VVSOP Package 150mil (Unit: millimeters) Note: Package dimensions are shown in mm. Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 31 IS25CD512/010 & IS25LD020 Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 32 IS25CD512/010 & IS25LD020 PACKAGE TYPE INFORMATION (CONTINUED) JU 8-pin USON Package (Unit: millimeters) Note: Package dimensions are shown in mm. Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 33 IS25CD512/010 & IS25LD020 Appendix1: Safe Guard function Safe Guard function is a security function for customer to protect by sector (4Kbyte). Every sector has one bit register to decide it will under safe guard protect or not. (“0”means protect and “1” means not protect by safe guard.) IS25CD512 (sector 0~sector 15), IS25CD010 (sector 0~sector 31) and IS25LD020 (sector 0~sector 63) *safe guard function priority is higher than status register (BP0/1/2) Mapping table for safe guard register Sector0 Sector1 Sector2 Sector3 Sector4 Sector5 Sector6 Sector7 Sector8 Sector9 Sector10 Sector11 Sector12 Sector13 Sector14 Sector15 Address[9:0] 000h 000h 000h 000h 000h 000h 000h 000h 001h 001h 001h 001h 001h 001h 001h 001h D7 D6 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 D5 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 D4 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 D3 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 D1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 … … 1 1 1 0 1 1 1 1 0 D0 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 … … … … … … … … … … … … … … … … … … Sector56 007h 1 1 1 1 Sector57 007h 1 1 1 1 Sector58 007h 1 1 1 1 Sector59 007h 1 1 1 1 Sector60 007h 1 1 1 0 Sector61 007h 1 1 0 1 Sector62 007h 1 0 1 1 Sector63 007h 0 1 1 1 Chip Erase disable* 008h 0 0 0 0 Note:1. Please set the Chip Erase disable to "0" after finished the register setting. 2. Please set the address 009h to "00" after finished the register setting. Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 D2 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 34 IS25CD512/010 & IS25LD020 Read Safe Guard register The READ Safe Guard instruction code is transmitted via the SlO line, followed by three address bytes (A23 - A0) of the first register location to be read. The first byte data (D7 - D0) addressed is then shifted out on the SO line, MSb first. The address is automatically incremented after each byte of data is shifted out. The read operation can be terminated at any time by driving CE# high (VIH) after the data comes out. CS 1 2 7 8 9 10 23 24 25 26 31 32 33 34 39 40 41 42 47 48 SCK SI 2Fh A23-A0 SO 1st byte 2nd byte D7-D0 D7-D0 Fig a. Timing waveform of Read Safe guard register Erase Safe Guard register If we want to erase the safe guard register to let the flash into unprotect status, it needs five continuous instructions. If any instruction is wrong, the erase command will be ignored. Erase wait time follow product erase timing spec. Fig b. shows the complete steps for Erase safe guard register. Program Safe Guard register If we want to erase the safe guard register to let the flash into unprotect status, it needs five continuous instructions. If any instruction is wrong, the program command will be ignored. The Program safe guard instruction allows up to 256 bytes data to be programmed into memory in a single operation. Program wait time follow product program timing spec. Fig c. shows the complete steps for program safe guard register. Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 35 IS25CD512/010 & IS25LD020 Sector Protection Mode Erase CS 1 2 7 8 9 10 31 32 SCK SI 55h A23-A0 CS 1 2 7 8 9 10 31 32 SCK SI AAh A23-A0 CS 1 2 7 8 9 10 31 32 SCK SI 80h A23-A0 CS 1 2 7 8 9 10 31 32 SCK SI AAh A23-A0 CS 1 2 7 8 SCK SI 2Bh Fig b. Erase safe guard register Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 36 IS25CD512/010 & IS25LD020 CS 1 2 7 8 9 10 31 32 SCK SI 55h A23-A0 CS 1 2 7 8 9 10 31 32 SCK SI AAh A23-A0 CS 1 2 7 8 9 10 31 32 SCK SI A0h A23-A0 CS 1 2 7 8 9 10 31 32 SCK SI 55h A23-A0 CS 1 2 7 8 9 10 31 32 33 34 39 40 41 42 47 48 SCK SI 23h A23-A0 1st byte 2nd byte D7-D0 D7-D0 Fig c. program safe guard register Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 37 IS25CD512/010 & IS25LD020 Appendix2: Sector Unlock function Instruction Name Hex Code 26h 24h SECT_UNLOCK SECT_LOCK Operation Command Cycle 4 Bytes 1 Byte Sector unlock Sector lock Maximum Frequency 100 MHz 100 MHz SEC_UNLOCK COMMAND OPERATION The Sector unlock command allows the user to select a specific sector to allow program and erase operations. This instruction is effective when the blocks are designated as write-protected through the BP0, BP1 and BP2 bits in the status register. Only one sector can be enabled at any time. To enable a different sector, a previously enabled sector must be disabled by executing a Sector Lock command. The instruction code is followed by a 24-bit address specifying the target sector, but A0 through A11 are not decoded. The remaining sectors within the same block remain in read-only mode. Figure d. Sector Unlock Sequence Sector unlock CS 1 2 7 8 1 2 7 8 9 10 15 16 17 18 23 24 25 26 31 32 SCK SI 06h 26h A23-A16 A15-A8 A7-A0 In the sector unlock procedure, [A11:A0] needs equal to “0”, unlock procedure is completed, otherwise chip will regard it as illegal command. Note: 1.If the clock number will not match 8 clocks(command)+ 24 clocks (address), it will be ignored. 2.It must be executed write enable (06h) before sector unlock instructions. Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 38 IS25CD512/010 & IS25LD020 SECT_LOCK COMMAND OPERATION The Sector Lock command reverses the function of the Sector Unlock command. The instruction code does not require an address to be specified, as only one sector can be enabled at a time. The remaining sectors within the same block remain in read-only mode. Figure e. Sector Lock Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. C 08/12/2013 39 IS25CD512/010 & IS25LD020 ORDERING INFORMATION: Density Frequency (MHz) 512Kb 100 1Mb 100 2Mb 100 Order Part Number Package IS25CD512-JDLE IS25CD512-JNLE IS25CD512-JKLE IS25CD512-JULE IS25CD512-JDLA* IS25CD512-JNLA* IS25CD512-JKLA* IS25CD512-JULA* IS25CD512-JWLE IS25CD010-JDLE IS25CD010-JNLE IS25CD010-JKLE IS25CD010-JDLA* IS25CD010-JNLA* IS25CD010-JWLE IS25LD020-JDLE IS25LD020-JNLE IS25LD020-JKLE IS25LD020-JVLE IS25LD020-JDLA* IS25LD020-JNLA* IS25LD020-JKLA* IS25LD020-JVLA* IS25LD020-JWLE 8-pin TSSOP 8-pin SOIC 150mil 8-pin WSON (5x6mm) 8-pin USON (2x3mm) 8-pin TSSOP (Call Factory) 8-pin SOIC 150mil (Call Factory) 8-pin WSON (5x6mm) (Call Factory) 8-pin USON (2x3mm) (Call Factory) KGD (Call Factory) 8-pin TSSOP 8-pin SOIC 150mil 8-pin WSON (5x6mm) (Call Factory) 8-pin TSSOP (Call Factory) 8-pin SOIC 150mil (Call Factory) KGD (Call Factory) 8-pin TSSOP 8-pin SOIC 150mil 8-pin WSON (5x6mm) 8-pin VVSOP 150mil 8-pin TSSOP (Call Factory) 8-pin SOIC 150mil (Call Factory) 8-pin WSON (5x6mm) (Call Factory) 8-pin VVSOP 150mil (Call Factory) KGD (Call Factory) A* = A1, A2 Automotive Temperature Ranges Integrated Silicon Solution, Inc.- www.issi.com Rev. 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