IS25LP512M
IS25WP512M
512Mb
SERIAL FLASH MEMORY 133/112MHZ MULTI I/O SPI &
QUAD I/O QPI DTR INTERFACE
IS25LP512M
IS25WP512M
512Mb
SERIAL FLASH MEMORY 133/112MHZ MULTI I/O SPI &
QUAD I/O QPI DTR INTERFACE
FEATURES
Industry Standard Serial Interface
- IS25LP512M: 512Mbit/64Mbyte
- IS25WP512M: 512Mbit/64Mbyte
- 3 or 4 Byte Addressing Mode
- Supports Standard SPI, Fast, Dual, Dual
I/O, Quad, Quad I/O, SPI DTR, Dual I/O
DTR, Quad I/O DTR, and QPI
- Software & Hardware Reset
- Supports Serial Flash Discoverable
Parameters (SFDP)
High Performance Serial Flash (SPI)
- 50MHz Normal Read
- Up to133Mhz Fast Read:
133MHz (max) for 3.0V
112MHz (max) for 1.8V
- Up to 66MHz DTR (Dual Transfer Rate)
- Equivalent Throughput of 532 Mb/s
- Selectable Dummy Cycles
- Configurable Drive Strength
- Supports SPI Modes 0 and 3
- More than 100,000 Erase/Program Cycles
- More than 20-year Data Retention
Flexible & Efficient Memory Architecture
- Chip Erase with Uniform Sector/Block
Erase (4/32/64KB or 4/32/256 KB)(2)
- Program 1 to 256 or 512 Byte per Page(2)
- Program/Erase Suspend & Resume
Low Power with Wide Temp. Ranges
- Single Voltage Supply
IS25LP: 2.30V to 3.60V
IS25WP: 1.70V to 1.95V
- 13 mA Active Read Current
- 21 µA Standby Current
- 1 µA Deep Power Down
- Temp Grades:
Extended: -40°C to +105°C
Auto Grade (A3): -40°C to +125°C
Advanced Security Protection
- Software and Hardware Write Protection
- Advanced Sector/Block Protection
- Top/Bottom Block Protection
- Power Supply Lock Protection
- 4x256 Byte Dedicated Security Area
with OTP User-lockable Bits
- 128 bit Unique ID for Each Device
(Call Factory)
Industry Standard Pin-out & Packages(1)
- M =16-pin SOIC 300mil(2)
- L = 8-contact WSON 8x6mm(2)
- G = 24-ball TFBGA 6x8mm (4x6 ball array)(2)
- H = 24-ball TFBGA 6x8mm (5x5 ball array)(2)
Notes:
1. Call Factory for other package options available.
2. For optional 512 Byte Page size with 256 KB
Block size, see the Ordering Information.
Efficient Read and Program modes
- Low Instruction Overhead Operations
- Continuous Read 8/16/32/64 Byte
Burst Wrap
- Selectable Burst Length
- QPI for Reduced Instruction Overhead
- Data Learning Pattern for training in DTR
operation
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Rev.A5
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IS25LP512M
IS25WP512M
GENERAL DESCRIPTION
The IS25LP512M and IS25WP512M Serial Flash memory offers a versatile storage solution with high flexibility
and performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash is for systems
that require limited space, a low pin count, and low power consumption. The device is accessed through a 4-wire
SPI Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable
(CE#) pins, which can also be configured to serve as multi-I/O (see pin descriptions).
The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock frequencies
of up to 133MHz allow for equivalent clock rates of up to 532MHz (133MHz x 4) which equates to 66.5Mbytes/s
of data throughput. The IS25xP series of Flash adds support for DTR (Double Transfer Rate) commands that
transfer addresses and read data on both edges of the clock. These transfer rates can outperform 16-bit Parallel
Flash memories allowing for efficient memory access to support XIP (execute in place) operation.
Initial state of the memory array is erased (all bits are set to 1) when shipped from the factory.
QPI (Quad Peripheral Interface) supports 2-cycle instruction further reducing instruction times. Pages can be
erased in groups of 4Kbyte sectors, 32Kbyte blocks, 64K/256Kbyte blocks, and/or the entire chip. The uniform
sector and block architecture allows for a high degree of flexibility so that the device can be utilized for a broad
variety of applications requiring solid data retention.
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IS25LP512M
IS25WP512M
TABLE OF CONTENTS
FEATURES ........................................................................................................................................................... 2
GENERAL DESCRIPTION ................................................................................................................................... 3
TABLE OF CONTENTS ........................................................................................................................................ 4
1.
PIN CONFIGURATION .................................................................................................................................. 7
2.
PIN DESCRIPTIONS ..................................................................................................................................... 8
3.
BLOCK DIAGRAM ....................................................................................................................................... 10
4.
SPI MODES DESCRIPTION ....................................................................................................................... 11
5.
SYSTEM CONFIGURATION ....................................................................................................................... 13
5.1 BLOCK/SECTOR ADDRESSES ........................................................................................................... 13
5.2 Serial Flash Discoverable Parameters .................................................................................................. 15
6.
REGISTERS ................................................................................................................................................ 21
6.1 STATUS REGISTER ............................................................................................................................. 21
6.2 FUNCTION REGISTER ......................................................................................................................... 26
6.3 READ REGISTER AND EXTENDED REGISTER ................................................................................. 28
6.3.1 READ REGISTER ......................................................................................................................... 28
6.3.2 EXTENDED READ REGISTER ..................................................................................................... 31
6.4 BANK ADDRESS REGISTER ............................................................................................................... 33
6.5 ADVANCED SECTOR/BLOCK PROTECTION (ASP) RELATED REGISTER ..................................... 34
6.5.1
ADVANCED SECTOR/BLOCK PROTECTION REGISTER (ASPR) ..................................... 34
6.5.2
PASSWORD REGISTER........................................................................................................ 35
6.5.3
PPB LOCK REGISTER........................................................................................................... 35
6.5.4 PB REGISTER ............................................................................................................................... 36
7.
6.5.5
DYB REGISTER ..................................................................................................................... 36
6.5.6
DATA LEARNING PATTERN REGISTER.............................................................................. 37
PROTECTION MODE.................................................................................................................................. 38
7.1 HARDWARE WRITE PROTECTION..................................................................................................... 38
7.2 SOFTWARE WRITE PROTECTION ..................................................................................................... 38
7.2.1 BLOCK PROTECTION BITS ......................................................................................................... 38
7.2.2 ADVANCED SECTOR/BLOCK PROTECTION (ASP) .................................................................. 39
8.
DEVICE OPERATION ................................................................................................................................. 47
8.1 COMMAND OVERVIEW ....................................................................................................................... 47
8.2 COMMAND SET SUMMARY ................................................................................................................ 48
8.3 NORMAL READ OPERATION (NORD, 03h or 4NORD, 13h) .............................................................. 57
8.4 FAST READ OPERATION (FRD, 0Bh or 4FRD, 0Ch) .......................................................................... 60
8.5 HOLD OPERATION ............................................................................................................................... 64
8.6 FAST READ DUAL I/O OPERATION (FRDIO, BBh or 4FRDIO, BCh) ................................................. 65
8.7 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh or 4FRDO, 3Ch).......................................... 69
8.8 FAST READ QUAD OUTPUT OPERATION (FRQO, 6Bh or 4FRQO 6Ch) ......................................... 72
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IS25LP512M
IS25WP512M
8.9 FAST READ QUAD I/O OPERATION (FRQIO, EBh or 4FRQIO, ECh) ................................................ 75
8.10 PAGE PROGRAM OPERATION (PP, 02h or 4PP, 12h)..................................................................... 82
8.11 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h/38h or 4PPQ, 34h/3Eh) ......................... 85
8.12 ERASE OPERATION .......................................................................................................................... 86
8.13 SECTOR ERASE OPERATION (SER, D7h/20h or 4SER, 21h) ......................................................... 87
8.14 BLOCK ERASE OPERATION (BER32K:52h or 4BER32K:5Ch, BER64K/256K:D8h or
4BER64K/256K:DCh) .................................................................................................................................. 89
8.15 CHIP ERASE OPERATION (CER, C7h/60h) ...................................................................................... 92
8.16 WRITE ENABLE OPERATION (WREN, 06h) ..................................................................................... 93
8.17 WRITE DISABLE OPERATION (WRDI, 04h) ...................................................................................... 94
8.18 READ STATUS REGISTER OPERATION (RDSR, 05h) .................................................................... 95
8.19 WRITE STATUS REGISTER OPERATION (WRSR, 01h) .................................................................. 96
8.20 READ FUNCTION REGISTER OPERATION (RDFR, 48h) ................................................................ 97
8.21 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h).............................................................. 98
8.22 ENTER QUAD PERIPHERAL INTERFACE (QPI) MODE OPERATION (QPIEN,35h; QPIDI,F5h) ... 99
8.23 PROGRAM/ERASE SUSPEND & RESUME ..................................................................................... 100
8.24 ENTER DEEP POWER DOWN (DP, B9h) ........................................................................................ 103
8.25 RELEASE DEEP POWER DOWN (RDPD, ABh) .............................................................................. 104
8.26 SET READ PARAMETERS OPERATION (SRPNV: 65h, SRPV: C0h/63h) ..................................... 105
8.27 SET EXTENDED READ PARAMETERS OPERATION (SERPNV: 85h, SERPV: 83h) ................... 107
8.28 READ READ PARAMETERS OPERATION (RDRP, 61h) ................................................................ 108
8.29 READ EXTENDED READ PARAMETERS OPERATION (RDERP, 81h) ......................................... 109
8.30 CLEAR EXTENDED READ REGISTER OPERATION (CLERP, 82h) .............................................. 110
8.31 READ PRODUCT IDENTIFICATION (RDID, ABh) ........................................................................... 111
8.32 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9Fh; RDJDIDQ, AFh)
................................................................................................................................................................... 113
8.33 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90h) ....................... 114
8.34 READ UNIQUE ID NUMBER (RDUID, 4Bh) ..................................................................................... 115
8.35 READ SFDP OPERATION (RDSFDP, 5Ah) ..................................................................................... 116
8.36 NO OPERATION (NOP, 00h) ............................................................................................................ 116
8.37 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h)) AND HARDWARE
RESET ....................................................................................................................................................... 117
8.38 SECURITY INFORMATION ROW ..................................................................................................... 118
8.39 INFORMATION ROW ERASE OPERATION (IRER, 64h) ................................................................ 119
8.40 INFORMATION ROW PROGRAM OPERATION (IRP, 62h) ............................................................ 120
8.41 INFORMATION ROW READ OPERATION (IRRD, 68h) .................................................................. 121
8.42 FAST READ DTR MODE OPERATION (FRDTR, 0Dh or 4FRDTR, 0Eh) ........................................ 122
8.43 FAST READ DUAL IO DTR MODE OPERATION (FRDDTR, BDh or 4FRDDTR, BEh) .................. 127
8.44 FAST READ QUAD IO DTR MODE OPERATION IN SPI MODE (FRQDTR, EDh or 4FRQDTR, EEh)
................................................................................................................................................................... 131
8.45 SECTOR LOCK/UNLOCK FUNCTIONS ........................................................................................... 139
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IS25LP512M
IS25WP512M
8.46 READ BANK ADDRESS REGISTER OPERATION (RDBR: 16h/C8h) ............................................ 142
8.47 WRITE BANK ADDRESS REGISTER OPERATION (WRBRNV: 18h, WRBRV: 17h/C5h) ............. 143
8.48 ENTER 4-BYTE ADDRESS MODE OPERATION (EN4B, B7h) ....................................................... 144
8.49 EXIT 4-BYTE ADDRESS MODE OPERATION (EX4B, 29h) ............................................................ 145
8.50 READ DYB OPERATION (RDDYB, FAh or 4RDDYB, E0h) ............................................................. 146
8.51 WRITE DYB OPERATION (WRDYB, FBh or 4WRDYB, E1h) .......................................................... 148
8.52 READ PPB OPERATION (RDPPB, FCh or 4RDPPB, E2h) ............................................................. 150
8.53 PROGRAM PPB OPERATION (PGPPB, FDh or 4PGPPB, E3h) ..................................................... 151
8.54 ERASE PPB OPERATION (ERPPB, E4h) ........................................................................................ 153
8.55 READ ASP OPERATION (RDASP, 2Bh) .......................................................................................... 154
8.56 PROGRAM ASP OPERATION (PGASP, 2Fh) .................................................................................. 155
8.57 READ PPB LOCK BIT OPERATION (RDPLB, A7h) ......................................................................... 156
8.58 WRITE PPB LOCK BIT OPERATION (WRPLB, A6h)....................................................................... 157
8.59 SET FREEZE BIT OPERATION (SFRZ, 91h) ................................................................................... 158
8.60 READ PASSWORD OPERATION (RDPWD, E7h) ........................................................................... 159
8.61 PROGRAM PASSWORD OPERATION (PGPWD, E8h) .................................................................. 160
8.62 UNLOCK PASSWORD OPERATION (UNPWD, E9h) ...................................................................... 161
8.63 GANG SECTOR/BLOCK LOCK OPERATION (GBLK, 7Eh) ............................................................ 162
8.64 GANG SECTOR/BLOCK UNLOCK OPERATION (GBUN, 98h) ....................................................... 163
8.65 DATA LEARNING PATTERN (DLP).................................................................................................. 164
8.66 PROGRAM NVDLR OPERATION (PNVDLR, 43h)........................................................................... 167
8.67 WRITE VDLR OPERATION (WRVDLR, 4Ah) ................................................................................... 168
8.68 READ DLP OPERATION (RDDLP, 41h) ........................................................................................... 169
9.
ELECTRICAL CHARACTERISTICS.......................................................................................................... 170
9.1 ABSOLUTE MAXIMUM RATINGS (1) .................................................................................................. 170
9.2 OPERATING RANGE .......................................................................................................................... 170
9.3 DC CHARACTERISTICS ..................................................................................................................... 171
9.4 AC MEASUREMENT CONDITIONS ................................................................................................... 172
9.5 Pin CAPACITANCE ............................................................................................................................. 172
9.6 AC CHARACTERISTICS ..................................................................................................................... 173
9.7 SERIAL INPUT/OUTPUT TIMING ....................................................................................................... 175
9.8 POWER-UP AND POWER-DOWN ..................................................................................................... 177
9.9 PROGRAM/ERASE PERFORMANCE ................................................................................................ 178
9.10 RELIABILITY CHARACTERISTICS .................................................................................................. 178
10.
PACKAGE TYPE INFORMATION ........................................................................................................ 179
10.1 8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD (WSON) PACKAGE 8x6mm (L).............. 179
10.2 16-LEAD PLASTIC SMALL OUTLINE PACKAGE (300 MILS BODY WIDTH) (M) ........................... 180
10.3 24-BALL THIN PROFILE FINE PITCH BGA 6x8mm 4x6 BALL ARRAY (G) .................................... 181
10.4 24-BALL THIN PROFILE FINE PITCH BGA 6x8mm 5x5 BALL ARRAY (H) .................................... 182
11.
ORDERING INFORMATION – Valid Part Numbers ............................................................................. 183
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Rev.A5
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IS25LP512M
IS25WP512M
1. PIN CONFIGURATION
(1)
HOLD# or RESET#
(IO3)
Vcc
1
16
SCK
2
15
SI (IO0)
RESET#/NC
3
14
NC
NC
4
13
NC
NC
5
12
NC
NC
6
11
NC
CE#
7
10
GND
SO (IO1)
8
9
CE#
1
8 Vcc
SO (IO1)
2
7 RESET# (IO3)(1)
WP# (IO2)
3
6 SCK
GND
4
5 SI (IO0)
WP# (IO2)
8-contact WSON 8x6mm
16-pin SOIC 300mil
Top View, Balls Facing Down
Top View, Balls Facing Down
A1
A2
A3
A4
NC
NC
NC
RESET#/NC
B1
B2
B3
B4
NC
SCK
GND
VCC
C1
C2
C3
C4
NC
CE#
NC
WP#(IO2)
D1
D2
D3
D4
NC
SO(IO1)
SI(IO0)
HOLD# or
RESET# (IO3)
(1)
E1
E2
E3
E4
NC
NC
NC
NC
F1
F2
F3
F4
NC
NC
NC
NC
24-ball TFBGA 6x8mm (4x6 ball array)
(Package: G)
Note:
1.
HOLD# or
A2
A3
NC
NC
A4
A5
B1
B2
B3
B4
B5
NC
SCK
GND
VCC
NC
C1
C2
C3
C4
C5
NC
CE#
NC
WP#(IO2)
NC
RESET#/NC
D1
D2
D3
D4
NC
SO(IO1)
SI(IO0)
HOLD# or
RESET# (IO3)
NC
D5
(1)
NC
E1
E2
E3
E4
E5
NC
NC
NC
NC
NC
24-ball TFBGA 6x8mm (5x5 ball array)
(Package: H)
The pin can be configured as Hold# (IO3) or Reset# (IO3) by setting P7 bit of the Read Register if A4 ball in
BGA or Pin#3 in 16-SOIC is DNU instead of Dedicated RESET#.
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IS25LP512M
IS25WP512M
2. PIN DESCRIPTIONS
SYMBOL
TYPE
DESCRIPTION
Chip Enable: The Chip Enable (CE#) pin enables and disables the devices
operation. When CE# is high the device is deselected and output pins are in a high
impedance state. When deselected the devices non-critical internal circuitry power
down to allow minimal levels of power consumption while in a standby state.
CE#
INPUT
When CE# is pulled low the device will be selected and brought out of standby mode.
The device is considered active and instructions can be written to, data read, and
written to the device. After power-up, CE# must transition from high to low before a
new instruction will be accepted.
Keeping CE# in a high state deselects the device and switches it into its low power
state. Data will not be accepted when CE# is high.
SI (IO0),
SO (IO1)
INPUT/OUTPUT
Serial Data Input, Serial Output, and IOs (SI, SO, IO0, and IO1):
This device supports standard SPI, Dual SPI, and Quad SPI operation. Standard SPI
instructions use the unidirectional SI (Serial Input) pin to write instructions,
addresses, or data to the device on the rising edge of the Serial Clock (SCK).
Standard SPI also uses the unidirectional SO (Serial Output) to read data or status
from the device on the falling edge of the serial clock (SCK).
In Dual and Quad SPI mode, SI and SO become bidirectional IO pins to write
instructions, addresses or data to the device on the rising edge of the Serial Clock
(SCK) and read data or status from the device on the falling edge of SCK. Quad
SPI instructions use the WP# and HOLD# pins as IO2 and IO3 respectively.
WP# (IO2)
INPUT/OUTPUT
Write Protect/Serial Data IO (IO2): The WP# pin protects the Status Register from
being written in conjunction with the SRWD bit. When the SRWD is set to “1” and the
WP# is pulled low, the Status Register bits (SRWD, QE, BP3, BP2, BP1, BP0) are
write-protected and vice-versa for WP# high. When the SRWD is set to “0”, the Status
Register is not write-protected regardless of WP# state.
When the QE bit is set to “1”, the WP# pin (Write Protect) function is not available
since this pin is used for IO2.
HOLD# or RESET#/Serial Data IO (IO3): When the QE bit of Status Register is set
to “1”, HOLD# pin or RESET# is not available since it becomes IO3.
The Device without Dedicated RESET#:
When QE=0, the pin acts as HOLD# or RESET# and either one can be selected by
the P7 bit setting in Read Register. HOLD# will be selected if P7=0 (Default) and
RESET# will be selected if P7=1.
The Device with Dedicated RESET#:
HOLD# (IO3)
or
RESET# (IO3)
-
When QE=0 and Dedicated RESET# is Enabled (Default), the pin acts as
HOLD# regardless of the P7 bit setting in Read Register.
-
When QE=0 and Dedicated RESET# is Disabled, the pin acts as HOLD# or
RESET# and either one can be selected by the P7 bit setting in Read Register.
HOLD# will be selected if P7=0 (Default) and RESET# will be selected if P7=1.
INPUT/OUTPUT
The HOLD# pin allows the device to be paused while it is selected. It pauses serial
communication by the master device without resetting the serial sequence. The
HOLD# pin is active low. When HOLD# is in a low state and CE# is low, the SO pin
will be at high impedance. Device operation can resume when HOLD# pin is brought
to a high state.
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IS25LP512M
IS25WP512M
SYMBOL
TYPE
DESCRIPTION
RESET#: This dedicated RESET# is available in 24-ball BGA package.
RESET#
INPUT
SCK
INPUT
Vcc
POWER
GND
GROUND
NC
Unused
The RESET# pin is a hardware RESET signal. When RESET# is driven HIGH, the
memory is in the normal operating mode. When RESET# is driven LOW, the memory
enters reset mode and output is High-Z. If RESET# is driven LOW while an internal
WRITE, PROGRAM, or ERASE operation is in progress, data may be lost.
Dedicated RESET# function can be Disabled when bit 0 of Function Register = 1.
It has an internal pull-up resistor and may be left floating if not used.
Serial Data Clock: Synchronized Clock for input and output timing operations.
Power: Device Core Power Supply
Ground: Connect to ground when referenced to Vcc
NC: Pins labeled “NC” stand for “No Connect”. Not internally connected.
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IS25LP512M
IS25WP512M
3. BLOCK DIAGRAM
Control Logic
High Voltage Generator
Status
Register
I/O Buffers and
Data Latches
256 Bytes
Page Buffer
WP#
(IO2)
SI
(IO0)
SO
(IO1)
(1)
HOLD# or RESET#
(IO3)
RESET#
Y-Decoder
X-Decoder
SCK
Serial Peripheral Interface
CE#
Memory Array
Address Latch &
Counter
Note:
1: In case of device without dedicated RESET#, when QE=0, the pin acts as HOLD# or RESET# and either one can
be selected by the P7 bit setting in Read Register. HOLD# will be selected if P7=0 (Default) and RESET# will be
selected if P7=1.
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IS25LP512M
IS25WP512M
4. SPI MODES DESCRIPTION
Multiple IS25LP512M devices or multiple IS25WP512M devices can be connected on the SPI serial bus and
controlled by a SPI Master, i.e. microcontroller, as shown in Figure 4.1. The devices support either of two SPI
modes:
Mode 0 (0, 0)
Mode 3 (1, 1)
The difference between these two modes is the clock polarity. When the SPI master is in stand-by mode, the serial
clock remains at “0” (SCK = 0) for Mode 0 and the clock remains at “1” (SCK = 1) for Mode 3. Please refer to Figure
4.2 and Figure 4.3 for SPI and QPI mode. In both modes, the input data is latched on the rising edge of Serial Clock
(SCK), and the output data is available from the falling edge of SCK.
Figure 4.1 Connection Diagram among SPI Master and SPI Slaves (Memory Devices)
SDO
SPI interface with
(0,0) or (1,1)
SDI
SCK
SCK SO
SI
SCK SO
SI
SCK SO
SI
SPI Master
(i.e. Microcontroller)
CS3
CS2
SPI
Memory
Device
CS1
CE#
SPI
Memory
Device
CE#
HOLD#
WP# or RESET#
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SPI
Memory
Device
CE#
WP# HOLD#
or RESET#
WP# HOLD#
or RESET#
11
IS25LP512M
IS25WP512M
Figure 4.2 SPI Mode Support
SCK
Mode 0 (0,0)
SCK
Mode 3 (1,1)
MSB
SI
SO
MSB
Figure 4.3 QPI Mode Support
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Mode 0
3-byte Address
Mode Bits
Data 1
Data 2
Data 3
IO0
C4
C0
20
16
12
8
4
0
4
0
4
0
4
0
4
0
...
IO1
C5
C1
21
17
13
9
5
1
5
1
5
1
5
1
5
1
...
IO2
C6
C2
22
18
14
10
6
2
6
2
6
2
6
2
6
2
...
IO3
C71
C3
23 1
19
15
11
7
3
71
3
71
3
71
3
71
3
...
Note1: MSB (Most Significant Bit)
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IS25LP512M
IS25WP512M
5. SYSTEM CONFIGURATION
The memory array is divided into uniform 4 Kbyte sectors or uniform 32/64 Kbyte blocks (a block consists of
eight/sixteen adjacent sectors respectively).
Also optional uniform 32/256 Kbyte blocks are available with 512B page size. See ordering table for more detail
information.
Table 5.1 illustrates the memory map of the device. The Status Register controls how the memory is protected.
5.1 BLOCK/SECTOR ADDRESSES
Table 5.1 Block/Sector Addresses (Block Size = 32KB/64KB)
Memory
Density
Block No.
(64Kbyte)
Block No.
(32Kbyte)
Block 0
Block 0
Block 1
Block 2
Block 1
Block 3
Block 4
Block 2
Block 5
512Mb
:
000 0000h – 000 0FFFh
:
:
000 F000h – 000 FFFFh
001 0000h – 001 0FFFh
:
:
Sector 31
Sector 32
:
:
Sector 47
:
4
4
:
:
4
:
001 F000h – 001 FFFFh
002 0000h – 002 0FFFh
:
:
002 F000h – 002 FFFFh
:
:
:
Sector 8160
:
:
4
:
:
1FE 0000h – 1FE 0FFFh
:
:
Sector 8175
Sector 8176
:
:
Sector 8191
4
4
:
:
4
1FE F000h – 1FE FFFFh
1FF 0000h – 1FF 0FFFh
:
:
1FF F000h – 1FF FFFFh
:
:
:
Sector 16352
:
:
Sector 16367
4
:
:
4
3FE 0000h – 3FE 0FFFh
:
:
3FE F000h – 3FE FFFFh
Sector 16368
:
:
Sector 16383
4
:
:
4
3FF 0000h – 3FF 0FFFh
:
:
Block 1020
Block 510
Block 1021
Block 1022
Block 511
Block 1023
:
Sector 0
:
:
Sector 15
Sector 16
:
Sector Size
(Kbyte)
4
:
:
4
4
:
Sector No.
:
Block 2044
Block 1022
Block 2045
Block 2046
Block 1023
Block 2047
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Address Range
:
3FF F000h – 3FF FFFFh
13
IS25LP512M
IS25WP512M
Table 5.2 Block/Sector Addresses (Block Size = 32KB/256KB)
Memory
Density
Block No.
(256Kbyte)
Block No.
(32Kbyte)
Block 0
Block 1
Block 2
Block 3
Block 0
Block 4
Block 5
Block 6
Block 7
:
512Mb
Block 1017
:
:
Sector 31
Sector 32
:
:
Sector 47
Sector 48
Block 1023
Block 2041
Block 2042
Block 2043
Block 255
Block 2044
Block 2045
Block 2046
Block 2047
Address Range
000 0000h – 000 0FFFh
:
:
000 F000h – 000 FFFFh
001 0000h – 001 0FFFh
:
:
001 F000h – 001 FFFFh
002 0000h – 002 0FFFh
:
:
002 F000h – 002 FFFFh
003 0000h – 003 0FFFh
:
:
003 F000h – 003 FFFFh
:
:
:
Sector 8128
:
:
Sector 8143
4
:
:
4
1FC 0000h – 1FC 0FFFh
:
:
1FC F000h – 1FCF FFFh
:
:
:
Sector 8176
:
:
Sector 8191
4
:
:
4
1FF 0000h – 1FF 0FFFh
:
:
1FF F000h – 1FF FFFFh
:
:
:
Sector 16320
:
:
Sector 16335
Sector 16336
:
:
Sector 16351
Sector 16352
:
:
4
:
:
4
3FC 0000h – 3FC 0FFFh
:
:
3FC F000h – 3FC FFFFh
3FD 0000h – 3FD 0FFFh
:
:
3FD F000h – 3FD FFFFh
3FE 0000h – 3FE 0FFFh
:
:
Sector 16367
Sector 16368
:
:
Sector 16383
4
4
:
:
4
Sector 63
:
Block 2040
Sector Size
(Kbyte)
4
:
:
4
4
:
:
4
4
:
:
4
:
Block 1022
:
Sector 0
:
:
Sector 15
Sector 16
:
Block 1016
Block 127
Sector No.
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4
:
:
3FE F000h – 3FE FFFFh
3FF 0000h – 3FF 0FFFh
:
:
3FF F000h – 3FF FFFFh
14
IS25LP512M
IS25WP512M
5.2 SERIAL FLASH DISCOVERABLE PARAMETERS
The Serial Flash Discoverable Parameters (SFDP) standard defines the structure of the SFDP database within the
memory device. SFDP is the standard of JEDEC JESD216.
The JEDEC-defined header with Parameter ID FF00h and related Basic Parameter Table is mandatory. Additional
parameter headers and tables are optional.
Table 5.3 Signature and Parameter Identification Data Values
Description
SFDP Signature
SFDP Revision
Number of Parameter Headers (NPH)
Unused
Parameter ID LSB
Parameter Minor Revision
Parameter Major Revision
Parameter Table Length (in DWPRDs)
Basic Flash Parameter Table Pointer (PTP)
Parameter ID MSB
Parameter ID LSB
Parameter Minor Revision
Parameter Major Revision
Parameter Table Length (in DWPRDs)
Parameter Table Pointer (PTP)
Parameter ID MSB
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Minor
Major
Address
(Byte)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
Address
(Bit)
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
15
Data
53h
46h
44h
50h
06h
01h
01h
FFh
00h
06h
01h
10h
30h
00h
00h
FFh
84h
0h
1h
02h
80h
00h
00h
FFh
IS25LP512M
IS25WP512M
Table 5.4 JEDEC Basic Flash Parameter Table
Description
Minimum Sector Erase Sizes
Write Granularity
Volatile Status Register Block Protect bits
Write Enable Instruction Select for writing to Volatile Status
Register
Unused
4KB Erase Instruction
Supports (1-1-2) Fast Read
Address Bytes
Supports Double Transfer Rate (DTR) Clocking
Supports (1-2-2) Fast Read
Supports (1-4-4) Fast Read
Supports (1-1-4) Fast Read
Unused
Reserved
Address
(Byte)
30h
Address
(Bit)
1:0
2
3
Data
01b
1b
0b
4
0b
33h
7:5
15:8
16
18:17
19
20
21
22
23
31:24
111b
20h
1b
01b
1b
1b
1b
1b
1b
FFh
Flash memory Density (bits)
34h
35h
36h
7:0
15:8
23:16
FFh
FFh
FFh
Flash memory Density
37h
31:24
1Fh
4:0
7:5
15:8
20:16
23:21
31:24
00100b
010b
EBh
01000b
000b
6Bh
4:0
7:5
15:8
20:16
23:21
31:24
01000b
000b
3Bh
00000b
100b
BBh
1-4-4 Fast Read Wait Cycle Count
1-4-4 Fast Read Mode bit Cycle Count
1-4-4 Fast Read Instruction
1-1-4 Fast Read Wait Cycle Count
1-1-4 Fast Read Mode bit Cycle Count
1-1-4 Fast Read Instruction
1-1-2 Fast Read Wait Cycle Count
1-1-2 Fast Read Mode bit Cycle Count
1-1-2 Fast Read Instruction
1-2-2 Fast Read Wait Cycle Count
1-2-2 Fast Read Mode bit Cycle Count
1-2-2 Fast Read Instruction
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31h
32h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
16
IS25LP512M
IS25WP512M
Table 5.4 JEDEC Basic Flash Parameter Table (Continued)
Address
(Bit)
0
3:1
4
7:5
31:8
0b
111b
1b
111b
FFFFFFh
15:0
20:16
23:21
31:24
FFFFh
00000b
000b
FFh
4Bh
15:0
20:16
23:21
31:24
FFFFh
00100b
010b
EBh
Erase Type 1 Size (4KB)
Erase Type 1 Instruction
Erase Type 2 Size (32KB)
Erase Type 2 Instruction
4Ch
4Dh
4Eh
4Fh
7:0
15:8
23:16
31:24
0Ch
20h
0Fh
52h
Erase Type 3 Size (64KB)
Erase Type 3 Instruction
Erase Type 4 Size (256KB)
Erase Type 4 Instruction
50h
51h
52h
53h
7:0
15:8
23:16
31:24
10h(00h(1))
D8h(FFh(1))
00h(12h(1))
FFh(D8h(1))
3:0
8:4
10:9
15:11
17:16
0010b
00110b
01b
01000b
01b
01010b
(00000b(1))
01b(00b(1))
00000b
(00101b(1))
00b(10b(1))
Description
Supports (2-2-2) Fast Read
Reserved
Supports (4-4-4) Fast Read
Reserved
Reserved
Address
(Byte)
40h
43:41h
Reserved
2-2-2 Fast Read Wait Cycle Count
2-2-2 Fast Read Mode bit Cycle Count
2-2-2 Fast Read Instruction
45:44h
Reserved
4-4-4 Fast Read Wait Cycle Count
4-4-4 Fast Read Mode bit Cycle Count
4-4-4 Fast Read Instruction
49:48h
46h
47h
4Ah
Multiplier from typical erase time to maximum erase time
Sector Type 1 ERASE time (typ)
Sector Type 2 ERASE time (typ)
57:54h
Sector Type 3 ERASE time (typ)
22:18
24:23
Sector Type 4 ERASE time (typ)
29:25
31:30
Note:
1.
Only for option K (256KB Block Size instead of 64KB)
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Data
IS25LP512M
IS25WP512M
Table 5.4 JEDEC Basic Flash Parameter Table (Continued)
Description
Multiplier from typical time to maximum time for page or byte
PROGRAM
Address
(Byte)
5Ah:59h
Chip Erase, Typical time
Suspend in-progress program max latency
5Bh
5Ch
5Eh:5Dh
Erase Resume to Suspend Interval
Suspend in-progress erase max latency
0010b
13
17:14
18
22:19
23
1000b
(1001b(1))
00100b
(01001b(1))
1b
1001b
0b
0000b
0b
28:24
10011b
30:29
31
10b
1b
3:0
7:4
8
12:9
17:13
19:18
23:20
28:24
30:29
31
1100b
1110b
1b
0110b
01100b
10b
0110b
01100b
10b
0b
12:8
Byte Program Typical time, additional byte
Prohibited Operations During Program Suspend
Prohibited Operations During Erase Suspend
Reserved
Program Resume to Suspend Interval
3:0
7:4
Page Program Typical time
Units
Reserved
Data
58h
Page size
Byte Program Typical time, first byte
Address
(Bit)
5Fh
Suspend /Resume supported
Program Resume Instruction
Program Suspend Instruction
Erase Resume Instruction
Erase Suspend Instruction
60h
61h
62h
63h
7:0
15:8
23:16
31:24
7Ah
75h
7Ah
75h
Reserved
Status Register Polling Device Busy
64h
1:0
7:2
11b
111101b
Note:
1.
Only for option K (512B Page Size instead of 256B)
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IS25LP512M
IS25WP512M
Table 5.4 JEDEC Basic Flash Parameter Table (Continued)
Address
(Byte)
Description
Exit Deep Power-down to next operation delay
3V
1.8V
Exit Deep Power-down to next operation delay Units
Exit Deep Power-down Instruction
Enter Deep Power-down Instruction
Deep Power-down Supported
4-4-4 mode disable sequences (QPIDI)
4-4-4 mode enable sequences (QPIEN)
0-4-4 Mode Supported
0-4-4 Mode Exit Method
0-4-4 Mode Entry Method:
Quad Enable Requirements (QER)
Hold or RESET Disable
Reserved
Volatile or Non-Volatile Register and Write Enable (WREN)
Instruction for Status Register 1
Reserved
Soft Reset and Rescue Sequence Support
Exit 4-Byte Addressing
Enter 4-Byte Addressing
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Address
(Bit)
14:13
22:15
30:23
31
00010b
00100b
01b
ABh
B9h
0b
3:0
8:4
9
15:10
19:16
22:20
23
31:24
1010b
00100b
1b
110000b
1100b
010b
0b
FFh
6:0
1100001b
7
13:8
23:14
31:24
1b
110000b
1111101000b
10101001b
12:8
67h:65h
69h:68h
6Ah
6Bh
6Ch
6Eh:6Dh
6Fh
Data
19
IS25LP512M
IS25WP512M
Table 5.5. Parameter Table (1): 4-byte Address Instruction Tables
Description
Support for (1-1-1) READ Command, Instruction = 13h
Support for (1-1-1) FAST_READ Command, Instruction = 0Ch
Support for (1-1-2) FAST_READ Command, Instruction = 3Ch
Support for (1-2-2) FAST_READ Command, Instruction = BCh
Support for (1-1-4) FAST_READ Command, Instruction = 6Ch
Support for (1-4-4) FAST_READ Command, Instruction = ECh
Support for (1-1-1) Page Program Command, Instruction = 12h
Support for (1-1-4) Page Program Command, Instruction = 34h
Support for (1-4-4) Page Program Command, Instruction = 3Eh
Support for Erase Command-Type 1
Support for Erase Command-Type 2
Support for Erase Command-Type 3
Support for Erase Command-Type 4
Support for (1-1-1) DTR_READ Command, Instruction = 0Eh
Support for (1-2-2) DTR_READ Command, Instruction = BEh
Support for (1-4-4) DTR_READ Command, Instruction = EEh
Support for volatile individual sector lock Read Command (E0h)
Support for volatile individual sector lock Write Command (E1h)
Support for non-volatile individual sector lock Read Command
(E2h)
Support for non-volatile individual sector lock Write Command
(E3h)
Reserved
Reserved
Sector Erase Instruction for Sector Type I
Sector Erase Instruction for Sector Type 2
Sector Erase Instruction for Sector Type 3
Sector Erase Instruction for Sector Type 4
Note:
1.
Address
(Byte)
Address
(Bit)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1b
1b
1b
1b
1b
1b
1b
1b
0b
1b
1b
1b (0b(1))
0b (1b(1))
1b
1b
1b
1b
1b
18
1b
19
1b
83h
23:20
31:24
1111b
FFh
84h
85h
86h
87h
7:0
15:8
23:16
31:24
21h
5Ch
DCh (FFh(1))
FFh (DCh(1))
80h
81h
82h
Only for option K (256KB Block Size instead of 64KB)
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IS25LP512M
IS25WP512M
6. REGISTERS
The device has many sets of Registers such as Status, Function, Read, and so on.
When the register is read continuously, the same data is output repeatedly until CE# goes HIGH.
6.1 STATUS REGISTER
Status Register Format and Status Register Bit Definitions are described in Tables 6.1 & 6.2.
Table 6.1 Status Register Format
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRWD
QE
BP3
BP2
BP1
BP0
WEL
WIP
0
0
0
0
0
0
0
0
Table 6.2 Status Register Bit Definition
Bit
Name
Bit 0
WIP
Bit 1
WEL
Bit 2
BP0
Bit 3
BP1
Bit 4
BP2
Bit 5
BP3
Bit 6
QE
Bit 7
SRWD
Definition
Write In Progress Bit:
"0" indicates the device is ready (default)
"1" indicates a write cycle is in progress and the device is busy
Write Enable Latch:
"0" indicates the device is not write enabled (default)
"1" indicates the device is write enabled
Block Protection Bit: (See Tables 6.4 for details)
"0" indicates the specific blocks are not write-protected (default)
"1" indicates the specific blocks are write-protected
Quad Enable bit:
“0” indicates the Quad output function disable (default)
“1” indicates the Quad output function enable
Status Register Write Disable: (See Table 7.1 for details)
"0" indicates the Status Register is not write-protected (default)
"1" indicates the Status Register is write-protected
Read/Write
Type
R
Volatile
R/W 1
Volatile
R/W
Non-Volatile
R/W
Non-Volatile
R/W
Non-Volatile
Note: WEL bit can be written by WREN and WRDI commands, but cannot by WRSR command.
The BP0, BP1, BP2, BP3, QE, and SRWD are non-volatile and volatile memory cells that can be written by a Write
Status Register (WRSR) instruction. The default value of the BP0, BP1, BP2, BP3, QE, and SRWD bits were set
to “0” at factory.
The function of Status Register bits are described as follows:
WIP bit: Write In Progress (WIP) is read-only, and can be used to detect the progress or completion of a Program,
Erase, Write/Set Non-Volatile/OTP Register, or Gang Sector/Block Lock/Unlock operation. WIP is set to “1” (busy
state) when the device is executing the operation. During this time the device will ignore further instructions except
for Read Status/Function Register and Software/Hardware Reset instructions. In addition to the instructions, an
Erase/Program Suspend instruction also can be executed during a Program or Erase operation. When an operation
has completed, WIP is cleared to “0” (ready state) whether the operation is successful or not and the device is
ready for further instructions.
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IS25LP512M
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WEL bit: Write Enable Latch (WEL) bit indicates the status of the internal write enable latch. When WEL bit is “0”,
the internal write enable latch is disabled and the Write operations described in Table 6.3 are inhibited. When WEL
bit is “1”, the Write operations are allowed. WEL bit is set by a Write Enable (WREN, 06h) instruction. Most of Write
Non-Volatile/Volatile Register, Program and Erase instruction must be preceded by a WREN instruction.
WEL bit can be reset by a Write Disable (WRDI) instruction. It will automatically reset after the completion of any
Write Non-Volatile Register, Program and Erase operation.
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IS25LP512M
IS25WP512M
Table 6.3 Instructions requiring WREN instruction ahead
Instructions must be preceded by the WREN instruction
Name
Hex Code
Operation
PP
02h
Serial Input Page Program (3-byte or 4-byte Address)
4PP
12h
Serial Input Page Program (4-byte Address)
PPQ
32h/38h
Quad Input Page Program (3-byte or 4-byte Address)
4PPQ
34h/3Eh
Quad Input Page Program (4-byte Address)
SER
D7h/20h
Sector Erase 4KB (3-byte or 4-byte Address)
4SER
21h
Sector Erase 4KB (4-byte Address)
BER32 (32KB)
52h
Block Erase 32KB (3-byte or 4-byte Address)
4BER32 (32KB)
5Ch
Block Erase 32KB (4-byte Address)
BER64 (64KB)
D8h
Block Erase 64KB (3-byte or 4-byte Address)
DCh
Block Erase 64KB (4-byte Address)
4BER64 (64KB)
CER
C7h/60h
Chip Erase
WRSR
01h
Write Status Register
WRFR
42h
Write Function Register
SRPNV
65h
Set Read Parameters (Non-Volatile)
SRPV(1)
63h
Set Read Parameters (Volatile)
SERPNV
85h
Set Extended Read Parameters (Non-Volatile)
SERPV
83h
Set Extended Read Parameters (Volatile)
IRER
64h
Erase Information Row
IRP
62h
Program Information Row
WRBRNV
18h
Write Non-Volatile Bank Address Register
(1)
WRBRV
C5h
Write Volatile Bank Address Register
WRDYB
FBh
Write DYB Register (4-byte Address)
4WRDYB
E1h
Write DYB Register (3-byte or 4-byte Address)
PGPPB
FDh
Write PPB (3-byte or 4-byte Address)
4PGPPB
E3h
Write PPB (4-byte Address)
ERPPB
E4h
Erase PPB
PGASP
2Fh
Program ASP
WRPLB
A6h
Write PPB Lock Bit
SFRZ
91h
Set FREEZE bit
GBLK
7Eh
GANG Sector/Block Lock
GBUN
98h
GANG Sector/Block Unlock
PGPWD
E8h
Program Password
PNVDLR
43h
Program Non-Volatile Data Learning Pattern Register
WRVDLR
4Ah
Program Volatile Data Learning Pattern Register
Note:
1. C0h command for SRPV operation and 17h command for WRBRV operation do not require WREN command ahead.
BP3, BP2, BP1, BP0 bits: The Block Protection (BP3, BP2, BP1 and BP0) bits are used to define the portion of
the memory area to be protected. Refer to Table 6.4 for the Block Write Protection (BP) bit settings. When a defined
combination of BP3, BP2, BP1 and BP0 bits are set, the corresponding memory area is protected. Any program or
erase operation to that area will be inhibited.
Note: A Chip Erase (CER) instruction will be ignored unless all the Block Protection Bits are “0”s.
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IS25LP512M
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SRWD bit: The Status Register Write Disable (SRWD) bit operates in conjunction with the Write Protection (WP#)
signal to provide a Hardware Protection Mode. When the SRWD is set to “0”, the Status Register is not writeprotected. When the SRWD is set to “1” and the WP# is pulled low (V IL), the bits of Status Register (SRWD, QE,
BP3, BP2, BP1, BP0) become read-only, and a WRSR instruction will be ignored. If the SRWD is set to “1” and
WP# is pulled high (VIH), the Status Register can be changed by a WRSR instruction.
QE bit: The Quad Enable (QE) is a non-volatile bit in the Status Register that allows quad operation. When the QE
bit is set to “0”, the pin WP# and HOLD#/RESET# are enabled. When the QE bit is set to “1”, the IO2 and IO3 pins
are enabled.
WARNING: The QE bit must be set to “0” if WP# or HOLD#/RESET# pin (or ball) is tied directly to the power supply.
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IS25LP512M
IS25WP512M
Table 6.4 Block assignment by Block Write Protect (BP) Bits
Status Register Bits
Block Size = 64KB, Protected Memory Area (1024Blocks)
BP3
BP2
BP1
BP0
0
0
0
0
TBS = 0, Top area
TBS = 1, Bottom area
0 ( None)
0 ( None)
1023rd)
1 (1 block: 0th)
0
0
0
1
1 (1 block:
0
0
1
0
2 (2 blocks: 1022nd and 1023rd)
2 (2 blocks: 0th and 1st)
0
0
1
1
3 (4 blocks: 1020th to 1023rd)
3 (4 blocks: 0th to 3rd)
0
1
0
0
4 (8 blocks: 1016th to 1023rd)
4 (8 blocks: 0th to 7th)
0
1
0
1
5 (16 blocks: 1008th to 1023rd)
5 (16 blocks: 0th to 15th)
0
1
1
0
6 (32 blocks: 992nd to 1023rd)
6 (32 blocks: 0th to 31st)
960th
7 (64 blocks: 0th to 63rd)
0
1
1
1
7 (64 blocks:
1
0
0
0
8 (128 blocks: 896th to 1023rd)
8 (128 blocks: 0th to 127th)
1
0
0
1
9 (256 blocks: 768th to 1023rd)
9 (256 blocks: 0th to 255th)
1
0
1
0
10 (512 blocks : 512nd to 1023rd)
10 (512 blocks : 0th to 511st)
1
0
1
1
11 (768 blocks : 256th to 1023rd)
11 (768 blocks : 0th to 767th)
1
1
0
0
12 (896 blocks : 128th to 1023rd)
12 (896 blocks : 0th to 895th)
1
1
0
1
13 (960 blocks : 64th to 1023rd)
13 (960 blocks : 0th to 959th)
1
1
1
0
14 (992 blocks : 32nd to 1023rd)
14 (992 blocks : 0th to 991st)
1
1
1
1
15 (1024 blocks :
to
1023rd)
0th
to
1023rd)
15 (1024 blocks : 0th to 1023rd)
Block Size = 256KB(2), Protected Memory Area (256Blocks)
Status Register Bits
BP3
BP2
BP1
BP0
TBS(T/B selection) = 0, Top area
TBS(T/B selection) = 1, Bottom area
0
0
0
0
0
0
0
0( None)
0( None)
1
1(1 block : 255th)
1(1 block : 0th)
0
0
1
0
2(2 blocks : 254th and 255th)
252nd
3(4 blocks : 0th to 3rd)
0
0
1
1
3(4 blocks :
0
1
0
0
4(8 blocks : 248th to 255th)
4(8 blocks : 0th to 7th)
0
1
0
1
5(16 blocks : 240th to 255th)
5(16 blocks : 0th to 15th)
0
1
1
0
6(32 blocks : 224th to 255th)
6(32 blocks : 0th to 31st)
0
1
1
1
7(64 blocks : 192nd to 255th)
7(64 blocks : 0th to 63rd)
1
0
0
0
8(128 blocks : 128th to 255th)
8(128 blocks : 0th to 127th)
1
0
0
1
9(256 blocks : 0th to 255th) All blocks
9(256 blocks : 0th to 255th) All blocks
1
0
1
x
10-11(256 blocks : 0th to 255th) All blocks
10-11(256 blocks : 0th to 255th) All blocks
x
0th
12-15(256 blocks : 0th to 255th) All blocks
1
1
x
to
2(2 blocks : 0th and 1st)
255th)
12-15(256 blocks :
to
255th)
All blocks
Notes:
1. x is don’t care
2. For Optional 256KB BP Table, see the Ordering Information (Option “K”)
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6.2 FUNCTION REGISTER
Function Register Format and Bit definition are described in Table 6.5 and Table 6.6.
Table 6.5 Function Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
IRL3
IRL2
IRL1
IRL0
ESUS
PSUS
TBS
0
0
0
0
0
0
0
Default
Bit 0
Dedicated
RESET#
Disable
0 or 1
Table 6.6 Function Register Bit Definition
Bit
Name
Bit 0
Dedicated
RESET# Disable
Bit 1
TBS
Bit 2
PSUS
Bit 3
ESUS
Bit 4
IR Lock 0
Bit 5
IR Lock 1
Bit 6
IR Lock 2
Bit 7
IR Lock 3
Definition
Dedicated RESET# Disable bit
“0” indicates Dedicated RESET# was enabled
“1” indicates Dedicated RESET# was disabled
Top/Bottom Selection. (See Table 6.4 for details)
“0” indicates Top area.
“1” indicates Bottom area.
Program suspend bit:
“0” indicates program is not suspend
“1” indicates program is suspend
Erase suspend bit:
"0" indicates Erase is not suspend
"1" indicates Erase is suspend
Lock the Information Row 0:
“0” indicates the Information Row can be programmed
“1” indicates the Information Row cannot be programmed
Lock the Information Row 1:
“0” indicates the Information Row can be programmed
“1” indicates the Information Row cannot be programmed
Lock the Information Row 2:
“0” indicates the Information Row can be programmed
“1” indicates the Information Row cannot be programmed
Lock the Information Row 3:
“0” indicates the Information Row can be programmed
“1” indicates the Information Row cannot be programmed
Read
/Write
R/W for 0
R only for
1
Type
OTP
R/W
OTP
R
Volatile
R
Volatile
R/W
OTP
R/W
OTP
R/W
OTP
R/W
OTP
Note: Once OTP bits of Function Register are written to “1”, it cannot be modified to “0” any more.
Dedicated RESET# Disable bit: The default status of the bit is dependent on package type. The device with
dedicated RESET# (16-pin SOIC and 24-ball BGA) can be programmed to “1” to disable dedicated RESET#
function to move RESET# function to Hold#/RESET# pin (or ball). So the device with dedicated RESET# can be
used for dedicated RESET# application and HOLD#/RESET# application.
TBS bit: BP0~3 area assignment can be changed from Top (default) to Bottom by setting TBS bit to “1”.
However, once Bottom is selected, it cannot be changed back to Top since TBS bit is OTP. See Table 6.4 for
details.
PSUS bit: The Program Suspend Status bit indicates when a Program operation has been suspended. The PSUS
changes to “1” after a suspend command is issued during the program operation. Once the suspended Program
resumes, the PSUS bit is reset to “0”.
ESUS bit: The Erase Suspend Status bit indicates when an Erase operation has been suspended. The ESUS bit
is “1” after a suspend command is issued during an Erase operation. Once the suspended Erase resumes, the
ESUS bit is reset to “0”.
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IR Lock bit 0 ~ 3: The default is “0” so that the Information Row can be programmed. If the bit is set to “1”, it cannot
be changed back to “0” again since IR Lock bits are OTP.
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6.3 READ REGISTER AND EXTENDED REGISTER
Read Register format and bit definitions are described below. Read Register and Extended Read Register consist
of a pair of rewritable non-volatile register and volatile register, respectively. During power up sequence, volatile
register will be loaded with the value of non-volatile value.
6.3.1 READ REGISTER
Table 6.7 and Table 6.8 define all bits that control features in SPI/QPI modes. HOLD#/RESET# pin selection (P7)
bit is used to select HOLD# pin or RESET# pin in SPI mode when QE=“0” for the device with HOLD#/RESET#.
When QE=1 or in QPI mode, P7 bit setting will be ignored since the pin becomes IO3.
For 16-pin SOIC or 24-ball TFBGA with dedicated RESET# device, HOLD# will be selected regardless of P7 bit
setting when QE=“0” in SPI mode.
The Dummy Cycle bits (P6, P5, P4, P3) define how many dummy cycles are used during various READ modes.
The wrap selection bits (P2, P1, P0) define burst length with an enable bit.
The SET READ PARAMETERS Operations (SRPNV: 65h, SRPV: C0h or 63h) are used to set all the Read Register
bits, and can thereby define HOLD#/RESET# pin (or ball) selection, dummy cycles, and burst length with wrap
around. SRPNV is used to set the non-volatile register and SRPV is used to set the volatile register.
Table 6.7 Read Register Parameter Bit Table
Default
P7
HOLD#/
RESET#
0
P6
Dummy
Cycles
0
P5
Dummy
Cycles
0
P4
Dummy
Cycles
0
P3
Dummy
Cycles
0
P2
Wrap
Enable
0
P1
Burst
Length
0
P0
Burst
Length
0
Table 6.8 Read Register Bit Definition
Read/Write
Bit
Name
Definition
P0
Burst Length
Burst Length
R/W
P1
Burst Length
Burst Length
R/W
P2
Burst Length
Set Enable
Burst Length Set Enable Bit:
"0" indicates disable (default)
"1" indicates enable
R/W
P3
Dummy Cycles
P4
Dummy Cycles
P5
Dummy Cycles
P6
Dummy Cycles
P7
HOLD#/
RESET#
Type
Non-Volatile
and Volatile
Non-Volatile
and Volatile
Non-Volatile
and Volatile
Non-Volatile
and Volatile
Non-Volatile
and Volatile
Non-Volatile
and Volatile
Non-Volatile
and Volatile
R/W
Number of Dummy Cycles:
Bits1 to Bit4 can be toggled to select the number of dummy cycles
(1 to 15 cycles)
R/W
R/W
R/W
HOLD#/RESET# function selection Bit:
"0" indicates the HOLD# function is selected (default)
"1" indicates the RESET# function is selected
Non-Volatile
and Volatile
R/W
Table 6.9 Burst Length Data
P1
P0
8 bytes
0
0
16 bytes
0
1
32 bytes
1
0
64 bytes
1
1
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Table 6.10 Wrap Function
Wrap around boundary
P2
Whole array regardless of P1 and P0 value
0
Burst Length set by P1 and P0
1
Table 6.11 Read Dummy Cycles vs Max Frequency
3.0V Device (IS25LP)
P[6:3]
Dummy
Cycles2,3
1
Fast Read5 Fast Read5
0Bh/0Ch
0Bh/0Ch
Fast Read
Dual
Output
3Bh/3Ch
Fast Read
Dual IO
BBh/BCh
Fast Read
Quad
Output
6Bh/6Ch
Fast Read
Quad IO
EBh/ECh
FRDTR
0Dh/0Eh
FRDDTR
BDh/BEh
FRQDTR
EDh/EEh
SPI
QPI
SPI
SPI
SPI
SPI, QPI
SPI/QPI
SPI4
SPI, QPI
133MHz
75MHz
133MHz
84MHz
117MHz
75MHz
66/66MHz
60MHz
66MHz
66MHz
25MHz
66MHz
33MHz
50MHz
25MHz
50/11MHz
29MHz
11MHz
0
Default
1
1
2
2
84MHz
33MHz
84MHz
50MHz
66MHz
33MHz
63/23MHz
40MHz
23MHz
3
3
104MHz
40MHz
104MHz
66MHz
75MHz
40MHz
66/34MHz
52MHz
34MHz
4
4
110MHz
50MHz
110MHz
84MHz
84MHz
50MHz
66/46MHz
60MHz
46MHz
5
5
115MHz
66MHz
117MHz
90MHz
95MHz
66MHz
66/58MHz
66MHz
58MHz
6
6
120MHz
75MHz
125MHz
104MHz
104MHz
75MHz
66/66MHz
66MHz
66MHz
7
7
133MHz
84MHz
133MHz
108MHz
110MHz
84MHz
66/66MHz
66MHz
66MHz
8
8
133MHz
95MHz
133MHz
117MHz
117MHz
95MHz
66/66MHz
66MHz
66MHz
9
9
133MHz
104MHz
133MHz
133MHz
125MHz
104MHz
66/66MHz
66MHz
66MHz
10
10
133MHz
110MHz
133MHz
133MHz
133MHz
110MHz
66/66MHz
66MHz
66MHz
11
11
133MHz
117MHz
133MHz
133MHz
133MHz
117MHz
66/66MHz
66MHz
66MHz
12
12
133MHz
120MHz
133MHz
133MHz
133MHz
120MHz
66/66MHz
66MHz
66MHz
13
13
133MHz
125MHz
133MHz
133MHz
133MHz
125MHz
66/66MHz
66MHz
66MHz
14
14
133MHz
133MHz
133MHz
133MHz
133MHz
133MHz
66/66MHz
66MHz
66MHz
15
15
133MHz
133MHz
133MHz
133MHz
133MHz
133MHz
66/66MHz
66MHz
66MHz
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1.8V Device (IS25WP)
P[6:3]
Dummy
Cycles2,3
Fast Read5 Fast Read5
0Bh/0Ch
0Bh/0Ch
1
Fast Read
Dual
Output
3Bh/3Ch
Fast Read
Dual IO
BBh/BCh
Fast Read
Quad
Output
6Bh/6Ch
Fast Read
Quad IO
EBh/ECh
FRDTR
0Dh/0Eh
FRDDTR
BDh/BEh
FRQDTR
EDh/EEh
SPI
QPI
SPI
SPI
SPI
SPI, QPI
SPI/QPI
SPI4
SPI, QPI
112MHz
75MHz
112MHz
84MHz
112MHz
75MHz
66/66MHz
60MHz
66MHz
66MHz
25MHz
66MHz
33MHz
50MHz
25MHz
50/11MHz
29MHz
11MHz
0
Default
1
1
2
2
84MHz
33MHz
84MHz
50MHz
66MHz
33MHz
63/23MHz
40MHz
23MHz
3
3
104MHz
40MHz
104MHz
66MHz
75MHz
40MHz
66/34MHz
52MHz
34MHz
4
4
110MHz
50MHz
110MHz
84MHz
84MHz
50MHz
66/46MHz
60MHz
46MHz
5
5
112MHz
66MHz
112MHz
90MHz
95MHz
66MHz
66/58MHz
66MHz
58MHz
6
6
112MHz
75MHz
112MHz
104MHz
104MHz
75MHz
66/66MHz
66MHz
66MHz
7
7
112MHz
84MHz
112MHz
108MHz
110MHz
84MHz
66/66MHz
66MHz
66MHz
8
8
112MHz
93MHz
112MHz
112MHz
112MHz
93MHz
66/66MHz
66MHz
66MHz
9
9
112MHz
104MHz
112MHz
112MHz
112MHz
104MHz
66/66MHz
66MHz
66MHz
10
10
112MHz
110MHz
112MHz
112MHz
112MHz
112MHz
66/66MHz
66MHz
66MHz
11
11
112MHz
112MHz
112MHz
112MHz
112MHz
112MHz
66/66MHz
66MHz
66MHz
12
12
112MHz
112MHz
112MHz
112MHz
112MHz
112MHz
66/66MHz
66MHz
66MHz
13
13
112MHz
112MHz
112MHz
112MHz
112MHz
112MHz
66/66MHz
66MHz
66MHz
14
14
112MHz
112MHz
112MHz
112MHz
112MHz
112MHz
66/66MHz
66MHz
66MHz
15
15
112MHz
112MHz
112MHz
112MHz
112MHz
112MHz
66/66MHz
66MHz
66MHz
Notes:
1. Default dummy cycles are as follows.
Operation
Command
Dummy Cycles
SPI mode
QPI mode
SPI mode
QPI mode
Fast Read
0Bh/0Ch
0Bh/0Ch
8
6
Fast Read Dual Output
3Bh/3Ch
-
8
-
Fast Read Quad Output
6Bh/6Ch
-
8
-
Fast Read Dual IO
BBh/BCh
-
4
-
Fast Read Quad IO
EBh/ECh
EBh/ECh
6
6
Fast Read DTR
0Dh/0Eh
0Dh/0Eh
8
6
Fast Read Dual IO DTR
BDh/BEh
-
4
-
Fast Read Quad IO DTR
EDh/EEh
EDh/EEh
6
6
Comment
RDUID, IRRD instructions are also
applied.
2. Enough number of dummy cycles must be applied to execute properly the AX read operation.
3. Must satisfy bus I/O contention. For instance, if the number of dummy cycles and AX bits cycles are same, then X
must be Hi-Z.
4. QPI mode is not available for FRDDTR command.
5. RDUID, IRRD instructions are also applied.
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6.3.2 EXTENDED READ REGISTER
Table 6.12 and Table 6.13 define all bits that control features in SPI/QPI modes. The ODS2, ODS1, ODS0 (EB7,
EB6, EB5) bits provide a method to set and control driver strength. The three bits (EB3, EB2, EB1) are read-only
bits and may be checked to know whether there is an error during an Erase, Program, or Write/Set Register
operation. These bits are not affected by SERPNV or SERPV commands. EB0 bit remains reserved for future use.
The SET EXTENDED READ PARAMETERS Operations (SERPNV: 85h, SERPV: 83h) are used to set all the
Extended Read Register bits, and can thereby define the output driver strength used during READ modes. SRPNV
is used to set the non-volatile register and SRPV is used to set the volatile register.
Table 6.12 Extended Read Register Bit Table
Bit
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
Name
ODS2
ODS1
ODS0
DLPEN
E_ERR
P_ERR
PROT_E
Reserved
Default
1
1
1
0
0
0
0
0
Table 6.13 Extended Read Register Bit Definition
Bit
Name
EB0
Reserved
EB1
PROT_E
EB2
P_ERR
EB3
E_ERR
EB4
DLPEN
EB5
ODS0
EB6
ODS1
EB7
ODS2
Definition
Reserved
Protection Error Bit:
"0" indicates no error
"1" indicates protection error in an Erase or a Program operation
Program Error Bit:
"0" indicates no error
"1" indicates a Program operation failure or protection error
Erase Error Bit:
"0" indicates no error
"1" indicates an Erase operation failure or protection error
DLP Enable Bit
"0" indicates Disable
"1" indicates Enable
Read/Write
R
Reserved
R
Volatile
R
Volatile
R
Volatile
R/W
Non-Volatile
and Volatile
Non-Volatile
and Volatile
Non-Volatile
and Volatile
Non-Volatile
and Volatile
R/W
Output Driver Strength:
Output Drive Strength can be selected according to Table 6.14
Type
R/W
R/W
Table 6.14 Driver Strength Table
ODS2
ODS1
ODS0
Description
0
0
0
Reserved
0
0
1
12.50%
0
1
0
25%
0
1
1
37.50%
1
0
0
Reserved
1
0
1
75%
1
1
0
100%
1
1
1
50%
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PROT_E bit: The Protection Error bit indicates whether an Erase or Program operation has attempted to modify a
protected array sector or block, or to access a locked Information Row region. When the bit is set to “1” it indicates
that there was an error or errors in previous Erase or Program operations. See Table 6.15 for details.
P_ERR bit: The Program Error bit indicates whether a Program operation has succeeded or failed, or whether a
Program operation has attempted to program a protected array sector/block or a locked Information Row region.
When the bit is set to “1” it indicates that there was an error or errors in previous Program or Write/Set Non-Volatile
Register operations. See Table 6.15 for details.
E_ERR bit: The Erase Error bit indicates whether an Erase operation has succeeded or failed, or whether an Erase
operation has attempted to erase a protected array sector/block or a locked Information Row region. When the bit
is set to “1” it indicates that there was an error or errors in previous Erase or Write/Set Non-Volatile Register
operations. See Table 6.15 for details.
Table 6.15 Instructions to set PROT_E, P_ERR, or E_ERR bit
Instructions
Description
PP/4PP/PPQ/4PPQ/PGPPB/
4PGPPB/PGPWD
The commands will set the P_ERR if there is a failure in the operation. Attempting to program
within the protected array sector/block or within an erase suspended sector/block will result in
a programming error with P_ERR and PROT_E set to “1”.
IRP
The command will set the P_ERR if there is a failure in the operation. In attempting to program
within a locked Information Row region, the operation will fail with P_ERR and PROT_E set to
1.
PGASP
The command will set the P_ERR if there is a failure in the operation. Attempting to program
ASPR [2:1] after the Protection Mode is selected or attempting to program ASPR[2:1] = 00b
will result in a programming error with P_ERR and PROT_E set to “1”.
UNPWD
WRSR/SRPNV/
SERPNV/WRBRNV/PNVDLR
WRFR
SER/4SER/BER32K/
4BER32K/BER64K/
4BER64K/BER256K/4BER25
6K/CER/IRER/ERPPB
If the UNPWD command supplied password does not match the hidden internal password, the
UNPWD operation fails in the same manner as a programming operation on a protected
sector/block and sets the P_ERR and PROT_E to “1”.
The update process for the non-volatile register bits involves an erase and a program operation
on the non-volatile register bits. If either the erase or program portion of the update fails, the
related error bit (P_ERR or E_ERR) will be set to “1”.
Only for WRSR command, when Status Register is write-protected by SRWD bit and WP# pin,
attempting to write the register will set PROT_E and E_ERR to “1”.
The commands will set the P_ERR if there is a failure in the operation.
The commands will set the E_ERR if there is a failure in the operation. E_ERR and PROT_E
will be set to “1” when the user attempts to erase a protected main memory sector/block or a
locked Information Row region. Chip Erase (CER) command will set E_ERR and PROT_E if
any blocks are protected by Block Protection bits (BP3~BP0). But Chip Erase (CER) command
will not set E_ERR and PROT_E if sectors/blocks are protected by ASP (DYB bits or PPB bits)
only.
Notes:
1. OTP bits in the Function Register and TBPARM (OTP bit) in the ASP Register may only be programmed to “1”.
Writing of the bits back to “0” is ignored and no error is set.
2. Read only bits and partially protected bits by FREEZE bit in registers are never modified by a command so that the
corresponding bits in the Write/Set Register command data byte are ignored without setting any error indication.
3. Once the PROT_E, P_ERR, and E_ERR error bits are set to “1”, they remains set to “1” until they are cleared to “0”
with a Clear Extended Read Register (CLERP) command. This means that those error bits must be cleared through
the CLERP command. Alternatively, Hardware Reset, or Software Reset may be used to clear the bits.
4. Any further command will be executed even though the error bits are set to “1”.
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6.4 BANK ADDRESS REGISTER
Related Commands: Read Volatile Bank Address Register (RDBR 16h/C8h), Write Volatile Bank Address
Register (WRBRV 17h/C5h), Write Non-Volatile Bank Address Register (WRBRNV 18h), Enter 4-byte Address
Mode (EN4B B7h), and Exit 4-byte Address Mode (EX4B 29h).
Bank Address Register Bit (8 bits) definitions are described in Table 6.17 and Table 6.18.
Table 6.16 Bank Address Register Bit Table
BA7
BA6
BA5
BA4
BA3
BA2
BA1
BA0
EXTADD
Reserved
Reserved
Reserved
Reserved
Reserved
BA25
BA24
0
0
0
0
0
0
0
0
Read/Write
Type
R/W
Non-Volatile
and Volatile
Default
Table 6.17 Bank Address Register Bit Definition
Bit
Name
Definition
BA0
BA24
BA1
BA25
BA2
Reserved
Reserved
R
Reserved
BA3
Reserved
Reserved
R
Reserved
BA4
Reserved
Reserved
R
Reserved
BA5
Reserved
Reserved
R
Reserved
BA6
Reserved
R
Reserved
BA7
EXTADD
Reserved
3-byte or 4-byte addressing mode selection Bit:
"0" indicates 3-byte addressing mode
"1" indicates 4-byte addressing mode
R/W
Non-Volatile
and Volatile
Enables 128Mb segment selection in 3-byte addressing
512Mb : BA24 and BA25
BA24, BA25: The Bank Address Register supplies additional high order bits of the main flash array byte boundary
address for legacy commands based systems, which supply only the low order 24 bits of address. The Bank
Addresses are used as the high bits of address (above A23) for legacy 3-byte address commands when
EXTADD=0.
The Bank Address is not used when EXTADD = 1 and traditional 3-byte address commands are instead required
to provide all four bytes of address.
EXTADD: Extended Address (EXTADD) controls the address field size for legacy SPI commands. When shipped
from factory, it is cleared to “0” for 3-byte addressing mode.
When set to “1” for 4-byte addressing mode, the legacy commands will require 4 bytes of address for the address
field
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6.5 ADVANCED SECTOR/BLOCK PROTECTION (ASP) RELATED REGISTER
6.5.1
ADVANCED SECTOR/BLOCK PROTECTION REGISTER (ASPR)
Related Commands: Read ASP (RDASP 2Bh) and Program ASP (PGASP 2Fh).
Advanced Sector/Block Protection (ASP) Register Bit (16 bits) definitions are described in Tables 6.19 and 6.20.
Table 6.18 Advanced Sector/Block Protection Register (ASPR) Bit Table
15
TBPARM(1)
Default
1
14 to 7
Reserve
d
1
6
Reserve
d
1
5
Reserve
d
1
4
Reserve
d
1
3
Reserve
d
1
2
1
PWDMLB
PSTMLB
1
1
0
Reserve
d
1
Table 6.19 Advanced Sector/Block Protection Register (ASPR) Bit Definition
Bit
Name
0
Reserved
1
PSTMLB
2
PWDMLB
14:3
Reserved
15
TBPARM(1)
Note:
1. TBPARM
Definition
Reserved
Persistent Protection Mode Lock Bit
“0” = Persistent Protection Mode permanently enabled.
“1” = Persistent Protection Mode not permanently enabled.
Password Protection Mode Lock Bit
“0” = Password Protection Mode permanently enabled.
“1” = Password Protection Mode not permanently enabled.
Reserved
Configures Parameter Sectors location
“0” = 4KB physical sectors at top, (high address)
“1” = 4KB physical sectors at bottom (Low address)
Read/Write
R
Reserved
R/W
OTP
R/W
OTP
R
Reserved
R/W
OTP(1)
Type
bit is Reserved for optional block size of 256KB device
The Advanced Sector/Block Protection Register (ASPR) is used to permanently configure the behavior of Advanced
Sector/Block Protection (ASP) features and parameter sectors location.
PWDMLB (ASPR [2]) and PSTMLB (ASPR[1]) bits: When shipped from the factory, all devices default ASP to
the Persistent Protection Mode, with all sectors unprotected, when power is applied. The device programmer or
host system must then choose which sector/block protection method to use. Programming either of the Protection
Mode Lock Bits locks the part permanently in the selected mode:
ASPR [2:1] = 11 = No ASP mode selected, Persistent Protection Mode is the default.
ASPR [2:1] = 10 = Persistent Protection Mode permanently selected.
ASPR [2:1] = 01 = Password Protection Mode permanently selected.
ASPR [2:1] = 00 = Illegal condition, attempting to program both bits to zero results in a programming failure
and the program operation will abort. It will result in a programming error with P_ERR set to 1.
As a result, PWDMLB and PSTMLB are mutually exclusive, only one may be programmed to zero.
ASPR programming rules:
If the Password Protection Mode is chosen, the password must be programmed prior to setting the
corresponding bit.
Once the Protection Mode is selected, the ASPR [2:1] bits are permanently protected from programming and
no further change to the ASPR[2:1] is allowed. Attempting to program ASPR [2:1] after selected will result in a
programming error with P_ERR set to 1. The programming time of the ASPR is the same as the typical page
programming time. The system can determine the status of the ASPR programming operation by reading the
WIP bit in the Status Register.
TBPARM bit can be programmed even after ASPR [2:1] bits are programmed while the FREEZE bit in the PPB
Lock Register is “0”.
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TBPARM bit: TBPARM defines the logical location of the parameter block. The parameter block consists of thirtytwo 4KB sectors, which replace two 64KB blocks. When TBPARM is set to a “0” the parameter block is in the top
of the memory array address space. When TBPARM is set to a “1” the parameter block is at the Bottom of the
array. TBPARM is OTP and set to a “1” when it ships from Factory. If TBPARM is programmed to “0”, an attempt
to change it back to “1” will fail and ignore the Program.
The desired state of TBPARM must be selected during the initial configuration of the device during system
manufacture; before the first program or erase operation on the main flash array. TBPARM must not be
programmed after programming or erasing is done in the main flash array.
TBS can be programmed independent of TBPARM. Therefore, the user can select to store parameter information
from the bottom of the array and protect boot code starting at the top of the array, and vice versa. Or the user can
select to store and protect the parameter information starting from the top or bottom together.
Note: For optional device with block size of 256KB, there is no parameter blocks, so TBPARM bit is reserved.
6.5.2
PASSWORD REGISTER
Related Commands: Read Password (RDPWD E7h), Program Password (PGPWD E8h), and Unlock Password
(UNPWD, E9h).
Table 6.20 Password Register Bit Definition
Bit
Name
63:0
PSWD
6.5.3
Definition
64 bit hidden password:
The password is no longer readable after the password
protection mode is selected by programming ASPR bit 2
to zero.
Default
Read/Write
Type
FFFFFFFFFFFFFFFFh
R/W
OTP
PPB LOCK REGISTER
Related Commands: Read PPB Lock Bit (RDPLB A7h), Write PPB Lock Bit (WRPLB A6h), and Set FREEZE Bit
(SFRZ 91h).
Table 6.21 PPB Lock Register Bit Definition
Bit
Name
0
PPBLK
6:1
Reserved
7
FREEZE
Definition
PPB Lock bit: Protect PPB Array
“0” = PPB array protected until next power cycle
or Hardware Reset
“1” = PPB array may be programmed or erased.
Reserved
Lock current state of BP3-0 bits in Status Register, TBS in
Function Register and TBPARM in ASPR, and
Information Row (IR) regions.
“1” = Locked
“0” = Un-locked
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Default
Read/Write
Type
Persistent: 1
Password: 0
R/W
Volatile
R
Reserved
R/W
Volatile
Reserved
0
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PPBLK bit: The PPB Lock bit is a volatile bit for protecting all PPB bits. When cleared to 0, it locks all PPBs, when
set to 1, it allows the PPBs to be changed. The WRPLB command is used to clear the PPB Lock bit to 0. The PPB
Lock bit must be cleared to 0 only after all the PPBs are configured to the desired settings.
In Persistent Protection mode, the PPB Lock bit is set to 1 during POR or Hardware Reset. When cleared to 0, no
software command sequence can set the PPB Lock bit to 1, only another Hardware Reset or power-up can set the
PPB Lock bit.
In the Password Protection mode, the PPB Lock bit is cleared to 0 during POR or Hardware Reset. The PPB Lock
bit can only be set to 1 by the Unlock Password command.
FREEZE bit: FREEZE bit, when set to “1”, locks the current state of BP3-0 in Status Register, TBS in the Function
Register, TBPARM in the Advanced Sector/Block Protection Register, and the Information Row. This prevents
writing, programming, or erasing these areas. As long as FREEZE remains cleared to logic “0”, BP3-0 in Status
Register, TBS in the Function Register, and TBPARM in the Advanced Sector/Block Protection Register are
writable and the Information Row is programmable. Once FREEZE has been written to a logic “1” it can only be
cleared to a logic “0” by a power-on cycle or a Hardware Reset. Software Reset will not affect the state of FREEZE.
The FREEZE is volatile and the default state of FREEZE after power-on is “0”. The FREEZE can be set to “1” by a
SFRZ command.
6.5.4 PB REGISTER
Related Commands: Read PPB (RDPPB FCh or 4RDPPB E2h)), Program PPB (PGPPB FDh or 4PGPPB E3h),
and Erase PPB (ERPPB E4h).
Table 6.22 PPB Register Bit Definition
Bit
7:0
6.5.5
Name
Definition
Default
Read/Write
Type
PPB
Read or Program per sector/block PPB:
00h = PPB for the sector/block addressed by the RDPPB or
PGPPB command is programmed to “0”, protecting
that sector/block from program or erase operations.
FFh = PPB for the sector/block addressed by the RDPPB
or
PGPPB command is erased to “1”, not protecting
that sector/block from program or erase operations.
FFh
R/W
Non-Volatile
DYB REGISTER
Related Commands: Read DYB (RDDYB FAh or 4RDDYB E0h) and Write DYB (WRDYB FBh or 4WRDYB E1h).
Table 6.23 DYB Register Bit Definition
Bit
7:0
Name
DYB
Definition
Read or Write per sector/block DYB:
00h = DYB for the sector/block addressed by the RDDYB
or
WRDYB command is cleared to “0”, protecting that
sector/block from program or erase operations.
FFh = DYB for the sector/block addressed by the RDDYB
or
WRDYB command is set to “1”, not protecting that
sector/block from program or erase operations.
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Default
Read/Write
Type
FFh
R/W
Volatile
36
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6.5.6
DATA LEARNING PATTERN REGISTER
Related Commands: Read DLP (RDDLP 41h), Program Non-Volatile DLP Register (PNVDLR 43h), Write Volatile
DLP Register (WRVDLR 4Ah).
The Data Learning Pattern (DLP) resides in an 8-bit NON-Volatile Data Learning Register (NVDLR) as well as an
8-bit Volatile Data Learning Register (VDLR). When shipped from the factory, default value is 00h.
A copy of the data pattern in NVDLR will also be written to the VDLR. The VDLR can be written to at any time, but
on power cycles the data pattern will return back to data pattern in NVDLR.
During Data Training phase, DLP will come from VDLR.
Table 6.24 Non-Volatile Data Learning Register (NVDLR)
Bit
7:0
Name
Definition
Default
Read/Write
Type
NVDLP
Non-Volatile Data Learning Pattern:
The value that may be transferred to the host during DDR
read command latency (dummy) cycles to provide a training
pattern to help the host more accurately center the data
capture point in the received data bits.
00h
R/W
Non-Volatile
Default
Read/Write
Type
Takes the
value of
NVDLR
during POR or
Reset
R/W
Volatile
Table 6.25 Volatile Data Learning Register (VDLR)
Bit
7:0
Name
VDLP
Definition
Volatile Data Learning Pattern:
Volatile copy of the NVDLP used to enable and deliver
the
Data Learning Pattern to the outputs. The VDLP may be
changed by the host during system operation.
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7. PROTECTION MODE
The device supports hardware and software write-protection mechanisms.
7.1 HARDWARE WRITE PROTECTION
The Write Protection (WP#) pin provides a hardware write protection method for BP3, BP2, BP1, BP0, SRWD, and
QE in the Status Register. Refer to the section 6.1 STATUS REGISTER.
Write inhibit voltage (VWI) is specified in the section 9.8 POWER-UP AND POWER-DOWN. All write sequence will
be ignored when Vcc drops to VWI.
Table 7.1 Hardware Write Protection on Status Register
SRWD
WP#
Status Register
0
Low
Writable
1
Low
Protected
0
High
Writable
1
High
Writable
Note: Before the execution of any program, erase or Write Status/Function Register instruction, the Write Enable Latch
(WEL) bit must be enabled by executing a Write Enable (WREN) instruction. If the WEL bit is not enabled, the
program, erase or write register instruction will be ignored.
7.2 SOFTWARE WRITE PROTECTION
The device also provides two kinds of software write protection feature. One is Block Protection by Block Protection
bits (BP3, BP2, BP1, BP0) and another is Advanced Sector/Block Protection (ASP). When Block Protection is
enabled (i.e., any BP3-0 are set to “1”), Advanced Sector/Block Protection (ASP) can still be used to protect
sectors/blocks not protected by the Block Protection scheme. In the case that both ASP and Block Protection are
used on the same sector/block the logical OR of ASP and Block Protection related to the sector/block is used.
Warning: ASP and Block Protection should not be used concurrently. Use one or the other, but not both.
7.2.1 BLOCK PROTECTION BITS
The device provides a software write protection feature. The Block Protection bits (BP3, BP2, BP1, BP0) allow part
or the whole memory area to be write-protected. For details, see 6.1 Status Register.
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7.2.2 ADVANCED SECTOR/BLOCK PROTECTION (ASP)
There are two ways to implement software Advanced Sector/Block Protection on this device: Password Protection
method or Persistent Protection methods. Through these two protection methods, user can disable or enable the
programming or erasing operation to any or all blocks including 32 top 4K sectors or 32 bottom 4K sectors when
block size is 64KB. When block size is uniform 256KB, there will be no 32 4KB parameter blocks.
The Figure 7.1 shows an overview of these methods
Every main flash array block/top sector/bottom sector has a non-volatile (PPB) and a volatile (DYB) protection bit
associated with it. When either bit is 0, the sector is protected from program and erase operations.
The PPB bits are protected from program and erase when the PPB Lock bit is “0”. The PPB bits are erased so that
all main flash array sectors are unprotected when shipped from factory.
There are two methods for managing the state of the PPB Lock bit, Persistent Protection and Password Protection.
The Persistent Protection Mode sets the PPB Lock bit to “1” during power up or Hardware Reset so that the PPB
bits are unprotected. There is a WRPLB command to clear the PPB Lock bit to “0” to protect the PPB bits. There
is no command in the Persistent Protection method to set the PPB Lock bit therefore the PPB Lock bit will remain
at “0” until the next power up or Hardware Reset. The Persistent Protection method allows boot code the option of
changing sector protection by programming or erasing the PPB, then protecting the PPB from further change for
the remainder of normal system operation by clearing the PPB Lock bit. This is sometimes called Boot-code
controlled sector protection.
The Password Protection Mode requires use of a password to control PPB protection. In the Password Protection
Mode, the PPB Lock bit is cleared to “0” during power up or Hardware Reset to protect the PPB bits. A 64-bit
password may be permanently programmed and hidden for the Password Protection Mode. The UNPWD command
can be used to provide a password for comparison with the hidden password. If the password matches the PPB
Lock bit is set to “1” to unprotect the PPB. The WRPLB command can be used to clear the PPB Lock bit to “0”.
After clearing the PPB Lock bit to “0”, the UNPWD command can be used again to unprotect the PPB.
The selection of the PPB Lock bit management method is made by programming OTP bits in the ASP Register so
as to permanently select the method used.
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Figure 7.1 Advanced Sector/Block Protection
ASP Register Bits (OTP)
Password Protection
Mode (ASPR[2]=0
Persistent Protection
Mode (ASPR[1]=0
64-bit Password
(OTP)
PPB Lock Bit
(Volatile)
0 = Locked 1 = Unocked
DYB
Memory Array
PPB
DYB 0
Sector/Block 0
PPB 0
DYB 1
Sector/Block 1
PPB 1
DYB 2
Sector/Block 2
PPB 2
DYB 3
Sector/Block 3
PPB 3
DYB N-3
Sector/Block N-3
PPB N-3
DYB N-2
Sector/Block N-2
PPB N-2
DYB N-1
Sector/Block N-1
PPB N-1
DYB N
Sector/Block N
PPB N
1. 0 = Sector/Block Protected
1 = Sector/Block Unprotected (default)
2. DYBs are volatile and defaults to “1”
after power-up
1. The bit defaults to “1” (Persistent Protection mode)
or “0” (Password Protection mode) upon reset.
2. “0” locks all PPB bits to their current state.
3. Password Protection mode requires a password to
set PPB Lock bit to “1” to enable program or
erase of PPB bits.
4. Persistent Protection mode only allows PPB Lock
bit to be cleared to “0” to prevent program or erase
PPB bits. Power off or hardware reset is required to
set PPB Lock bit to “1”.
1. 0 = Sector/Block Protected
1 = Sector/Block Unprotected
2. PPB bits are programmed individually,
but erased collectively
Notes:
1. 512M (64KB Block): N = 1053 = 32 (32xTop 4KB sectors or 32xBottom 4KB sectors) + 1022 (1022x64KB blocks) - 1
2. 512M (256KB Block): N = 255 = 0 + 256 (256x256KB blocks) - 1
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Table 7.2 PPB/DYB and Sector/Block mapping when Block Size is 64KB (TBPARM = 1)
Memory
Density
PPB
Group
DYB
Group
Block No.
(64Kbyte)
PPB 0
:
DYB 0
:
:
PPB 15
PPB 16
:
:
PPB 31
:
DYB 15
DYB 16
:
:
DYB 31
PPB 32
DYB 32
Block 2
:
:
:
Block 0
Block 1
PPB 540
DYB 540
Block 510
PPB 541
DYB 541
Block 511
:
:
:
512Mb
PPB 1052
PPB 1053
DYB 1052
DYB 1053
Block 1022
Block 1023
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Sector 0
:
Sector
Size
(Kbyte)
4
:
000 0000h – 000 0FFFh
:
:
Sector 15
Sector 16
:
:
Sector 31
Sector 32
:
:
Sector 47
:
4
4
:
:
4
4
:
:
4
:
000 F000h – 000 FFFFh
001 0000h – 001 0FFFh
:
:
001 F000h – 001 FFFFh
002 0000h – 002 0FFFh
:
:
002 F000h – 002 FFFFh
:
:
:
Sector 8160
:
:
Sector 8175
Sector 8176
:
:
Sector 8191
4
:
:
4
4
:
:
4
1FE 0000h – 1FE 0FFFh
:
:
1FE F000h – 1FE FFFFh
1FF 0000h – 1FF 0FFFh
:
:
1FF F000h – 1FF FFFFh
:
:
:
4
3FE 0000h – 3FE 0FFFh
:
:
:
4
3FE F000h – 3FE FFFFh
4
3FF 0000h – 3FF 0FFFh
:
:
:
4
3FF F000h – 3FF FFFFh
Sector No.
Sector
16352
:
:
Sector
16367
Sector
16368
:
:
Sector
16383
Address Range
:
:
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Table 7.3 PPB/DYB and Sector/Block mapping when Block Size is 64KB
Memory
Density
PPB
Group
DYB
Group
Block No.
(64Kbyte)
(TBPARM = 0)
Sector 0
:
Sector
Size
(Kbyte)
4
:
000 0000h – 000 0FFFh
:
:
Sector 15
Sector 16
:
:
Sector 31
Sector 32
:
:
Sector 47
:
4
4
:
:
4
4
:
:
4
:
000 F000h – 000 FFFFh
001 0000h – 001 0FFFh
:
:
001 F000h – 001 FFFFh
002 0000h – 002 0FFFh
:
:
002 F000h – 002 FFFFh
Sector No.
Address Range
PPB 0
DYB 0
Block 0
PPB 1
DYB 1
Block 1
PPB 2
DYB 2
Block 2
:
:
:
:
:
:
:
:
:
:
:
:
Sector 8176
:
:
Sector 8191
:
4
:
:
4
:
1FF 0000h – 1FF 0FFFh
:
:
1FF F000h – 1FF FFFFh
:
:
:
:
4
3FE 0000h – 3FE 0FFFh
:
:
:
:
4
3FE F000h – 3FE FFFFh
4
3FF 0000h – 3FF 0FFFh
:
:
:
:
4
3FF F000h – 3FF FFFFh
512Mb
PPB 511
DYB 511
Block 511
:
:
:
:
:
:
PPB 1022
DYB 1022
:
:
:
:
PPB 1037
DYB 1037
PPB 1038
DYB 1038
:
:
:
:
PPB 1053
DYB 1053
Block 1022
Block 1023
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Sector
16352
:
:
Sector
16367
Sector
16368
:
:
Sector
16383
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Table 7.4 PPB/DYB and Sector/Block mapping when Block Size is 256KB (TBPARM bit is Reserved)
Memory
Density
PPB Group
DYB Group
Block No.
(256Kbyte)
Sector No.
Sector 0
:
:
Sector 15
Sector 16
512Mb
PPB 0
DYB 0
Block 0
:
:
:
PPB 127
:
PPB 255
DYB 127
:
DYB 255
Block 127
:
Block 255
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Sector Size
(Kbyte)
4
:
:
4
4
Address Range
000 0000h – 000 0FFFh
:
:
000 F000h – 000 FFFFh
001 0000h – 001 0FFFh
:
:
Sector 31
Sector 32
:
:
Sector 47
Sector 48
:
:
Sector 63
:
:
4
4
:
:
4
4
:
:
:
:
001 F000h – 001 FFFFh
002 0000h – 002 0FFFh
:
:
002 F000h – 002 FFFFh
003 0000h – 003 0FFFh
:
:
03 F000h – 03 FFFFh
:
:
:
Sector 8128
:
:
Sector 8143
4
:
:
4
1FC0000h – 1F C0FFFh
:
:
1FC F000h – 1FC FFFFh
:
:
:
Sector 8176
:
:
Sector 8191
4
:
:
4
1FF 0000h – 1FF 0FFFh
:
:
1FF F000h – 1FF FFFFh
:
:
:
Sector 16320
:
:
Sector 16335
Sector 16336
:
:
Sector 16351
Sector 16352
:
:
4
:
:
4
4
:
:
4
4
:
:
3FC 0000h – 3FC 0FFFh
:
:
3FC F000h – 3FC FFFFh
3FD 0000h – 3FD 0FFFh
:
:
3FD F000h – 3FD FFFFh
3FE 0000h – 3FE 0FFFh
:
:
Sector 16367
Sector 16368
:
:
Sector 16383
4
4
:
:
4
3FE F000h – 3FE FFFFh
3FF 0000h – 3FF 0FFFh
:
:
3FF F000h – 3FF FFFFh
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Persistent Protection Bits (PPBs)
The Persistent Protection Bits (PPBs) are unique for each sector/block and non-volatile (refer to Figure 7.1, Table
7.2, and Table 7.3). It is programmed individually but must be erased as a group, similar to the way individual words
may be programmed in the main array but an entire sector/block must be erased at the same time. The PPBs have
the same endurances as the Flash memory. Preprogramming and verification prior to erasure are handled by the
device, and therefore do not require system monitoring. Programming a PPB bit requires the typical page
programming time. Erasing all the PPBs requires typical sector erase time. During PPB bit programming and PPB
bit erasing, status is available by reading the Status Register. Reading of a PPB bit requires the initial access time
of the device.
Notes:
1. Each PPB is individually programmed to “0” and all are erased to “1” in parallel.
2. The PPB Lock bit must be cleared first before changing the status of a PPB.
3. While programming PPB, array data cannot be read from any sectors/blocks.
4. When reading the PPB of the desired sector/block the address should be location zero within the sector/block. The high
order address bits not used must be zero.
5. There are no means for individually erasing a specific PPB and no specific sector/block address is required for this operation.
6. The state of the PPB for a given sector/block can be verified by using a PPB Read command.
7. When the parts are first shipped, the PPBs are cleared (erased to “1”).
Dynamic Protection Bits (DYBs)
Dynamic Protection Bits (DYBs) are volatile and unique for each sector/block and can be individually modified.
DYBs only control the protection for unprotected sectors/blocks that have their PPBs cleared (erased to “1”). By
issuing the Write DYB command, the DYBs are cleared to “0” or set to “1”, thus placing each sector/block in the
protected or unprotected state respectively. This feature allows software to easily protect sectors/blocks against
inadvertent changes, yet does not prevent the easy removal of protection when changes are needed. The DYBs
can be set or cleared as often as needed as they are volatile bits.
Persistent Protection Bit (PPB) Lock Bit
The PPB Lock bit is a volatile bit for protecting all PPB bits. When cleared to “0”, it locks all PPBs and when set to
“1”, it allows the PPBs to be changed. . If the PPB Lock bit is “0”, the PPB Program or Erase command does not
execute and fails without programming or erasing the PPB.
In Persistent Protection mode, the PPB Lock bit is set to “1” during power up or Hardware Reset. When cleared to
“0”, no software command sequence can set the PPB Lock bit to “1”, only another Hardware Reset or power-up
can set the PPB Lock bit.
In the Password Protection mode, the PPB Lock bit is cleared to “0” during power up or a Hardware Reset during
power up or a Hardware Reset during power up or a Hardware Reset. The PPB Lock bit can only be set to “1” by
the Password Unlock command.
The PPB Lock bit must be cleared to “0” only after all PPBs are configured to the desired settings.
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Sector/Block Protection States Summary
Each sector in specific blocks and each of all other blocks except for the specific blocks can be in one of the
following protection states:
Unlocked – The sector/block is unprotected and protection can be changed by a simple command. The
protection state defaults to unprotected after a power cycle, software reset, or hardware reset.
Dynamically Locked – A sector/block is protected and protection can be changed by a simple command. The
protection state is not saved across a power cycle.
Persistently Locked – A sector/block is protected and protection can only be changed if the PPB Lock bit is set
to “1”. The protection state is non-volatile and saved across a power cycle or reset. Changing the protection
state requires programming and or erase of the PPB bits.
Table 7.5 contains all possible combinations of the DYB, PPB, and PPB Lock bit relating to the status of the
sector/block. In summary, if the PPB Lock bit is locked (cleared to “0”), no changes to the PPBs are allowed. The
PPB Lock bit can only be unlocked (set to “1”) through a Hardware Reset or power cycle.
Table 7.5 Sector/Block Protection States
Protection Bit values
DYB
1
1
Unprotected
1
0
Protected
0
1
Protected
0
0
Protected
1
Changeable
Changeable
0
NOT changeable
Changeable
“0” = Locked or Protected
“1” = Unlocked or Unprotected
PPB Lock Bit
Assigned Sector/Block State
PPB
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Persistent Protection Mode
The Persistent Protection Mode sets the PPB Lock bit to “1” during power up or Hardware Reset so that the PPB
bits are unprotected by a device Hardware Reset. Software Reset does not affect the PPB Lock bit. The WRPLB
command can clear the PPB Lock bit to “0” to protect the PPB. There is no command to set the PPB Lock bit
therefore the PPB Lock bit will remain at “0” until the next power up or Hardware Reset.
Password Protection Mode
The Password Protection Mode allows an even higher level of security than the Persistent Protection Mode by
requiring a 64-bit password for unlocking the device PPB Lock bit. In addition to this password requirement, after
power up or Hardware Reset, the PPB Lock bit is cleared to “0” to maintain the password mode of operation.
Successful execution of the Unlock Password command by entering the entire password sets the PPB Lock bit to
“1”, allowing for sector/block PPBs modifications.
Notes:
1. The password is all “1”s when shipped from Factory. It is located in its own memory space and is accessible through the use
of the Program Password and Read Password commands.
2. Once the Password is programmed and verified, the Password Protection Mode Lock Bit (ASPR[2]=0) in ASP Register must
be programmed in order to prevent reading or modifying the password. After the Password Protection Mode Lock Bit is
programmed, all further Program and Read commands to the password region are disabled and these commands are
ignored so that there is no means to verify what the password is. Password verification is only allowed before selecting the
Password Protection Mode.
3. The Program Password Command is only capable of programming “0”s. Programming a “1” after a cell is programmed as a
“0” results in the cell left as a “0” with no programming error.
4. All 64-bit password combinations are valid as a password.
5. The Protection Mode Lock Bits in ASP Register are not erasable because they are OTP.
6. The exact password must be entered in order for the unlocking function to occur. If the password provided by Unlock
Password command does not match the hidden internal password, the unlock operation fails in the same manner as a
programming operation on a protected sector/block. The P_ERR and PROT_E are set to 1 and the PPB Lock bit remains
cleared to 0. In this case it is a failure to change the state of the PPB Lock bit because it is still protected by the lack of a
valid password.
7. The Unlock Password command cannot be accepted any faster than once every 100μs ± 20μs. This makes it take an
unreasonably long time (58 million years) for a hacker to run through all the 64-bit combinations in an attempt to correctly
match a password. The Read Status Register command may be used to read the WIP bit to determine when the device has
completed the Unlock Password command or is ready to accept a new password command. When a valid password is
provided the Unlock Password command does not insert the 100μs delay before returning the WIP bit to zero.
8. If the password is lost after selecting the Password Protection Mode, there is no way to set the PPB Lock bit.
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8. DEVICE OPERATION
8.1 COMMAND OVERVIEW
The device utilizes an 8-bit instruction register. Refer to Table 8.4. Instruction Set for details on instructions and
instruction codes. All instructions, addresses, and data are shifted in with the most significant bit (MSB) first on
Serial Data Input (SI) or Serial Data IOs (IO0, IO1, IO2, IO3). The input data on SI or IOs is latched on the rising
edge of Serial Clock (SCK) for normal mode and both of rising and falling edges for DTR mode after Chip Enable
(CE#) is driven low (VIL). Every instruction sequence starts with a one-byte instruction code and is followed by
address bytes and/or dummy cycles (configurable) and/or data bytes, depending on the type of instruction. CE#
must be driven high (VIH) after the last bit of the instruction sequence has been shifted in to end the operation.
Commands are structured as follows:
Each command begins with a byte (eight bits) instruction.
The instruction may be stand alone or may be followed by address bits to select a location within one of several
address spaces in the device. The address may be either a 24-bit or 32-bit byte boundary address.
The SPI interface with Multiple IO provides the option for each transfer of address and data information to be
done one, two, or four bits in parallel. This enables a tradeoff between the number of signal connections (IO bus
width) and the speed of information transfer. If the host system can support a two or four bit wide IO bus the
memory performance can be increased by using the instructions that provide parallel two bit (dual) or parallel
four bit (quad) transfers.
The width of all transfers following the instruction are determined by the instruction sent.
All single bit or parallel bit groups are transferred in most to least significant bit order.
Some instructions send Mode Bits following the address to indicate that the next command will be of the same
type with an implied, rather than an explicit, instruction. The next command thus does not provide an instruction
byte, only a new address and mode bits. This reduces the time needed to send each command when the same
command type is repeated in a sequence of commands.
The address or Mode Bits may be followed by Dummy Cycles before read data is returned to the host.
Dummy Cycles may be zero to several SCK cycles. In fact, Mode Bits will be counted as a part of Dummy
Cycles.
All instruction, address, Mode, and data information is transferred in byte granularity. Addresses are shifted into
the device with the Most Significant Byte first. All data is transferred with the lowest address byte sent first.
Following bytes of data are sent in lowest to highest byte address order i.e. the byte address increments.
All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations)
are ignored. The embedded operation will continue to execute without any affect. A very limited set of commands
are accepted during an embedded operation. These are discussed in the individual command descriptions.
While a program, erase, or write operation is in progress, it is recommended to check that the Write In Progress
(WIP) bit is “0” before issuing most commands to the device, to ensure the new command can be accepted.
Depending on the command, the time for execution varies. A command to read status information from an
executing command is available to determine when the command completes execution and whether the
command was successful.
Following are some general signal relationship descriptions to keep in mind.
– The host always controls the Chip Enable (CE#), Serial Clock (SCK), and Serial Input (SI) - SI for single bit
wide transfers. The memory drives Serial Output (SO) for single bit read transfers. The host and memory
alternately drive the IO0-IO3 signals during Dual and Quad transfers.
– All commands begin with the host selecting the memory by driving CE# low before the first rising edge of
SCK. CE# is kept low throughout a command and when CE# is returned high the command ends.
Generally, CE# remains low for 8-bit transfer multiples to transfer byte granularity information. All commands
will not be accepted if CE# is returned high not at an 8-bit boundary.
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IS25LP512M
IS25WP512M
8.2 COMMAND SET SUMMARY
Extended Addressing
To accommodate addressing above 128Mb (24-bit) for read, erase, write and program operations, there are three
options:
1. New 4-byte (32-bit) address instructions.
New 4-byte instructions are valid in both 4-byte addressing mode and 3-byte addressing mode. See Table 8.2.
2. 4-byte addressing mode with legacy 3-byte address instructions.
There are 2 ways to enter into 4-byte addressing mode.
- The device can be set to 4-byte addressing mode by setting EXTADD bit = “1” in the Bank Address Register
(BAR[7])
- If EXTADD bit is set to “0” (3-byte addressing mode), also the device can be switched to 4-byte addressing
mode by issuing Enter 4-byte Address Mode Command See Table 8.3.
- BA24, BA25 bits are ignored in 4-byte addressing mode
3. 3-byte addressing mode with the 3-byte address instructions:
The device can be set to 3-byte addressing mode by setting EXTADD bit = “0” in the Bank Address Register
(BAR [7])
BA24, BA25 select individual bank (128Mb) in 3-byte addressing mode.
3-byte address selects an address within the bank (128Mb)
The host system writes the Bank Address Register to access beyond the first 128Mbit of memory.
Bank Address Register bits are volatile.
o On power up, the default is Bank0 (the lowest address 16 Mbytes).
For Read, the device will continuously transfer out data until the end of the array.
o There is no bank to bank delay.
o The Bank Address Register is not updated.
o The Bank Address Register value is used only for the initial address of an access.
Table 8.1 Bank Address Map
512Mb
BA[25:24]
Bank
00
0
0000 0000h
00FF FFFFh
01
1
0100 0000h
01FF FFFFh
10
2
0200 0000h
02FF FFFFh
11
3
0300 0000h
03FF FFFFh
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Memory Array Address Range
48
IS25LP512M
IS25WP512M
Table 8.2 New Instruction Set with 4-byte address
Instruction Name
Operation
Code
Address Mode
4NORD
4-byte Address Normal Read Mode
13h
4-byte Address
4FRD
4-byte Address Fast Read Mode
0Ch
4-byte Address
4FRDIO
4-byte Address Fast Read Dual I/O
BCh
4-byte Address
4FRDO
4-byte Address Fast Read Dual Output
3Ch
4-byte Address
4FRQIO
4-byte Address Fast Read Quad I/O
ECh
4-byte Address
4FRQO
4-byte Address Fast Read Quad Output
6Ch
4-byte Address
4FRDTR
4-byte Address Fast Read DTR Mode
0Eh
4-byte Address
4FRDDTR
4-byte Address Fast Read Dual I/O DTR
BEh
4-byte Address
4FRQDTR
4-byte Address Fast Read Quad I/O DTR
EEh
4-byte Address
4PP
4-byte Address Serial Input Page Program
12h
4-byte Address
4PPQ
4-byte Address Quad Input Page Program
34h/3Eh
4-byte Address
4SER
4-byte Address Sector Erase
21h
4-byte Address
4BER32 (32KB)
4-byte Address Block Erase 32KB
5Ch
4-byte Address
4BER64/256
(64/256KB)
4-byte Address Block Erase 64KB
DCh
4-byte Address
4SECUNLOCK
4-byte Address Sector Unlock
25h
4-byte Address
4RDDYB
4-byte Address Read DYB
E0
4-byte Address
4WRDYB
4-byte Address Write DYB
E1
4-byte Address
4RDPPB
4-byte Address Read PPB
E2
4-byte Address
4PGPPB
4-byte Address Program PPB
E3
4-byte Address
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IS25LP512M
IS25WP512M
Table 8.3 Instruction Set with 3-byte or 4-byte address according to EXTADD Bit setting
Address Mode
Instruction Name
NORD
Operation
Normal Read Mode
Code
EXTADD (BAR[7] = 1
EXTADD (BAR[7]) = 0
03h
4-byte Address
3-byte Address
FRD
Fast Read Mode
0Bh
4-byte Address
3-byte Address
FRDIO
Fast Read Dual I/O
BBh
4-byte Address
3-byte Address
FRDO
Fast Read Dual Output
3Bh
4-byte Address
3-byte Address
FRQIO
Fast Read Quad I/O
EBh
4-byte Address
3-byte Address
FRQO
Fast Read Quad Output
6Bh
4-byte Address
3-byte Address
FRDTR
Fast Read DTR Mode
0Dh
4-byte Address
3-byte Address
FRDDTR
Fast Read Dual I/O DTR
BDh
4-byte Address
3-byte Address
FRQDTR
Fast Read Quad I/O DTR
EDh
4-byte Address
3-byte Address
PP
Serial Input Page Program
02h
4-byte Address
3-byte Address
PPQ
Quad Input Page Program
32h/38h
4-byte Address
3-byte Address
SER
Sector Erase
D7h/20h
4-byte Address
3-byte Address
BER32 (32KB)
Block Erase 32KB
52h
4-byte Address
3-byte Address
BER64 (64KB/256KB)
Block Erase 64KB/256KB
D8h
4-byte Address
3-byte Address
SECUNLOCK
Sector Unlock
26h
4-byte Address
3-byte Address
RDDYB
Read DYB
FA
4-byte Address
3-byte Address
WRDYB
Write DYB
FB
4-byte Address
3-byte Address
RDPPB
Read PPB
FC
4-byte Address
3-byte Address
PGPPB
Program PPB
FD
4-byte Address
3-byte Address
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IS25LP512M
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Table 8.4 All Instruction Set
Instruction
Name
Operation
Mode
Byte0
Byte1
Byte2
Byte3
Byte4
NORD
Normal Read
Mode
(3-byte Address)
SPI
03h
A
A
A
Data out
NORD
Normal Read
Mode
(4-byte Address)
SPI
03h
A
A
A
A
Data out
4NORD
4-byte Address
Normal Read
Mode
SPI
13h
A
A
A
A
Data out
FRD
Fast Read
Mode
(3-byte Address)
SPI
QPI
0Bh
A
A
A
Dummy(1)
Byte
Data out
FRD
Fast Read
Mode
(4-byte Address)
SPI
QPI
0Bh
A
A
A
A
Dummy(1)
Byte
Data out
4FRD
4-byte Address
Fast Read
Mode
SPI
QPI
0Ch
A
A
A
A
Dummy(1)
Byte
Data out
FRDIO
Fast Read
Dual I/O
(3-byte Address)
SPI
BBh
A
Dual
A
Dual
A
Dual
AXh(1),(2)
Dual
Dual
Data out
FRDIO
Fast Read
Dual I/O
(4-byte Address)
SPI
BBh
A
A
Dual
A
Dual
A
Dual
AXh(1),(2)
Dual
Dual
Data out
4FRDIO
4-byte Address
Fast Read
Dual I/O
SPI
BCh
A
A
Dual
A
Dual
A
Dual
AXh(1),(2)
Dual
Dual
Data out
FRDO
Fast Read
Dual Output
(3-byte Address)
SPI
3Bh
A
A
A
Dummy(1)
Byte
Dual
Data out
FRDO
Fast Read
Dual Output
(4-byte Address)
SPI
3Bh
A
A
A
A
Dummy(1)
Byte
Dual
Data out
4FRDO
4-byte Address
Fast Read
Dual Output
SPI
3Ch
A
A
A
A
Dummy(1)
Byte
Dual
Data out
FRQIO
Fast Read
Quad I/O
(3-byte Address)
SPI
QPI
EBh
A
Quad
A
Quad
A
Quad
AXh(1), (2)
Quad
Quad
Data out
FRQIO
Fast Read
Quad I/O
(4-byte Address)
SPI
QPI
EBh
A
Quad
A
Quad
A
Quad
A
Quad
AXh(1), (2)
Quad
Quad
Data out
4FRQIO
4-byte Address
Fast Read
Quad I/O
SPI
QPI
ECh
A
Quad
A
Quad
A
Quad
A
Quad
AXh(1), (2)
Quad
Quad
Data out
FRQO
Fast Read
Quad Output
(3-byte Address)
SPI
6Bh
A
A
A
Dummy(1)
Byte
Quad
Data out
FRQO
Fast Read
Quad Output
(4-byte Address)
SPI
6Bh
A
A
A
A
Dummy(1)
Byte
Quad
Data out
4FRQO
4-byte Address
Fast Read
Quad Output
SPI
6Ch
A
A
A
A
Dummy(1)
Byte
Quad
Data out
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Byte5
Byte6
51
IS25LP512M
IS25WP512M
Instruction
Name
Operation
Mode
Byte0
Byte1
Byte2
Byte3
Byte4
Byte5
FRDTR
Fast Read
DTR Mode
(3-byte Address)
SPI
QPI
0Dh
A
A
A
Dummy(1)
Byte
Dual
Data out
FRDTR
Fast Read
DTR Mode
(4-byte Address)
SPI
QPI
0Dh
A
A
A
A
Dummy(1)
Byte
Dual
Data out
4FRDTR
4-byte Address
Fast Read
DTR Mode
SPI
QPI
0Eh
A
A
A
A
Dummy(1)
Byte
Dual
Data out
FRDDTR
Fast Read
Dual I/O DTR
(3-byte Address)
SPI
BDh
A
Dual
A
Dual
A
Dual
AXh(1), (2)
Dual
Dual
Data out
FRDDTR
Fast Read
Dual I/O DTR
(4-byte Address)
SPI
BDh
A
A
Dual
A
Dual
A
Dual
AXh(1), (2)
Dual
Dual
Data out
4FRDDTR
4-byte Address
Fast Read
Dual I/O DTR
SPI
BEh
A
A
Dual
A
Dual
A
Dual
AXh(1), (2)
Dual
Dual
Data out
FRQDTR
Fast Read
Quad I/O DTR
(3-byte Address)
SPI
QPI
EDh
A
A
A
AXh(1), (2)
Quad
Quad
Data out
FRQDTR
Fast Read
Quad I/O DTR
(4-byte Address)
SPI
QPI
EDh
A
A
A
A
AXh(1), (2)
Quad
Quad
Data out
4FRQDTR
4-byte Address
Fast Read
Quad I/O DTR
SPI
QPI
EEh
A
A
A
A
AXh(1), (2)
Quad
Quad
Data out
PP
Input Page
Program
(3-byte Address)
SPI
QPI
02h
A
A
A
PD
(256byte)
PP
Input Page
Program
(4-byte Address)
SPI
QPI
02h
A
A
A
A
PD
(256byte)
4PP
4-byte Address
Input Page
Program
SPI
QPI
12h
A
A
A
A
PD
(256byte)
PPQ
Quad Input
Page Program
(3-byte Address)
SPI
32h/38h
A
A
A
Quad PD
(256byte)
PPQ
Quad Input
Page Program
(4-byte Address)
SPI
32h/38h
A
A
A
A
Quad PD
(256byte)
4PPQ
4-byte Address
Quad Input
Page Program
SPI
34h/3Eh
A
A
A
A
Quad PD
(256byte)
SER
Sector Erase
(3-byte Address)
SPI
QPI
D7h/20h
A
A
A
SER
Sector Erase
(4-byte Address)
SPI
QPI
D7h/20h
A
A
A
A
4SER
4-byte Address
Sector Erase
SPI
QPI
21h
A
A
A
A
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Byte6
52
IS25LP512M
IS25WP512M
Instruction
Name
Operation
Mode
Byte0
Byte1
Byte2
Byte3
BER32
(32KB)
Block Erase
32Kbyte
(3-byte Address)
SPI
QPI
52h
A
A
A
BER32
(32KB)
Block Erase
32Kbyte
(4-byte Address)
SPI
QPI
52h
A
A
A
A
4BER32
(32KB)
4-byte Address
Block Erase
32Kbyte
SPI
QPI
5Ch
A
A
A
A
BER64
(64KB)
Block Erase
64Kbyte
(3-byte Address)
SPI
QPI
D8h
A
A
A
BER64
(64KB)
Block Erase
64Kbyte
(4-byte Address)
SPI
QPI
D8h
A
A
A
A
4BER64
(64KB)
4-byte Address
Block Erase
64Kbyte
SPI
QPI
DCh
A
A
A
A
CER
Chip Erase
SPI
QPI
C7h/60h
WREN
Write Enable
SPI
QPI
06h
WRDI
Write Disable
SPI
QPI
04h
RDSR
Read Status
Register
SPI
QPI
05h
Data out
WRSR
Write Status
Register
SPI
QPI
01h
Data in
RDFR
Read Function
Register
SPI
QPI
48h
Data out
WRFR
Write Function
Register
SPI
QPI
42h
Data in
QPIEN
Enter
QPI mode
SPI
35h
QPIDI
Exit
QPI mode
QPI
F5h
PERSUS
Suspend during
program/erase
SPI
QPI
75h/B0h
PERRSM
Resume
program/erase
SPI
QPI
7Ah/30h
DP
Deep Power
Down
SPI
QPI
B9h
RDID,
RDPD
Read ID /
Release
Power Down
SPI
QPI
ABh
XXh(3)
XXh(3)
XXh(3)
ID7-ID0
SRPNV
Set Read
Parameters
(Non-Volatile)
SPI
QPI
65h
Data in
SRPV
Set Read
Parameters
(Volatile)
SPI
QPI
C0h/63h
Data in
SERPNV
Set Extended
Read Parameters
(Non-Volatile)
SPI
QPI
85h
Data in
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Byte4
Byte5
Byte6
53
IS25LP512M
IS25WP512M
Instruction
Name
Operation
Mode
Byte0
Byte1
SERPV
Set Extended
Read Parameters
(Volatile)
SPI
QPI
83h
Data in
RDRP
Read Read
Parameters
(Volatile)
SPI
QPI
61h
Data out
RDERP
Read Extended
Read Parameters
(Volatile)
SPI
QPI
81h
Data out
CLERP
Clear Extended
Read Register
SPI
QPI
82h
RDJDID
Read JEDEC
ID Command
SPI
QPI
9Fh
RDMDID
Read
Manufacturer
& Device ID
SPI
QPI
90h
RDJDIDQ
Read JEDEC
ID
QPI mode
QPI
AFh
MF7-MF0
ID15-ID8
ID7-ID0
RDUID
Read
Unique ID
SPI
QPI
4Bh
A(4)
A(4)
RDSFDP
SFDP Read
SPI
5Ah
A
NOP
No Operation
SPI
QPI
00h
RSTEN
Software
Reset
Enable
SPI
QPI
66h
RST
Software Reset
SPI
QPI
99h
IRER
Erase
Information
Row
SPI
QPI
64h
IRP
Program
Information
Row
SPI
QPI
IRRD
Read
Information
Row
SECUNLOCK
Byte4
Byte5
00h
MF7-MF0
ID7-ID0
01h
ID7-ID0
MF7-MF0
A(4)
Dummy
Byte
Data out
A
A
Dummy
Byte
Data out
A
A
A
62h
A
A
A
PD
(256byte)
SPI
QPI
68h
A
A
A
Dummy
Byte
Sector Unlock
(3-byte Address)
SPI
QPI
26h
A
A
A
SECUNLOCK
Sector Unlock
(4-byte Address)
SPI
QPI
26h
A
A
A
A
4SECUNLOCK
4-byte Address
Sector Unlock
SPI
QPI
25h
A
A
A
A
SECLOCK
Sector Lock
SPI
QPI
24h
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Byte2
Byte3
MF7-MF0
ID15-ID8
ID7-ID0
XXh(3)
XXh(3)
Byte6
Data out
54
IS25LP512M
IS25WP512M
Instruction
Name
Operation
Mode
Byte0
Byte1
RDBR
Read Bank
Address Register
(Volatile)
SPI
QPI
16h/C8h
Data out
WRBRV
Write Bank
Address Register
(Volatile)
SPI
QPI
17h/C5h
Data in
WRBRNV
Write Bank
Address Register
(Non-Volatile)
SPI
QPI
18h
Data in
EN4B
Enter 4-byte
Address Mode
SPI
QPI
B7h
EX4B
Exit 4-byte
Address Mode
SPI
QPI
29h
RDDYB
Read DYB
(3-byte Address)
SPI
FAh
RDDYB
Read DYB
(4-byte Address)
SPI
4RDDYB
4-byte Address
Read DYB
WRDYB
Byte2
Byte3
Byte4
A
A
A
Data out
FAh
A
A
A
A
Data out
SPI
E0h
A
A
A
A
Data out
Write DYB
(3-byte Address)
SPI
QPI
FBh
A
A
A
Data in
WRDYB
Write DYB
(4-byte Address)
SPI
QPI
FBh
A
A
A
A
Data in
4WRDYB
4-byte Address
Write DYB
SPI
QPI
E1h
A
A
A
A
Data in
RDPPB
Read PPB
(3-byte Address)
SPI
FCh
A
A
A
Data out
RDPPB
Read PPB
(4-byte Address)
SPI
FCh
A
A
A
A
Data out
4RDPPB
4-byte Address
Read PPB
SPI
E2h
A
A
A
A
Data out
PGPPB
Program PPB
(Individually)
(3-byte Address)
SPI
QPI
FDh
A
A
A
PGPPB
Program PPB
(Individually)
(4-byte Address)
SPI
QPI
FDh
A
A
A
A
4PGPPB
4-byte Address
Program PPB
(Individually)
SPI
QPI
E3h
A
A
A
A
ERPPB
Erase PPB (as
a group)
SPI
QPI
E4h
RDASP
Read ASP
SPI
2Bh
Data out
(2 byte)
PGASP
Program ASP
SPI
QPI
2Fh
PD
(2 byte)
RDPLB
Read PPB Lock
Bit
SPI
A7h
Data out
WRPLB
Write PPB Lock
Bit
SPI
QPI
A6h
SFRZ
Set FREEZE bit
SPI
QPI
91h
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Byte6
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Instruction
Name
Operation
Mode
Byte0
Byte1
RDPWD
Read Password
SPI
E7h
Data out
(8 byte)
PGPWD
Program
Password
SPI
QPI
E8h
PD
(8 byte)
UNPWD
Unlock
Password
SPI
QPI
E9h
Data in
(8 byte)
GBLK
Set all DYB bits
(Gang Sector/
Block Lock)
SPI
QPI
7Eh
GBUN
Clear all DYB bits
(Gang Sector/
Block Unlock)
SPI
QPI
98h
RDDLP
Read Data
Learning Pattern
SPI
QPI
41h
Data out
PNVDLR
Program DLP
Register (NonVolatile)
SPI
QPI
43h
Data in
WRVDLR
Write DLP
Register
(Volatile)
SPI
QPI
4Ah
Data in
Byte2
Byte3
Byte4
Byte5
Byte6
Notes:
1. The number of dummy cycles depends on the value setting in the Table 6.11 Read Dummy Cycles.
2. AXh has to be counted as a part of dummy cycles. X means “don’t care”.
3. XX means “don’t care”.
4. A are “don’t care” and A are always “0”.
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8.3 NORMAL READ OPERATION (NORD, 03h or 4NORD, 13h)
The Normal Read (NORD) instruction is used to read memory contents at a maximum frequency of 80MHz.
03h (EXTADD=0) is followed by a 3-byte address (A23-A0) or
03h (EXTADD=1) is followed by a 4-byte address (A31-A0) or
13h is followed by a 4-byte address (A31-A0)
The Normal Read instruction code is transmitted via the SI line, followed by three (A23 - A0) or four (A31 – A0)
address bytes of the first memory location to be read as above. A total of 24 or 32 address bits are shifted in, but
only AVMSB (Valid Most Significant Bit) - A0 are decoded. The remaining bits (A31 – AVMSB+1) are ignored. The first
byte addressed can be at any memory location. Upon completion, any data on the SI will be ignored. Refer to Table
8.5 for the related Address Key.
The first byte data (D7 - D0) is shifted out on the SO line, MSB first. A single byte of data, or up to the whole memory
array, can be read out in one Normal Read instruction. The address is automatically incremented by one after each
byte of data is shifted out. The read operation can be terminated at any time by driving CE# high (VIH) after the
data comes out. When the highest address of the device is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read in one continuous Read instruction.
If the Normal Read instruction is issued while an Erase, Program or Write operation is in process (WIP=1) the
instruction is ignored and will not have any effects on the current operation .
Table 8.5 Address Key
Mode
3 byte address
4 byte address
Valid Address
AVMSB(2)–A0
512Mb
A23-A0
A25-A0 (A31-A26=X)(2)
Notes:
1.
X=Don’t Care
2.
AVMSB is a Valid MSB. In 4 byte address for 512Mb, A31 is an MSB, and A25 is a Valid MSB.
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Figure 8.1 Normal Read Sequence (03h [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
...
28
29
30
31
0
SCK
Mode 0
3-byte Address
SI
Instruction = 03h
23
22
...
21
3
2
1
45
46
47
High Impedance
SO
CE #
32
33
34
35
36
37
39
38
40
41
42
43
44
...
SCK
SI
Data Out 1
SO
tV
7
6
5
4
3
Data Out 2
2
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1
0
7
6
5
4
3
2
0
1
58
...
IS25LP512M
IS25WP512M
Figure 8.2 Normal Read Sequence (03h [EXTADD=1] or 13h, 4-byte address)
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
36
...
37
38
39
0
SCK
Mode 0
4-byte Address
SI
Instruction = 03h/13h
31
30
...
29
3
2
1
53
54
55
High Impedance
SO
CE #
40
41
42
43
44
45
47
46
48
49
50
51
52
...
SCK
SI
Data Out 1
SO
tV
7
6
5
4
3
Data Out 2
2
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0
7
6
5
4
3
2
0
1
59
...
IS25LP512M
IS25WP512M
8.4 FAST READ OPERATION (FRD, 0Bh or 4FRD, 0Ch)
The Fast Read (FRD, 4FRD) instruction is used to read memory data at up to a 133MHz clock.
0Bh (EXTADD=0) is followed by a 3-byte address (A23-A0) or
0Bh (EXTADD=1) is followed by a 4-byte address (A31-A0) or
0Ch is followed by a 4-byte address (A31-A0)
The Fast Read instruction code is followed by three or four address bytes as above and dummy cycles
(configurable, default is 8 clocks), transmitted via the SI line, with each bit latched-in during the rising edge of SCK.
Then the first data byte from the address is shifted out on the SO line, with each bit shifted out at a maximum
frequency fCT, during the falling edge of SCK.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single Fast Read instruction. The Fast Read
instruction is terminated by driving CE# high (VIH).
If the Fast Read instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction
is ignored without affecting the current cycle.
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Figure 8.3 Fast Read Sequence (0Bh [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
2
3
4
5
6
8
7
9
10
...
28
29
30
31
SCK
Mode 0
3-byte Address
SI
Instruction = 0Bh
23
22
21
...
3
2
1
0
41
42
43
44
45
46
47
...
High Impedance
SO
CE #
32
33
34
35
36
37
38
39
40
SCK
SI
Dummy Cycles
Data Out
tV
SO
7
6
5
4
3
2
0
1
...
Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.
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Figure 8.4 Fast Read Sequence (0Bh [EXTADD=1] or 0Ch, 4-byte address)
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
...
36
37
38
39
SCK
Mode 0
4-byte Address
SI
Instruction = 0Bh/0Ch
31
30
49
50
29
...
3
2
1
0
52
53
54
55
...
High Impedance
SO
CE #
40
41
42
43
44
45
46
47
48
51
SCK
SI
Dummy Cycles
Data Out
tV
SO
7
6
5
4
3
2
0
1
...
Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.
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FAST READ OPERATION IN QPI MODE (FRD, 0Bh or 4FRD, 0Ch)
The Fast Read (FRD) instruction in QPI mode is used to read memory data at up to a 133MHz clock.
0Bh (EXTADD=0) is followed by a 3-byte address (A23-A0) or
0Bh (EXTADD=1) is followed by a 4-byte address (A31-A0) or
0Ch is followed by a 4-byte address (A31-A0)
The Fast Read instruction code (2 clocks) is followed by three (6 clocks) or four (8 clocks) address bytes as above
and 6 dummy cycles (configurable, default is 6 clocks), transmitted via the IO3, IO2, IO1 and IO0 lines, with each
bit latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out on the IO3, IO2, IO1
and IO0 lines, with each bit shifted out at a maximum frequency fCT, during the falling edge of SCK.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single Fast Read QPI instruction. The Fast Read
QPI instruction is terminated by driving CE# high (VIH).
If the Fast Read instruction in QPI mode is issued while an Erase, Program or Write cycle is in process (WIP=1)
the instruction is ignored without affecting the current cycle.
The Fast Read sequence in QPI mode is also applied to the commands in the following table 8.6. However, only
3-byte address mode QPI sequence is applied for RDUID, and IRRD commands.
Table 8.6 Instructions that Fast Read sequence in QPI Mode is applied to
Instruction Name
Operation
Hex Code
FRQIO
Fast Read Quad I/O
EBh
RDUID
Read Unique ID
4Bh
Read Information Row
68h
IRRD
Figure 8.5 Fast Read Sequence In QPI Mode (0Bh [EXTADD=0], 3-byte address)
CE#
Mode 3 0
1
2
3
4
5
6
7
8
9
...
13
14
15
16
17
...
SCK
Mode 0
tV
IO[3:0]
0Bh
Instruction
23:20 19:16 15:12 11:8
3-byte Address
7:4
3:0
7:4
6 Dummy Cycles
3:0
Data 1
7:4
3:0
...
Data 2
Note: Number of dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy
Cycles.
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Figure 8.6 Fast Read Sequence In QPI Mode (0Bh [EXTADD=1] or 0Ch, 4-byte address)
CE#
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
...
15
16
17
...
SCK
Mode 0
tV
IO[3:0]
0Bh/0Ch
Instruction
31:28 27:24 23:20 19:16 15:12 11:8
7:4
4-byte Address
3:0
7:4
6 Dummy Cycles
3:0
...
Data 1
Note: Number of dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy
Cycles.
8.5 HOLD OPERATION
HOLD# is used in conjunction with CE# to select the device. When the device is selected and a serial sequence is
underway, HOLD# can be used to pause the serial communication with the master device without resetting the
serial sequence. To pause, HOLD# is brought low while the SCK signal is low. To resume serial communication,
HOLD# is brought high while the SCK signal is low (SCK may still toggle during HOLD). Inputs to SI will be ignored
while SO is in the high impedance state, during HOLD.
Note: HOLD is not supported in DTR mode or with QE=1 or when RESET# is selected for the HOLD# or RESET# pin.
Timing graph can be referenced in AC Parameters Figure 9.4.
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8.6 FAST READ DUAL I/O OPERATION (FRDIO, BBh or 4FRDIO, BCh)
The Fast Read Dual I/O (FRDIO, 4FRDIO) instruction allows the address bits to be input two bits at a time. This
may allow for code to be executed directly from the SPI in some applications.
BBh (EXTADD=0) is followed by a 3-byte address (A23-A0) or
BBh (EXTADD=1) is followed by a 4-byte address (A31-A0) or
BCh is followed by a 4-byte address (A31-A0)
The FRDIO/4FRDIO instruction code is followed by three or four address bytes as above and dummy cycles
(configurable, default is 4 clocks), transmitted via the IO1 and IO0 lines, with each pair of bits latched-in during the
rising edge of SCK. The address MSB is input on IO1, the next bit on IO0, and this shift pattern continues to
alternate between the two lines. Depending on the usage of AX read operation mode, a mode byte may be located
after address input.
The first data byte addressed is shifted out on the IO1 and IO0 lines, with each pair of bits shifted out at a maximum
frequency fCT, during the falling edge of SCK. The first bit (MSB) is output on IO1, while simultaneously the second
bit is output on IO0. Figures 8.7 and 8.8 illustrates the timing sequence.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FRDIO/4FRDIO instruction. The
FRDIO/4FRDIO instruction is terminated by driving CE# high (VIH).
The device supports the AX read operation by applying mode bits during dummy period. Mode bits consist of 8
bits, such as M7 to M0. Four cycles after address input are reserved for Mode bits in FRDIO/4FRDIO execution.
M7 to M4 are important for enabling this mode. M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah),
it enables the AX read operation and subsequent FRDIO/4FRDIO execution skips command code. It saves cycles
as described in Figures 8.9 and 8.10. When the code is different from AXh (where X is don’t care), the device exits
the AX read operation. After finishing the read operation, device becomes ready to receive a new command. SPI
or QPI mode configuration retains the prior setting. Mode bit must be applied during dummy cycles. Number of
dummy cycles in Table 6.11 includes number of mode bit cycles. If dummy cycles are configured as 4 cycles, data
output will start right after mode bit is applied.
If the FRDIO/4FRDIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the
instruction is ignored and will not affect the current cycle.
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Figure 8.7 Fast Read Dual I/O Sequence (BBh [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
...
18
19
20
21
SCK
Mode 0
4 Dummy Cycles
3-byte Address
IO0
Instruction = BBh
22
20
18
...
2
0
6
4
23
21
19
...
3
1
7
5
High Impedance
IO1
Mode Bits
CE #
22
23
24
25
26
27
29
28
30
31
32
33
34
35
36
37
...
SCK
tV
IO0
2
0
6
4
2
0
6
Data Out 1
IO1
3
1
7
5
3
4
2
0
6
Data Out 2
1
7
5
3
4
2
0
6
4
...
1
7
5
...
Data Out 3
1
7
5
3
Mode Bits
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode
bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.
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Figure 8.8 Fast Read Dual I/O Sequence (BBh [EXTADD=1] or BCh, 4-byte address)
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
22
...
23
24
25
SCK
Mode 0
4 Dummy Cycles
4-byte Address
IO0
Instruction = BBh/BCh
30
28
26
...
2
0
6
4
31
29
27
...
3
1
7
5
High Impedance
IO1
Mode Bits
CE #
26
27
28
29
30
31
33
32
34
35
36
37
38
39
36
41
...
SCK
tV
IO0
2
0
6
4
2
0
6
Data Out 1
IO1
3
1
7
5
3
4
2
0
6
Data Out 2
1
7
5
3
4
2
0
6
4
...
1
7
5
...
Data Out 3
1
7
5
3
Mode Bits
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode
bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.
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Figure 8.9 Fast Read Dual I/O AX Read Sequence (BBh [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
2
3
...
11
12
13
14
15
16
17
18
19
20
...
21
SCK
Mode 0
4 Dummy Cycles
3-byte Address
tV
Data Out 2
Data Out 1
IO0
22
20
18
...
2
0
6
4
2
0
6
4
2
0
6
4
...
IO1
23
21
19
...
3
1
7
5
3
1
7
5
3
1
7
5
...
Mode Bits
Notes:
1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.
Figure 8.10 Fast Read Dual I/O AX Read Sequence (BBh [EXTADD=1] or BCh, 4-byte address)
CE #
Mode 3 0
1
2
3
...
15
16
17
18
19
20
21
22
23
24
...
25
SCK
Mode 0
4 Dummy Cycles
4-byte Address
tV
Data Out 2
Data Out 1
IO0
30
28
26
...
2
0
6
4
2
0
6
4
2
0
6
4
...
IO1
31
29
27
...
3
1
7
5
3
1
7
5
3
1
7
5
...
Mode Bits
Notes:
1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.
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8.7 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh or 4FRDO, 3Ch)
The FRDO/4FRDO instruction is used to read memory data on two output pins each at up to a 133MHz clock.
3Bh (EXTADD=0) is followed by a 3-byte address (A23-A0) or
3Bh (EXTADD=1) is followed by a 4-byte address (A31-A0) or
3Ch is followed by a 4-byte address (A31-A0)
The FRDO/4FRDO instruction code is followed by three or four address bytes as above and dummy cycles
(configurable, default is 8 clocks), transmitted via the IO0 line, with each bit latched-in during the rising edge of SCK.
Then the first data byte addressed is shifted out on the IO1 and IO0 lines, with each pair of bits shifted out at a
maximum frequency fCT, during the falling edge of SCK. The first bit (MSB) is output on IO1. Simultaneously, the
second bit is output on IO0.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. W hen the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FRDO/4FRDO instruction. The instruction
FRDO/4FRDO is terminated by driving CE# high (VIH).
If the FRDO/4FRDO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the
instruction is ignored and will not have any effects on the current cycle.
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Figure 8.11 Fast Read Dual Output Sequence (3Bh [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
...
28
29
30
31
SCK
Mode 0
3-byte Address
IO0
Instruction = 3Bh
23
22
41
42
21
...
3
2
1
0
44
45
46
47
...
High Impedance
IO1
CE #
32
33
34
35
36
37
38
39
40
43
SCK
tV
IO0
6
2
0
6
Data Out 1
8 Dummy Cycles
IO1
4
7
5
3
4
2
0
...
1
...
Data Out 2
1
7
5
3
Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.
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Figure 8.12 Fast Read Dual Output Sequence (3Bh [EXTADD=1] or 3Ch, 4-byte address)
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
...
36
37
38
39
SCK
Mode 0
4-byte Address
IO0
Instruction = 3Bh/3Ch
31
30
29
49
50
51
...
3
2
1
0
52
53
54
55
...
High Impedance
IO1
CE #
40
41
42
43
44
45
46
47
48
SCK
tV
IO0
6
2
0
6
Data Out 1
8 Dummy Cycles
IO1
4
7
5
3
4
2
0
...
1
...
Data Out 2
1
7
5
3
Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.
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8.8 FAST READ QUAD OUTPUT OPERATION (FRQO, 6Bh or 4FRQO 6Ch)
The FRQO/4FRQO instruction is used to read memory data on four output pins each at up to a 133 MHz
clock.
A Quad Enable (QE) bit of Status Register must be set to "1" before sending the Fast Read Quad Output instruction.
6Bh (EXTADD=0) is followed by a 3-byte address (A23-A0) or
6Bh (EXTADD=1) is followed by a 4-byte address (A31-A0) or
6Ch is followed by a 4-byte address (A31-A0)
The FRQO/4FRQO instruction code is followed by three or four address bytes as above and dummy cycles
(configurable, default is 8 clocks), transmitted via the IO0 line, with each bit latched-in during the rising
edge of SCK. Then the first data byte addressed is shifted out on the IO3, IO2, IO1 and IO0 lines, with
each group of four bits shifted out at a maximum frequency f CT, during the falling edge of SCK. The first
bit (MSB) is output on IO3, while simultaneously the second bit is output on IO2, the third bit is output on
IO1, etc.
The first byte addressed can be at any memory location. The address is automatically incremented after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over
to the 000000h address, allowing the entire memory to be read with a single FRQO/ 4FRQO instruction.
FRQO/4FRQO instruction is terminated by driving CE# high (VIH).
If a FRQO/4FRQO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the
instruction is ignored and will not have any effects on the current cycle.
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Figure 8.13 Fast Read Quad Output Sequence (6Bh [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
...
28
29
30
31
SCK
Mode 0
3-byte Address
IO0
Instruction = 6Bh
23
22
41
42
21
...
3
2
1
0
44
45
46
47
...
High Impedance
IO1
High Impedance
IO2
High Impedance
IO3
CE #
32
33
34
35
36
37
38
39
40
43
SCK
tV
IO0
4
8 Dummy Cycles
0
4
0
4
0
4
0
...
Data Out 1 Data Out 2 Data Out 3 Data Out 4
IO1
5
1
5
1
5
1
5
1
...
IO2
6
2
6
2
6
2
6
2
...
IO3
7
3
7
3
7
3
7
3
...
Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.
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Figure 8.14 Fast Read Quad Output Sequence (6Bh [EXTADD=1] or 6Ch, 4-byte address)
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
...
36
37
38
39
SCK
Mode 0
4-byte Address
IO0
Instruction = 6Bh/6Ch
31
30
29
...
3
2
1
0
52
53
54
55
...
High Impedance
IO1
High Impedance
IO2
High Impedance
IO3
CE #
40
41
42
43
44
45
46
47
48
49
50
51
SCK
tV
IO0
4
8 Dummy Cycles
0
4
0
4
0
4
0
...
Data Out 1 Data Out 2 Data Out 3 Data Out 4
IO1
5
1
5
1
5
1
5
1
...
IO2
6
2
6
2
6
2
6
2
...
IO3
7
3
7
3
7
3
7
3
...
Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.
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8.9 FAST READ QUAD I/O OPERATION (FRQIO, EBh or 4FRQIO, ECh)
The FRQIO/4FRQIO instruction allows the address bits to be input four bits at a time. This may allow for code to
be executed directly from the SPI in some applications.
A Quad Enable (QE) bit of Status Register must be set to "1" before sending the Fast Read Quad I/O instruction.
EBh (EXTADD=0) is followed by a 3-byte address (A23-A0) or
EBh (EXTADD=1) is followed by a 4-byte address (A31-A0) or
ECh is followed by a 4-byte address (A31-A0)
The FRQIO/4FRQIO instruction code is followed by three or four address bytes as above and dummy cycles
(configurable, default is 6 clocks), transmitted via the IO3, IO2, IO1 and IO0 lines, with each group of four bits
latched-in during the rising edge of SCK. The address of MSB inputs on IO3, the next bit on IO2, the next bit on
IO1, the next bit on IO0, and continue to shift in alternating on the four. Depending on the usage of AX read
operation mode, a mode byte may be located after address input.
The first data byte addressed is shifted out on the IO3, IO2, IO1 and IO0 lines, with each group of four bits shifted
out at a maximum frequency f CT, during the falling edge of SCK. The first bit (MSB) is output on IO3, while
simultaneously the second bit is output on IO2, the third bit is output on IO1, etc. Figures 8.15 and 8.16 illustrates
the timing sequence.
The first byte addressed can be at any memory location. The address is automatically incremented after each byte
of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h
address, allowing the entire memory to be read with a single FRQIO/4FRQIO instruction. FRQIO/4FRQIO
instruction is terminated by driving CE# high (VIH).
The device supports the AX read operation by applying mode bits during dummy period. Mode bits consist of 8
bits, such as M7 to M0. Two cycles after address input are reserved for Mode bits in FRQIO/4FRQIO execution.
M7 to M4 are important for enabling this mode. M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah),
it enables the AX read operation and subsequent FRQIO/4FRQIO execution skips command code. It saves cycles
as described in Figures 8.17 and 8.18. When the code is different from AXh (where X is don’t care), the device
exits the AX read operation. After finishing the read operation, device becomes ready to receive a new command.
SPI or QPI mode configuration retains the prior setting. Mode bit must be applied during dummy cycles. Number
of dummy cycles in Table 6.11 includes number of mode bit cycles. If dummy cycles are configured as 6 cycles,
data output will start right after mode bits and 4 additional dummy cycles are applied.
If the FRQIO/4FRQIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the
instruction is ignored and will not have any effects on the current cycle.
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Figure 8.15 Fast Read Quad I/O Sequence (EBh [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
11
12
13
14
15
SCK
Mode 0
3-byte Address
IO0
20
16
12
8
4
0
4
0
21
17
13
9
5
1
5
1
IO2
22
18
14
10
6
2
6
2
IO3
23
19
15
11
7
3
7
3
Instruction = EBh
High Impedance
IO1
Mode Bits
CE #
16
17
18
19
20
21
23
22
24
25
26
27
28
29
30
31
...
SCK
6 Dummy Cycles
tV Data Out 1 Data Out 2 Data Out 3 Data Out 4 Data Out 5 Data Out 6
IO0
4
0
4
0
4
0
4
0
4
0
4
0
...
IO1
5
1
5
1
5
1
5
1
5
1
5
1
...
6
2
6
2
6
2
6
2
6
2
6
2
...
7
3
7
3
7
3
7
3
7
3
7
3
...
IO2
IO3
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode
bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.
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Figure 8.16 Fast Read Quad I/O Sequence (EBh [EXTADD=1] or ECh, 4-byte address)
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
11
12
13
14
15
SCK
Mode 0
4-byte Address
IO0
28
24
20
16
12
8
4
0
29
25
21
17
13
9
5
1
IO2
30
26
22
18
14
10
6
2
IO3
31
27
23
19
15
11
7
3
25
26
27
28
29
30
31
...
Instruction = EBh/ECh
High Impedance
IO1
CE #
16
17
18
19
20
21
23
22
24
SCK
6 Dummy Cycles
tV Data Out 1 Data Out 2 Data Out 3 Data Out 4 Data Out 5
IO0
4
0
4
0
4
0
4
0
4
0
4
0
...
IO1
5
1
5
1
5
1
5
1
5
1
5
1
...
6
2
6
2
6
2
6
2
6
2
6
2
...
7
3
7
3
7
3
7
3
7
3
7
3
...
IO2
IO3
Mode Bits
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode
bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.
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Figure 8.17 Fast Read Quad I/O AX Read Sequence (EBh [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
...
SCK
Mode 0
6 Dummy Cycles
3-byte Address
tV
Data Out 1 Data Out 2
IO0
20
16
12
8
4
0
4
0
4
0
4
0
...
IO1
21
17
13
9
5
1
5
1
5
1
5
1
...
IO2
22
18
14
10
6
2
6
2
6
2
6
2
...
IO3
23
19
15
11
7
3
7
3
7
3
7
3
...
Mode Bits
Notes:
1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.
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Figure 8.18 Fast Read Quad I/O AX Read Sequence (EBh [EXTADD=1] or ECh, 4-byte address)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
...
SCK
Mode 0
6 Dummy Cycles
4-byte Address
tV
Data Out 1
IO0
28
24
20
16
12
8
4
0
4
0
4
0
...
IO1
29
25
21
17
13
9
5
1
5
1
5
1
...
IO2
30
26
22
18
14
10
6
2
6
2
6
2
...
IO3
31
27
23
19
15
11
7
3
7
3
7
3
...
Mode Bits
Notes:
1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.
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FAST READ QUAD I/O OPERATION IN QPI MODE (FRQIO, EBh or 4FRQIO, ECh)
The FRQIO/4FRQIO instruction in QPI mode is used to read memory data at up to a 133MHz clock.
It is not required to set QE bit to “1”.before Fast Read Quad I/O instruction in QPI mode.
The FRQIO/4FRQIO instruction in QPI mode utilizes all four IO lines to input the instruction code so that only two
clocks are required, while the FRQIO/4FRQIO instruction requires that the byte-long instruction code is shifted into
the device only via IO0 line in eight clocks. As a result, 6 command cycles will be reduced by the FRQIO/4FRQIO
QPI instruction. In addition, subsequent address and data out are shifted in/out via all four IO lines like the
FRQIO/4FRQIO instruction. In fact, except for the command cycle, the FRQIO/4FRQIO operation in QPI mode is
exactly same as the FRQIO/4FRQIO operation in SPI mode.
The device supports the AX read operation by applying mode bits during dummy period. Mode bits consist of 8
bits, such as M7 to M0. Two cycles after address input are reserved for Mode bits in FRQIO/4FRQIO execution.
M7 to M4 are important for enabling this mode. M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah),
it enables the AX read operation and subsequent FRQIO/4FRQIO execution skips command code. It saves cycles
as described in Figures 8.17 and 8.18. When the code is different from AXh (where X is don’t care), the device
exits the AX read operation. After finishing the read operation, device becomes ready to receive a new command.
SPI or QPI mode configuration retains the prior setting. Mode bit must be applied during dummy cycles. Number
of dummy cycles in Table 6.11 includes number of mode bit cycles. If dummy cycles are configured as 6 cycles,
data output will start right after mode bits and 4 additional dummy cycles are applied.
If the FRQIO/4FRQIO instruction in QPI mode is issued while an Erase, Program or Write cycle is in process
(WIP=1) the instruction is ignored and will not have any effects on the current cycle.
Figure 8.19 Fast Read Quad I/O Sequence In QPI Mode (EBh [EXTADD=0], 3-byte address)
CE#
Mode 3 0
1
2
3
4
5
6
7
8
9
...
13
14
15
16
17
...
SCK
Mode 0
Mode Bits
IO[3:0]
EBh
Instruction
23:20 19:16 15:12 11:8
3-byte Address
7:4
3:0
7:4
3:0
6 Dummy Cycles
tV
7:4
3:0
Data 1
7:4
3:0
...
Data 2
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode
bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy
Cycles.
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Figure 8.20 Fast Read Quad I/O Sequence In QPI Mode (EBh [EXTADD=1] or ECh, 4-byte address)
CE#
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
...
15
16
17
...
SCK
Mode 0
Mode Bits
IO[3:0]
EBh/ECh 31:28 27:24 23:20 18:16 15:12 11:8
Instruction
4-byte Address
7:4
3:0
7:4
3:0
6 Dummy Cycles
tV
7:4
3:0
...
Data 1
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode
bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy
Cycles.
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8.10 PAGE PROGRAM OPERATION (PP, 02h or 4PP, 12h)
The Page Program (PP/4PP) instruction allows up to 256/512 bytes data to be programmed into memory in a single
operation. The destination of the memory to be programmed must be outside the protected memory area set by
the Block Protection bits (BP3, BP2, BP1, BP0) or ASP. A PP/4PP instruction which attempts to program into a
page that is write-protected will be ignored. Before the execution of PP/4PP instruction, the Write Enable Latch
(WEL) must be enabled through a Write Enable (WREN) instruction.
02h (EXTADD=0) is followed by a 3-byte address (A23-A0) or
02h (EXTADD=1) is followed by a 4-byte address (A31-A0) or
12h is followed by a 4-byte address (A31-A0)
The PP/4PP instruction code, three or four address bytes as above and program data (1 to 256/512 bytes) are
input via the SI line. Program operation will start immediately after the CE# is brought high, otherwise the PP/4PP
instruction will not be executed. The internal control logic automatically handles the programming voltages and
timing. The progress or completion of the program operation can be determined by reading the WIP bit. If the WIP
bit is “1”, the program operation is still in progress. If WIP bit is “0”, the program operation has completed.
If more than 256/512 bytes data are sent to a device, the address counter rolls over within the same page, the
previously latched data are discarded, and the last 256/512 bytes are kept to be programmed into the page. The
starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap around
to the beginning of the same page. If the data to be programmed are less than a full page, the data of all other
bytes on the same page will remain unchanged.
Notes:
A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s.
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Figure 8.21 Page Program Sequence In SPI Mode (02h [EXTADD=0], 3-byte address)
1
...
7
8
9
...
31
32
33
...
39
...
...
2079
Mode 3 0
2072
CE #
SCK
Mode 0
SI
3-byte Address
Instruction = 02h
23
22
...
Data In 1
0
7
6
...
Data In 256
0
...
7
...
0
High Impedance
SO
Figure 8.22 Page Program Sequence In QPI Mode (02h [EXTADD=0], 3-byte address)
CE#
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
...
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
...
SCK
Mode 0
IO[3:0]
02h
23:20 19:16 15:12 11:8
3-byte Address
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Data In 1
Data In 2
Data In 3
Data In 4
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Figure 8.23 Page Program Sequence In SPI Mode (02h [EXTADD=1] or 12h, 4-byte address)
1
...
7
8
9
...
39
40
41
...
47
...
...
2087
Mode 3 0
2080
CE #
SCK
Mode 0
SI
4-byte Address
Instruction = 02h/12h
31
30
...
Data In 1
0
7
6
...
Data In 256
0
...
7
...
0
High Impedance
SO
Figure 8.24 Page Program Sequence In QPI Mode (02h [EXTADD=1] or 12h, 4-byte address)
CE#
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
...
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
...
SCK
Mode 0
IO[3:0]
02h/12h
31:28 27:24 23:20 19:16 15:12 11:8
4-byte Address
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Data In 2
Data In 3
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8.11 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h/38h or 4PPQ, 34h/3Eh)
The Quad Input Page Program instruction allows up to 256/512 bytes data to be programmed into memory in a
single operation with four pins (IO0, IO1, IO2 and IO3). The destination of the memory to be programmed must be
outside the protected memory area set by the Block Protection (BP3, BP2, BP1, BP0) bits or ASP. A Quad Input
Page Program instruction which attempts to program into a page that is write-protected will be ignored.
Before the execution of Quad Input Page Program instruction, the QE bit in the Status Register must be set to “1”
and the Write Enable Latch (WEL) must be enabled through a Write Enable (WREN) instruction.
32h/38h (EXTADD=0) is followed by a 3-byte address (A23-A0) or
32h/38h (EXTADD=1) is followed by a 4-byte address (A31-A0) or
34h/3Eh is followed by a 4-byte address (A31-A0)
Program operation will start immediately after the CE# is brought high, otherwise the Quad Input Page Program
instruction will not be executed. The internal control logic automatically handles the programming voltages and
timing. The progress or completion of the program operation can be determined by reading the WIP bit. If the WIP
bit is “1”, the program operation is still in progress. If WIP bit is “0”, the program operation has completed.
If more than 256/512 bytes data are sent to a device, the address counter rolls over within the same page, the
previously latched data are discarded, and the last 256/512 bytes data are kept to be programmed into the page.
The starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap
around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all
other bytes on the same page will remain unchanged.
Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s.
Figure 8.25 Quad Input Page Program operation (32h/38h [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
...
31
32
33
34
35
...
SCK
Mode 0
3-byte Address
Data In 1
Data In 2
4
0
4
0
...
5
1
5
1
...
IO2
6
2
6
2
...
IO3
7
3
7
3
...
IO0
IO1
Instruction = 32h/38h
High Impedance
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22
...
0
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IS25LP512M
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Figure 8.26 Quad Input Page Program operation (32h/38h [EXTADD=1] or 34h/3Eh, 4-byte address)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
...
39
40
41
42
43
...
SCK
Mode 0
4-byte Address
Data In 1
Data In 2
4
0
4
0
...
5
1
5
1
...
IO2
6
2
6
2
...
IO3
7
3
7
3
...
IO0
IO1
Instruction = 32h/38h/34h/3Eh
31
30
High Impedance
...
0
8.12 ERASE OPERATION
The Erase command sets all bits in the addressed sector or block to “1”s.
The memory array of the device is organized into uniform 4 Kbyte sectors or 32/64/256 Kbyte uniform blocks (a
block consists of eight/sixteen adjacent sectors respectively).
Before a byte is reprogrammed, the sector or block that contains the byte must be erased (erasing sets bits to “1”).
In order to erase the device, there are three erase instructions available: Sector Erase (SER), Block Erase (BER),
and Chip Erase (CER). A sector erase operation allows any individual sector to be erased without affecting the
data in other sectors. A block erase operation erases any individual block. A chip erase operation erases the whole
memory array of a device. A sector erase, block erase, or chip erase operation can be executed prior to any
programming operation.
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8.13 SECTOR ERASE OPERATION (SER, D7h/20h or 4SER, 21h)
A Sector Erase (SER/4SER) instruction erases a 4 Kbyte sector before the execution of a SER/4SER instruction,
the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is automatically
reset after the completion of Sector Erase operation.
D7h/20h (EXTADD=0) is followed by a 3-byte address (A23-A0) or
D7h/20h (EXTADD=1) is followed by a 4-byte address (A31-A0) or
21h is followed by a 4-byte address (A31-A0)
A SER/4SER instruction is entered, after CE# is pulled low to select the device and stays low during the entire
instruction sequence The SER/4SER instruction code, and three or four address bytes as above are input via SI.
Erase operation will start immediately after CE# is pulled high. The internal control logic automatically handles the
erase voltage and timing.
The progress or completion of the erase operation can be determined by reading the WIP bit. If the WIP bit is “1”,
the erase operation is still in progress. If the WIP bit is “0”, the erase operation has been completed.
Figure 8.27 Sector Erase Sequence In SPI Mode (D7h/20h [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
...
28
29
30
31
1
0
SCK
Mode 0
3-byte Address
SI
SO
Instruction = D7h/20h
23
22
21
...
3
2
High Impedance
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Figure 8.28 Sector Erase Sequence In SPI Mode (D7h/20h [EXTADD=1] or 21h, 4-byte address)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
...
36
37
38
39
1
0
SCK
Mode 0
4-byte Address
SI
Instruction = D7h/20h/21h
31
30
29
...
3
2
High Impedance
SO
Figure 8.29 Sector Erase Sequence In QPI Mode (D7h/20h [EXTADD=0], 3-byte address)
CE#
Mode 3 0
1
2
3
4
5
6
7
7:4
3:0
SCK
Mode 0
3-byte Address
D7h/20h
IO[3:0]
23:20 19:16 15:12 11:8
Figure 8.30 Sector Erase Sequence In QPI Mode (D7h/20h [EXTADD=1] or 21h, 4-byte address)
CE#
Mode 3 0
1
2
3
4
5
6
7
8
9
7:4
3:0
SCK
Mode 0
IO[3:0]
4-byte Address
D7h/
20h/21h
31:28 27:24 23:20 19:16 15:12 11:8
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8.14 BLOCK ERASE OPERATION (BER32K:52h or 4BER32K:5Ch, BER64K/256K:D8h or
4BER64K/256K:DCh)
A Block Erase (BER) instruction erases a 32/64 or 32/256 Kbyte block. Before the execution of a BER instruction,
the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically
after the completion of a block erase operation.
52h/D8h (EXTADD=0) is followed by a 3-byte address (A23-A0) or
52h/D8h (EXTADD=1) is followed by a 4-byte address (A31-A0) or
5Ch/DCh is followed by a 4-byte address (A31-A0)
The BER instruction code and three or four address bytes as above are input via SI. Erase operation will start
immediately after the CE# is pulled high, otherwise the BER instruction will not be executed. The internal control
logic automatically handles the erase voltage and timing.
Figure 8.31 Block Erase (64K/256K) Sequence In SPI Mode (D8h [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
...
28
29
30
31
2
1
0
SCK
Mode 0
3-byte Address
SI
Instruction = D8h
23
22
21
...
3
High Impedance
SO
Figure 8.32 Block Erase (64K/256K) Sequence In SPI Mode (D8h [EXTADD=1] or DCh, 4-byte address)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
...
36
37
38
39
2
1
0
SCK
Mode 0
4-byte Address
SI
SO
Instruction = D8h/DCh
31
29
28
...
3
High Impedance
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Figure 8.33 Block Erase (64K/256K) Sequence In QPI Mode (D8h [EXTADD=0], 3-byte address)
CE#
Mode 3 0
1
2
3
4
5
6
7
7:4
3:0
SCK
Mode 0
3-byte Address
D8h
IO[3:0]
23:20 19:16 15:12 11:8
Figure 8.34 Block Erase (64K/256K) Sequence In QPI Mode (D8h [EXTADD=1] or DCh, 4-byte address)
CE#
Mode 3 0
1
2
3
4
5
7
6
8
9
7:4
3:0
SCK
Mode 0
4-byte Address
D8h/DCh
IO[3:0]
31:28 27:24 23:20 19:16 15:12 11:8
Figure 8.35 Block Erase (32K) Sequence In SPI Mode (52h [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
...
28
29
30
31
2
1
0
SCK
Mode 0
3-byte Address
SI
SO
Instruction = 52h
23
22
21
...
3
High Impedance
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Figure 8.36 Block Erase (32K) Sequence In SPI Mode (52h [EXTADD=1] or 5Ch, 4-byte address)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
...
36
37
38
39
2
1
0
SCK
Mode 0
4-byte Address
SI
Instruction = 52h/5Ch
31
29
28
...
3
High Impedance
SO
Figure 8.37 Block Erase (32K) Sequence In QPI Mode (52h [EXTADD=0], 3-byte address)
CE#
Mode 3 0
1
2
3
4
5
6
7
7:4
3:0
SCK
Mode 0
3-byte Address
52h
IO[3:0]
23:20 19:16 15:12 11:8
Figure 8.38 Block Erase (32K) Sequence In QPI Mode (52h [EXTADD=1] or 5Ch, 4-byte address)
CE#
Mode 3 0
1
2
3
4
5
6
7
8
9
7:4
3:0
SCK
Mode 0
IO[3:0]
4-byte Address
52h/5Ch
31:28 27:24 23:20 19:16 15:12 11:8
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8.15 CHIP ERASE OPERATION (CER, C7h/60h)
A Chip Erase (CER) instruction erases the entire memory array. Before the execution of CER instruction, the Write
Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is automatically reset after
completion of a chip erase operation.
The CER instruction code is input via the SI. Erase operation will start immediately after CE# is pulled high,
otherwise the CER instruction will not be executed. The internal control logic automatically handles the erase
voltage and timing.
Chip Erase (CER) instruction can be executed only when Block Protection (BP3~BP0) bits are set to 0s. If the BP
bits are not 0, the CER command is not executed and E_ERR and PROT_E are set.
Chip Erase (CER) instruction will skip sectors/blocks protected by ASP (DYB bits or PPB bits) and will not set
E_ERR and PROT_E if sectors/blocks are protected by ASP only.
Figure 8.39 Chip Erase Sequence In SPI Mode
CE#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
SI
Instruction = C7h/60h
SO
High Impedance
Figure 8.40 Chip Erase Sequence In QPI Mode
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
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8.16 WRITE ENABLE OPERATION (WREN, 06h)
The Write Enable (WREN) instruction is used to set the Write Enable Latch (WEL) bit. The WEL bit is reset to the
write-protected state after power-up. The WEL bit must be write enabled before any write operation, including
Sector Erase, Block Erase, Chip Erase, Page Program, Program Information Row, Write Non-Volatile Status
Register, Write Function Register, Set Non-Volatile Read Register, Set Non-Volatile Extended Read Register, ,
Set Volatile Read Register and Set Volatile Extended Read Register. The WEL bit will be reset to the writeprotected state automatically upon completion of a write operation. The WREN instruction is required before any
above operation is executed.
Figure 8.41 Write Enable Sequence In SPI Mode
CE#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Instruction = 06h
SI
High Impedance
SO
Figure 8.42 Write Enable Sequence In QPI Mode
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
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8.17 WRITE DISABLE OPERATION (WRDI, 04h)
The Write Disable (WRDI) instruction resets the WEL bit and disables all write instructions. The WRDI instruction
is not required after the execution of a write instruction, since the WEL bit is automatically reset.
Figure 8.43 Write Disable Sequence In SPI Mode
CE#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Instruction = 04h
SI
High Impedance
SO
Figure 8.44 Write Disable Sequence In QPI Mode
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
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8.18 READ STATUS REGISTER OPERATION (RDSR, 05h)
The Read Status Register (RDSR) instruction provides access to the Status Register.
During the execution of a program, erase or Write Status Register operation, the RDSR instruction will be executed,
which can be used to check the progress or completion of an operation by reading the WIP bit.
Figure 8.45 Read Status Register Sequence In SPI Mode
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Mode 0
SI
Instruction = 05h
tV
SO
Data Out
7
6
5
4
3
2
1
Figure 8.46 Read Status Register Sequence In QPI Mode
CE#
Mode 3 0
1
2
3
SCK
Mode 0
tV
IO[3:0]
05h
7:4
3:0
Data Out
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8.19 WRITE STATUS REGISTER OPERATION (WRSR, 01h)
The Write Status Register (WRSR) instruction allows the user to enable or disable the block protection and Status
Register write protection features by writing “0”s or “1”s into non-volatile BP3, BP2, BP1, BP0, and SRWD bits.
Also WRSR instruction allows the user to disable or enable quad operation by writing “0” or “1” into QE bit.
To write Status Register bits, a standard Write Enable (06h) instruction must previously have been executed for
the device to accept Write Status Register (01h) instruction (Status Register bit WEL must equal 1).
Figure 8.47 Write Status Register Sequence In SPI Mode
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
11
12
13
14
15
2
1
0
SCK
Mode 0
Data In
SI
SO
Instruction = 01h
7
6
2
3
7:4
3:0
5
4
3
High Impedence
Figure 8.48 Write Status Register QPI Sequence
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
01h
Data In
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8.20 READ FUNCTION REGISTER OPERATION (RDFR, 48h)
The Read Function Register (RDFR) instruction provides access to the Function Register. Refer to Table 6.6
Function Register Bit Definition for more detail.
Figure 8.49 Read Function Register Sequence In SPI Mode
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Mode 0
SI
Instruction = 48h
tV
SO
Data Out
7
6
5
4
3
2
1
Figure 8.50 Read Function Register QPI Sequence
CE#
Mode 3 0
1
2
3
SCK
Mode 0
tV
IO[3:0]
48h
7:4
3:0
Data Out
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8.21 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h)
The Write Function Register (WRFR) instruction allows the user to disable dedicated RESET# pin or ball on 16-pin
SOIC or 24 ball TFBGA by setting Dedicated RESET# Disable bit to “1”. Also Information Row Lock bits
(IRL3~IRL0) can be set to “1” individually by WRFR instruction in order to lock Information Row.
Since Dedicated RESET# Disable bit and IRL bits are OTP, once they are set to “1”, they cannot be set back to “0”
again
Figure 8.51 Write Function Register Sequence In SPI Mode
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
11
12
13
14
15
2
1
0
SCK
Mode 0
Data In
SI
SO
Instruction = 42h
7
6
2
3
7:4
3:0
5
4
3
High Impedence
Figure 8.52 Write Function Register QPI Sequence
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
42h
Data In
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8.22 ENTER QUAD PERIPHERAL INTERFACE (QPI) MODE OPERATION (QPIEN,35h; QPIDI,F5h)
The Enter QPI (QPIEN) instruction, 35h, enables the Flash device for QPI bus operation. Upon completion of the
instruction, all instructions thereafter will be 4-bit multiplexed input/output until a power cycle or an Exit QPI
instruction is sent to device.
The Exit QPI instruction, F5h, resets the device to 1-bit SPI protocol operation. To execute an Exit QPI operation,
the host drives CE# low, sends the Exit QPI command cycle, then drives CE# high. The device just accepts QPI (2
clocks) command cycles.
Figure 8.53 Enter Quad Peripheral Interface (QPI) Mode Sequence
CE#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Instruction = 35h
SI
High Impedance
SO
Figure 8.54 Exit Quad Peripheral Interface (QPI) Mode Sequence
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
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8.23 PROGRAM/ERASE SUSPEND & RESUME
The device allows the interruption of Sector Erase, Block Erase, or Page Program operations to conduct other
operations. 75h/B0h command for suspend and 7Ah/30h for resume will be used. (SPI/QPI all acceptable) Function
Register bit2 (PSUS) and bit3 (ESUS) are used to check whether or not the device is in suspend mode.
Suspend to read ready timing (tSUS): 100µs (TYP)
Resume to another suspend timing (tRS): 80µs (TYP)
SUSPEND DURING SECTOR-ERASE OR BLOCK-ERASE (PERSUS 75h/B0h)
The Suspend command allows the interruption of Sector Erase and Block Erase operations. But Suspend command
will be ignored during Chip Erase operation. After the Suspend command, other commands include array read
operation can be accepted.
But Write Status Register command (01h) and Erase instructions are not allowed during Erase Suspend. Also,
array read for being erased sector/block is not allowed.
To execute Erase Suspend operation, the host drives CE# low, sends the Suspend command cycle (75h/B0h),
then drives CE# high. The Function Register indicates that the Erase has been suspended by setting the ESUS bit
from “0” to “1”, but the device will not accept another command until it is ready. To determine when the device will
accept a new command, poll the WIP bit or wait the specified time t SUS. When ESUS bit is set to “1”, the Write
Enable Latch (WEL) bit clears to “0”.
SUSPEND DURING PAGE PROGRAMMING (PERSUS 75h/B0h)
The Suspend command also allows the interruption of all array Program operations. After the Suspend command,
other commands include array read operation can be accepted can be accepted.
But Write Status Register instruction (01h) and Program instructions are not allowed during Program Suspend.
Also, array read for being programmed page is not allowed.
To execute the Program Suspend operation, the host drives CE# low, sends the Suspend command cycle
(75h/B0h), then drives CE# high. The Function Register indicates that the programming has been suspended by
setting the PSUS bit from “0” to “1”, but the device will not accept another command until it is ready. To determine
when the device will accept a new command, poll the WIP bit or wait the specified time t SUS. When PSUS bit is set
to “1”, the Write Enable Latch (WEL) bit clears to “0”.
PROGRAM/ERASE RESUME (PERRSM 7Ah/30h)
The Program/Erase Resume restarts the Program or Erase command that was suspended, and clears the suspend
status bit in the Function Register (ESUS or PSUS bits) to “0”. To execute the Program/Erase Resume operation,
the host drives CE# low, sends the Program/Erase Resume command cycle (7Ah/30h), then drives CE# high. A
cycle is two nibbles long, most significant nibble first. To issue another Erase Suspend operation after Erase
Resume operation, Erase Resume to another Erase Suspend delay (tRS) is required, but it could require longer
Erase time to complete Erase operation.
To determine if the internal, self-timed Write operation completed, poll the WIP bit.
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Table 8.7 Instructions accepted during Suspend
Instruction Allowed
Operation
Suspended
Name
Hex Code
Program or Erase
NORD
03h
Normal Read Mode
Program or Erase
4NORD
13h
4-byte Address Normal Read Mode
Program or Erase
FRD
0Bh
Fast Read Mode
Program or Erase
4FRD
0Ch
4-byte Address Fast Read Mode
Program or Erase
FRDIO
BBh
Fast Read Dual I/O
Program or Erase
4FRDIO
BCh
4-byte Address Fast Read Dual I/O
Program or Erase
FRDO
3Bh
Fast Read Dual Output
Program or Erase
4FRDO
3Ch
4-byte Address Fast Read Dual Output
Program or Erase
FRQIO
EBh
Fast Read Quad I/O
Program or Erase
4FRQIO
ECh
4-byte Address Fast Read Quad I/O
Program or Erase
FRQO
6Bh
Fast Read Quad Output
Program or Erase
4FRQO
6Ch
4-byte Address Fast Read Quad Output
Program or Erase
FRDTR
0Dh
Fast Read DTR Mode
Program or Erase
4FRDTR
0Eh
4-byte Address Fast Read DTR Mode
Program or Erase
FRDDTR
BDh
Fast Read Dual I/O DTR
Program or Erase
4FRDDTR
BEh
4-byte Address Fast Read Dual I/O DTR
Program or Erase
FRQDTR
EDh
Fast Read Quad I/O DTR
Program or Erase
4FRQDTR
EEh
4-byte Address Fast Read Quad I/O DTR
Program or Erase
WREN
06h
Write Enable
Program or Erase
WRDI
04hh
Write Disable
Program or Erase
RDSR
05h
Read Status Register
Program or Erase
RDFR
48h
Read Function Register
Program or Erase
RDBR
16h/C8h
Program or Erase
RDRP
61h
Read Read Parameters (Volatile)
Program or Erase
RDERP
81h
Read Extended Read Parameters (Volatile)
Program or Erase
RDID
ABh
Read Manufacturer and Product ID
Program or Erase
RDJDID
9Fh
Read Manufacturer and Product ID by JEDEC ID Command
Program or Erase
RDMDID
90h
Read Manufacturer and Device ID
Program or Erase
RDJDIDQ
AFh
Read JEDEC ID QPI mode
Program or Erase
RDUID
4Bh
Read Unique ID Number
Program or Erase
RDSFDP
5Ah
SFDP Read
Program or Erase
CLERP
82h
Clear Extended Read Register
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Read Bank Address Register
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Operation
Suspended
Program or Erase
Instruction Allowed
Name
PERRSM
Hex Code
7Ah/30h
Operation
Program/Erase Resume
Program or Erase
SRPV
C0/63h
Program or Erase
SERPV
83h
Program or Erase
WRBRV
17h/C5
Program or Erase
EN4B
B7h
Enter 4-byte Address Mode
Program or Erase
EX4B
29h
Exit 4-byte Address Mode
Program or Erase
RDPPB
FCh
Read PPB
Program or Erase
4RDPPB
F2h
4-byte Address Read PPB
Program or Erase
RDDYB
FAh
Read DYB
Program or Erase
4RDDYB
E0h
4-byte Address Read DYB
Program or Erase
RDPWD
E7h
Read Password
Program or Erase
RDPLB
A7h
Read PPB Lock Bit
Program or Erase
RDASP
2Bh
Read ASP
Program or Erase
RDDLP
41h
Read Data Learning Pattern
Program or Erase
WRVDLR
4Ah
Write Volatile DLP Register
Erase
SECLOCK
24h
Sector Lock
Erase
SECUNLOCK
26h
Sector Unlock
Erase
4SECUNLOCK
25h
4-byte Address Sector Unlock
Erase
PERSUS
75h/B0h
Erase
PP
02h
Serial Input Page Program
Erase
4PP
12h
4-byte Address Serial Input Page Program
Erase
PPQ
32h/38h
Quad Input Page Program
Erase
4PPQ
34h/3Eh
4-byte Address Quad Input Page Program
Erase
WRDYB
FBh
Write DYB
Erase
4WRDYB
E0h
4-byte Address Write DYB
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Set Extended Read Parameters (Volatile)
Write Bank Address Register (Volatile)
Program/Erase Suspend
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8.24 ENTER DEEP POWER DOWN (DP, B9h)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (enter
into Power-down mode). During this mode, standby current is reduced from I sb1 to Isb2. While in the Power-down
mode, the device is not active and all Write/Program/Erase instructions are ignored. The instruction is initiated by
driving the CE# pin low and shifting the instruction code into the device. The CE# pin must be driven high after the
instruction has been latched, or Power-down mode will not engage. Once CE# pin driven high, the Power-down
mode will be entered within the time duration of tDP. While in the Power-down mode only the Release from Powerdown/RDID instruction, which restores the device to normal operation, will be recognized. All other instructions are
ignored, including the Read Status Register instruction which is always available during normal operation. Ignoring
all but one instruction makes the Power Down state a useful condition for securing maximum write protection. It is
available in both SPI and QPI mode.
Figure 8.55 Enter Deep Power Down Mode Sequence In SPI Mode
tDP
CE #
Mode 3 0
1
2
3
4
5
6
7
SCK
Mode 0
SI
SO
Instruction = B9h
High Impedance
Figure 8.56 Enter Deep Power Down Mode Sequence In QPI Mode
tDP
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
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8.25 RELEASE DEEP POWER DOWN (RDPD, ABh)
The Release Deep Power-down/Read Device ID instruction is a multi-purpose command. To release the device
from the deep power-down mode, the instruction is issued by driving the CE# pin low, shifting the instruction code
into the device and driving CE# high.
Releasing the device from Power-down mode will take the time duration of tRES1 before normal operation is restored
and other instructions are accepted. The CE# pin must remain high during the t RES1 time duration. If the Release
Deep Power-down/RDID instruction is issued while an Erase, Program or Write cycle is in progress (WIP=1) the
instruction is ignored and will not have any effects on the current cycle.
Figure 8.57 Release Power Down Mode Sequence In SPI Mode
tRES1
CE #
Mode 3 0
1
2
3
4
5
6
7
SCK
Mode 0
SI
SO
Instruction = ABh
High Impedance
Figure 8.58 Release Power Down Mode Sequence In QPI Mode
tRES1
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
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ABh
104
IS25LP512M
IS25WP512M
8.26 SET READ PARAMETERS OPERATION (SRPNV: 65h, SRPV: C0h/63h)
Set Read Parameter Bits
This device supports configurable burst length and dummy cycles in both SPI and QPI mode by setting three bits
(P2, P1, P0) and four bits (P6, P5, P4, P3) within the Read Register, respectively. To set those bits the SRPNV
and SRPV operation instruction are used. Details regarding burst length and dummy cycles can be found in Table
6.9, Table 6.10, and Table 6.11. HOLD#/RESET# function selection (P7) bit in the Read Register can be set with
the SRPNV and SRPV operation as well, in order to select HOLD#/RESET# pin as RESET# or HOLD#.
For the device with dedicated RESET# pin (or ball), RESET# pin (or ball) will be a separate pin (or ball) and it is
independent of the P7 bit setting in Read Register.
SRPNV is used to set the non-volatile Read Register, while SRPV is used to set the volatile Read Register.
To write non-volatile Read Parameter bits, a standard Write Enable (06h) instruction must previously have been
executed for the device to accept SRPNV(65h) instruction (Status Register bit WEL must equal “1”).
To write volatile Read Parameter bits (SRPV), 63h or C0h command can be used.
When using 63h instruction, a standard Write Enable (06h) instruction must previously have been executed for the
device to accept SRPV (63h) instruction (Status Register bit WEL must equal “1”).
But C0h instruction does not require a standard Write Enable (06h) operation. (Status Register bit WEL remains
“0”).
Note: When SRPNV is executed, the volatile Read Register is set as well as the non-volatile Read Register.
Figure 8.59 Set Read Parameters Sequence In SPI Mode
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2
1
0
SCK
Mode 0
Data In
SI
SO
Instruction = 65h or C0h/63h
7
6
2
3
7:4
3:0
5
4
3
High Impedence
Figure 8.60 Set Read Parameters Sequence In QPI Mode
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
65h or
C0h/63h
Data In
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Read with “8/16/32/64-Byte Wrap Around”
The device is capable of burst read with wrap around in both SPI and QPI mode. The size of burst length is
configurable by using P0, P1, and P2 bits in Read Register. P2 bit (Wrap enable) enables the burst mode feature.
P0 and P1 define the size of burst. Burst lengths of 8, 16, 32, and 64 bytes are supported. By default, address
increases by one up through the entire array. By setting the burst length, the data being accessed can be limited
to the length of burst boundary within a 256 byte page. The first output will be the data at the initial address which
is specified in the instruction. Following data will come out from the next address within the burst boundary. Once
the address reaches the end of boundary, it will automatically move to the first address of the boundary. CE# high
will terminate the command.
For example, if burst length of 8 and initial address being applied is 0h, following byte output will be from address
00h and continue to 01h,..,07h, 00h, 01h… until CE# terminates the operation. If burst length of 8 and initial address
being applied is FEh(254d), following byte output will be from address FEh and continue to FFh, F8h, F9h, FAh,
FBh, FCh, FDh, and repeat from FEh until CE# terminates the operation.
The commands, “SRPV (65h) or SRPNV (C0h or 63h)”, are used to configure the burst length. If the following data
input is one of “00h”,”01h”,”02h”, and ”03h”, the device will be in default operation mode. It will be continuous burst
read of the whole array. If the following data input is one of “04h”,”05h”,”06h”, and ”07h”, the device will set the
burst length as 8,16,32 and 64, respectively.
To exit the burst mode, another “C0h or 63h” command is necessary to set P2 to 0. Otherwise, the burst mode will
be retained until either power down or reset operation. To change burst length, another “C0h or 63h” command
should be executed to set P0 and P1 (Detailed information in Table 6.9 Burst Length Data). All read commands
will operate in burst mode once the Read Register is set to enable burst mode.
Refer to Figure 8.59 and Figure 8.60 for instruction sequence.
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8.27 SET EXTENDED READ PARAMETERS OPERATION (SERPNV: 85h, SERPV: 83h)
Set Read Operational Driver Strength
This device supports configurable Operational Driver Strength in both SPI and QPI modes by setting three bits
(ODS0, ODS1, ODS2) within the Extended Read Register. To set the ODS bits the SERPNV and SERPV operation
instructions are required. The device’s driver strength can be reduced as low as 12.50% of full drive strength.
Details regarding the driver strength can be found in Table 6.14.
SERPNV is used to set the non-volatile Extended Read register, while SERPV is used to set the volatile Extended
Read register.
Notes:
1. The default driver strength is set to 50%.
2. When SERPNV is executed, the volatile Read Extended Register is set as well as the non-volatile Read Extended
Register.
Figure 8.61 Set Extended Read Parameters Sequence In SPI Mode
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2
1
0
SCK
Mode 0
Data In
SI
SO
Instruction = 85h/83h
7
6
5
4
3
High Impedence
Figure 8.62 Set Extended Read Parameters Sequence In QPI Mode
CE#
Mode 3 0
1
2
3
7:4
3:0
SCK
Mode 0
IO[3:0]
85h/83h
Data In
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8.28 READ READ PARAMETERS OPERATION (RDRP, 61h)
Prior to, or after setting Read Register, the data of the Read Register can be confirmed by the RDRP command.
The instruction is only applicable for the volatile Read Register, not for the non-volatile Read Register.
Figure 8.63 Read Read Parameters Sequence In SPI Mode
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Mode 0
SI
Instruction = 61h
tV
SO
Data Out
7
6
5
4
3
2
1
Figure 8.64 Read Read Parameters Sequence In QPI Mode
CE#
Mode 3 0
1
2
3
SCK
Mode 0
tV
IO[3:0]
61h
7:4
3:0
Data Out
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8.29 READ EXTENDED READ PARAMETERS OPERATION (RDERP, 81h)
Prior to, or after setting Extended Read Register, the data of the Extended Read Register can be confirmed by the
RDERP command. The instruction is only applicable for the volatile Extended Read Register, not for the nonvolatile Extended Read Register.
Figure 8.65 Read Extended Read Parameters Sequence In SPI Mode
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Mode 0
SI
Instruction = 81h
tV
SO
Data Out
7
6
5
4
3
2
1
Figure 8.66 Read Extended Read Parameters Sequence In QPI Mode
CE#
Mode 3 0
1
2
3
SCK
Mode 0
tV
IO[3:0]
81h
7:4
3:0
Data Out
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8.30 CLEAR EXTENDED READ REGISTER OPERATION (CLERP, 82h)
A Clear Extended Read Register (CLERP) instruction clears PROT_E, P_ERR, and E_ERR error bits in the
Extended Read Register to “0” when the error bits are set to “1”. Once the error bits are set to “1”, they remains set
to “1” until they are cleared to “0” with a CLERP command.
Figure 8.67 Clear Extended Read Register Sequence In SPI Mode
CE#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Instruction = 82h
SI
High Impedance
SO
Figure 8.68 Clear Extended Read Register Sequence In QPI Mode
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
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110
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8.31 READ PRODUCT IDENTIFICATION (RDID, ABh)
The Release from Power-down/Read Device ID instruction is a multi-purpose instruction. It can support both SPI
and QPI modes. The Read Product Identification (RDID) instruction is for reading out the old style of 8-bit Electronic
Signature, whose values are shown as the table of Product Identification.
The RDID instruction code is followed by three dummy bytes, each bit being latched-in on SI during the rising SCK
edge. Then the Device ID is shifted out on SO with the MSB first, each bit been shifted out during the falling edge
of SCK. The RDID instruction is ended by driving CE# high. The Device ID (ID7-ID0) outputs repeatedly if additional
clock cycles are continuously sent to SCK while CE# is at low.
Table 8.8 Product Identification
Manufacturer ID
(MF7-MF0)
ISSI Serial Flash
9Dh
Instruction
ABh
90h
Part Number
Device ID (ID7-ID0)
9Fh
Memory Type + Capacity
(ID15-ID0)
IS25LP512M
19h
601Ah
IS25WP512M
19h
701Ah
Figure 8.69 Read Product Identification Sequence
CE #
Mode 3 0
1
...
7
8
9
...
31
32
33
...
39
SCK
Mode 0
SI
Instruction = ABh
3 Dummy Bytes
tV
SO
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Data Out
Device ID
(ID7-ID0)
111
IS25LP512M
IS25WP512M
Figure 8.70 Read Product Identification Sequence In QPI Mode
CE#
Mode 3 0
1
2
3
4
5
6
7
8
9
SCK
Mode 0
tV
IO[3:0]
ABh
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Device ID
(ID7-ID0)
112
IS25LP512M
IS25WP512M
8.32 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9Fh; RDJDIDQ, AFh)
The JEDEC ID READ instruction allows the user to read the manufacturer and product ID of devices. Refer to Table
8.8 Product Identification for Manufacturer ID and Device ID. After the JEDEC ID READ command (9Fh in SPI
mode, AFh in QPI mode) is input, the Manufacturer ID is shifted out MSB first followed by the 2-byte electronic ID
(ID15-ID0) that indicates Memory Type and Capacity, one bit at a time. Each bit is shifted out during the falling
edge of SCK. If CE# stays low after the last bit of the 2-byte electronic ID, the Manufacturer ID and 2-byte electronic
ID will loop until CE# is pulled high.
Figure 8.71 Read Product Identification by JEDEC ID Read Sequence in SPI mode
CE #
Mode 3 0
1
...
7
8
9
15
...
16
17
...
23
24
25
...
SCK
Mode 0
SI
Instruction = 9Fh
tV
Manufacturer ID
(MF7-MF0)
SO
Capacity
(ID7-ID0)
Memory Type
(ID15-ID8)
Figure 8.72 RDJDID and RDJDIDQ (Read JEDEC ID) Sequence In QPI Mode
CE#
Mode 3 0
1
2
3
4
5
6
7
SCK
Mode 0
IO[3:0]
tV
9Fh/AFh
7:4
3:0
MF7-MF0
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3:0
ID15-ID8
7:4
3:0
ID7-ID0
113
31
IS25LP512M
IS25WP512M
8.33 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90h)
The Read Device Manufacturer and Device ID (RDMDID) instruction allows the user to read the Manufacturer and
product ID of devices. Refer to Table 8.8 Product Identification for Manufacturer ID and Device ID. The RDMDID
instruction code is followed by two dummy bytes and one byte address (A7~A0), each bit being latched-in on SI
during the rising edge of SCK. If one byte address is initially set as A0 = 0, then the Manufacturer ID is shifted out
on SO with the MSB first followed by the device ID (ID7- ID0). Each bit is shifted out during the falling edge of SCK.
If one byte address is initially set as A0 = 1, then Device ID7-ID0 will be read first followed by the Manufacturer ID.
The Manufacturer and Device ID can be read continuously alternating between the two until CE# is driven high.
Figure 8.73 Read Product Identification by RDMDID Sequence In SPI Mode (A0=0)
CE #
Mode 3 0
1
...
7
8
9
...
31
32
33
...
39
40
41
...
47
SCK
Mode 0
SI
Instruction = 90h
3-byte Address
tV
Device ID
(ID7-ID0)
Manufacturer ID
(MF7-MF0)
SO
Notes:
1. ADDRESS A0 = 0, will output the 1-byte Manufacturer ID (MF7-MF0) 1-byte Device ID (ID7-ID0)
ADDRESS A0 = 1, will output the 1-byte Device ID (ID7-ID0) 1-byte Manufacturer ID (MF7-MF0)
2. The Manufacturer and Device ID can be read continuously and will alternate from one to the other until CE# pin is
pulled high.
Figure 8.74 Read Product Identification by RDMDID Sequence In QPI Mode (A0=0)
CE#
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
SCK
Mode 0
tV
IO[3:0]
90h
23:20 19:16 15:12 11:8
Instruction
3-byte Address
7:4
3:0
7:4
3:0
7:4
3:0
Manufacturer Device ID
ID (MF7-MF0) (ID7-ID0)
Notes:
1. ADDRESS A0 = 0, will output the 1-byte Manufacturer ID (MF7-MF0) 1-byte Device ID (ID7-ID0)
ADDRESS A0 = 1, will output the 1-byte Device ID (ID7-ID0) 1-byte Manufacturer ID (MF7-MF0)
2. The Manufacturer and Device ID can be read continuously and will alternate from one to the other until CE# pin is
pulled high.
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8.34 READ UNIQUE ID NUMBER (RDUID, 4Bh)
The Read Unique ID Number (RDUID) instruction accesses a factory-set read-only 16-byte number that is unique
to the device. The ID number can be used in conjunction with user software methods to help prevent copying or
cloning of a system. The RDUID instruction is instated by driving the CE# pin low and shifting the instruction code
(4Bh) followed by 3 address bytes and dummy cycles (configurable, default is 8 clocks). After which, the 16-byte
ID is shifted out on the falling edge of SCK as shown below.
As a result, the sequence of RDUID instruction is same as FAST READ. RDUID sequence in QPI mode is also
same as FAST READ sequence in QPI mode except for the instruction code. Refer to the FAST READ operation
in QPI mode.
Note: 16 bytes of data will repeat as long as CE# is low and SCK is toggling.
Figure 8.75 RDUID Sequence In SPI Mode
CE #
Mode 3 0
1
...
7
8
9
...
31
32
33
...
39
40
41
...
47
...
SCK
Mode 0
SI
Instruction = 4Bh
3 Byte Address
Dummy Cycles
tV
SO
Data Out
Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.
A[23:16]
A[15:9]
A[8:4]
A[3:0]
XXh
XXh
00h
0h Byte address
XXh
XXh
00h
1h Byte address
XXh
XXh
00h
2h Byte address
XXh
XXh
00h
…
Table 8.9 Unique ID Addressing
XXh
XXh
00h
Fh Byte address
Note: XX means “don’t care”.
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8.35 READ SFDP OPERATION (RDSFDP, 5Ah)
The Serial Flash Discoverable Parameters (SFDP) standard provides a consistent method of describing the
functions and features of serial Flash devices in a standard set of internal parameter tables. These parameters can
be interrogated by host system software to enable adjustments needed to accommodate divergent features from
multiple vendors. For more details please refer to the JEDEC Standard JESD216 (Serial Flash Discoverable
Parameters).
The sequence of issuing RDSFDP instruction in SPI mode is:
CE# goes low Send RDSFDP instruction (5Ah) Send 3 address bytes on SI pin 8 dummy cycles on SI pin
Read SFDP code on SO End RDSFDP operation by driving CE# high at any time during data out. Refer to
ISSI’s Application note for SFDP table. The data at the addresses that are not specified in SFDP table are
undefined.
RDSFDP Sequence is not supported in QPI mode.
Figure 8.76 RDSFDP (Read SFDP) Sequence
CE #
Mode 3 0
1
...
7
8
9
...
31
32
33
...
39
40
41
...
47
...
SCK
Mode 0
SI
Instruction = 5Ah
3 Byte Address
Dummy Cycles
tV
SO
Data Out
8.36 NO OPERATION (NOP, 00h)
The No Operation command solely cancels a Reset Enable command and has no impact on any other commands.
It is available in both SPI and QPI modes. To execute a NOP, the host drives CE# low, sends the NOP command
cycle (00h), then drives CE# high.
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8.37 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h)) AND HARDWARE RESET
The Software Reset operation is used as a system reset that puts the device in normal operating mode. During the
Reset operation, the value of volatile registers will default back to the value in the corresponding non-volatile
register. However, the volatile FREEZE bit and the volatile PPB Lock bit in the PPB Lock Register are not changed
by Software Reset. In all other respects, Software Reset is the same as Hardware Reset. This operation consists
of two commands: Reset-Enable (RSTEN) and Reset (RST). The operation requires the Reset-Enable command
followed by the Reset command. Any command other than the Reset command after the Reset-Enable command
will disable the Reset-Enable.
Execute the CE# pin low sends the Reset-Enable command (66h), and drives CE# high. Next, the host drives
CE# low again, sends the Reset command (99h), and pulls CE# high.
Only if the RESET# pin is enabled, Hardware Reset function is available.
For the device with HOLD#/RESET#, the RESET# pin will be solely applicable in SPI mode and when the QE bit =
“0”. For the device with dedicated RESET# (Dedicated RESET# Disable bit is “0” in Function Register), the RESET#
pin is always applicable regardless of the QE bit value in Status Register and HOLD#/RESET# selection bit (P7) in
Read Register in SPI/QPI mode.
In order to activate Hardware Reset, the RESET# pin (or ball) must be driven low for a minimum period of t RESET
(100ns). Drive RESET# low for a minimum period of tRESET will interrupt any on-going internal and external
operations, release the device from deep power down mode1, disable all input signals, force the output pin enter a
state of high impedance, and reset all the read parameters.
The required wait time after activating a HW Reset before the device will accept another instruction is tHWRST of
35us.
The Software/Hardware Reset during an active Program or Erase operation aborts the operation, which can result
in corrupting or losing the data of the targeted address range. Depending on the prior operation, the reset timing
may vary. Recovery from a Write operation will require more latency than recovery from other operations.
Note1: The Status and Function Registers remain unaffected.
Figure 8.77 Software Reset Enable and Software Reset Sequence (RSTEN, 66h + RST, 99h)
CE#
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
SCK
Mode 0
SI
Instruction = 66h
Instruction = 99h
High Impedance
SO
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14
15
IS25LP512M
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Figure 8.78 Software Reset Enable and Software Reset Sequence In QPI Mode (RSTEN, 66h + RST, 99h)
CE#
Mode 3 0
1
0
1
SCK
Mode 0
IO[3:0]
99h
66h
8.38 SECURITY INFORMATION ROW
The security Information Row is comprised of an additional 4 x 256 bytes of programmable information. The security
bits can be reprogrammed by the user. Any program security instruction issued while an erase, program or write
cycle is in progress is rejected without having any effect on the cycle that is in progress.
Table 8.10 Information Row Valid Address Range
Address Assignment
IRL0 (Information Row Lock0)
IRL1
IRL2
IRL3
A[23:16]
00h
00h
00h
00h
A[15:8]
00h
10h
20h
30h
A[7:0]
Byte address
Byte address
Byte address
Byte address
Bit 7~4 of the Function Register is used to permanently lock the programmable memory array.
When Function Register bit IRLx = “0”, the 256 bytes of the programmable memory array can be programmed.
When Function Register bit IRLx = “1”, the 256 bytes of the programmable memory array function as read only.
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8.39 INFORMATION ROW ERASE OPERATION (IRER, 64h)
Information Row Erase (IRER) instruction erases the data in the Information Row x (x: 0~3) array. Prior to the
operation, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is
automatically reset after the completion of the operation.
The sequence of IRER operation: Pull CE# low to select the device Send IRER instruction code Send three
address bytes Pull CE# high. CE# should remain low during the entire instruction sequence. Once CE# is pulled
high, Erase operation will begin immediately. The internal control logic automatically handles the erase voltage and
timing.
Figure 8.79 IRER (Information Row Erase) Sequence
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
...
28
29
30
31
1
0
SCK
Mode 0
3-byte Address
SI
SO
Instruction = 64h
23
22
21
...
3
2
High Impedance
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8.40 INFORMATION ROW PROGRAM OPERATION (IRP, 62h)
The Information Row Program (IRP) instruction allows up to 256 bytes of data to be programmed into the memory
in a single operation. Before the execution of IRP instruction, the Write Enable Latch (WEL) must be enabled
through a Write Enable (WREN) instruction.
The IRP instruction code, three address bytes and program data (1 to 256 bytes) should be sequentially input.
Three address bytes has to be input as specified in the Table 8.10 Information Row Valid Address Range. Program
operation will start once the CE# goes high, otherwise the IRP instruction will not be executed. The internal control
logic automatically handles the programming voltages and timing. The progress or completion of the program
operation can be determined by reading the WIP bit. If the WIP bit is “1”, the program operation is still in progress.
If WIP bit is “0”, the program operation has completed.
If more than 256 bytes data are sent to a device, the address counter rolls over within the same page. The
previously latched data are discarded and the last 256 bytes data are kept to be programmed into the page. The
starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap around
to the beginning of the same page. If the data to be programmed are less than a full page, the data of all other
bytes on the same page will remain unchanged.
Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s. A
byte cannot be reprogrammed without first erasing the corresponding Information Row array which is one of
IR0~3.
Figure 8.80 IRP (Information Row Program) Sequence
1
...
7
8
9
...
31
32
33
...
39
...
...
2079
Mode 3 0
2072
CE #
SCK
Mode 0
SI
SO
3-byte Address
Instruction = 62h
23
22
...
Data In 1
0
7
6
...
Data In 256
0
...
7
...
High Impedance
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8.41 INFORMATION ROW READ OPERATION (IRRD, 68h)
The IRRD instruction is used to read memory data.
The IRRD instruction code is followed by three address bytes (A23 - A0) and dummy cycles (configurable, default
is 8 clocks), transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the first data
byte addressed is shifted out on the SO line, with each bit shifted out at a maximum frequency f CT, during the falling
edge of SCK.
The address is automatically incremented by one after each byte of data is shifted out. Once the address reaches
the last address of each 256 byte Information Row, the next address will not be valid and the data of the address
will be garbage data. It is recommended to repeat four times IRRD operation that reads 256 byte with a valid starting
address of each Information Row in order to read all data in the 4 x 256 byte Information Row array. The IRRD
instruction is terminated by driving CE# high (VIH).
If an IRRD instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not have any effects on the current cycle
The sequence of IRRD instruction is same as Fast Read except for the instruction code. IRRD QPI sequence is
same as Fast Read QPI except for the instruction code. Refer to the Fast Read QPI operation.
Figure 8.81 IRRD (Information Row Read) Sequence
CE #
Mode 3
0
1
...
7
8
9
...
31
32
33
...
39
40
41
...
47
...
SCK
Mode 0
SI
Instruction = 68h
3 Byte Address
Dummy Cycles
tV
SO
Data Out
Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.
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8.42 FAST READ DTR MODE OPERATION (FRDTR, 0Dh or 4FRDTR, 0Eh)
The FRDTR/4FRDTR instruction is for doubling the data in and out. Signals are triggered on both rising and falling
edge of clock. The address is latched on both rising and falling edge of SCK, and data of each bit shifts out on both
rising and falling edge of SCK. The 2-bit address can be latched-in at one clock, and 2-bit data can be read out at
one clock, which means one bit at the rising edge of clock, the other bit at the falling edge of clock.
The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte of data is shifted out, so the whole memory can be read out in a single FRDTR/4FRDTR instruction.
The address counter rolls over to 0 when the highest address is reached.
0Dh (EXTADD=0) is followed by a 3-byte address (A23-A0) or
0Dh (EXTADD=1) is followed by a 4-byte address (A31-A0) or
0Eh is followed by a 4-byte address (A31-A0)
The sequence of issuing FRDTR/4FRDTR instruction is: CE# goes low Sending FRDTR/4FRDTR instruction
code (1bit per clock) 3-byte or 4-byte address on SI (2-bit per clock) as above 8 dummy clocks (configurable,
default is 8 clocks) on SI Data out on SO (2-bit per clock) End FRDTR/4FRDTR operation via driving CE#
high at any time during data out.
While a Program/Erase/Write Status Register cycle is in progress, FRDTR/4FRDTR instruction will be rejected
without any effect on the current cycle.
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Figure 8.82 FRDTR Sequence (0Dh [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
...
19
20
21
SCK
Mode 0
3-byte Address
SI
Instruction = 0Dh
23 22 21 20 19 18 17
...
0
High Impedance
SO
CE #
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
...
SCK
SI
8 Dummy Cycles
tV
Data Out 1
SO
Data Out 2
Data Out ...
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 ...
Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.
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Figure 8.83 FRDTR Sequence (0Dh [EXTADD=1] or 0Eh, 4-byte address)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
...
27
28
29
SCK
Mode 0
4-byte Address
SI
Instruction = 0Dh/0Eh
31 30 29 28 27 26 25
...
0
High Impedance
SO
CE #
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
...
SCK
SI
8 Dummy Cycles
tV
Data Out 1
SO
Data Out 2
Data Out ...
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 ...
Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.
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FAST READ DTR OPERATION IN QPI MODE (FRDTR, 0Dh or 4FRDTR, 0Eh)
The FRDTR/4FRDTR instruction in QPI mode utilizes all four IO lines to input the instruction code so that only two
clocks are required, while the FRDTR/4FRDTR instruction in SPI mode requires that the byte-long instruction code
is shifted into the device only via IO0 (SI) line in eight clocks. In addition, subsequent address and data out are
shifted in/out via all four IO lines unlike the FRDTR/4FRDTR instruction. Eventually this operation is same as the
FRQDTR/4FRQDTR in QPI mode, but the only different thing is that AX mode is not available in the
FRDTR/4FRDTR operation in QPI mode.
0Dh (EXTADD=0) is followed by a 3-byte address (A23-A0) or
0Dh (EXTADD=1) is followed by a 4-byte address (A31-A0) or
0Eh is followed by a 4-byte address (A31-A0)
The sequence of issuing FRDTR/4FRDTR instruction in QPI mode is: CE# goes low Sending FRDTR/4FRDTR
QPI instruction (4-bit per clock) 24-bit or 32-bit address interleave on IO3, IO2, IO1 & IO0 (8-bit per clock) as
above 6 dummy clocks (configurable, default is 6 clocks) Data out interleave on IO3, IO2, IO1 & IO0 (8-bit
per clock) End FRDTR/4FRDTR operation in QPI mode by driving CE# high at any time during data out.
If the FRDTR/4FRDTR instruction in QPI mode is issued while an Erase, Program or Write cycle is in process is in
progress (WIP=1), the instruction will be rejected without any effect on the current cycle.
Figure 8.84 FRDTR Sequence In QPI Mode (0Dh [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
...
SCK
Mode 0
IO0
IO1
IO2
IO3
Instruction
= 0Dh
6 Dummy Cycles
3-byte Address
tV
Data Data
Out Out
4
0
20 16 12 8 4 0
4 0 4 0 ...
5
1
21 17 13 9 5 1
5 1 5 1 ...
6
2
22 18 14 10 6 2
6 2 6 2 ...
7
3
23 19 15 11 7 3
7 3 7 3 ...
Notes:
1. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
2. Sufficient dummy cycles are required to avoid I/O contention.
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Figure 8.85 FRDTR Sequence In QPI Mode (0Dh [EXTADD=1] or 0Eh, 4-byte address)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
...
SCK
Mode 0
IO0
IO1
IO2
IO3
Instruction
= 0Dh/0Eh
6 Dummy Cycles
4-byte Address
tV
Data
Out
4
0
28 24 20 16 12 8 4 0
4 0 ...
5
1
29 25 21 17 13 9 5 1
5 1 ...
6
2
30 26 22 18 14 10 6 2
6 2 ...
7
3
31 27 23 19 15 11 7 3
7 3 ...
Notes:
1. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
2. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.
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8.43 FAST READ DUAL IO DTR MODE OPERATION (FRDDTR, BDh or 4FRDDTR, BEh)
The FRDDTR/4FRDDTR instruction enables Double Transfer Rate throughput on dual I/O of the device in read
mode. The address (interleave on dual I/O pins) is latched on both rising and falling edge of SCK, and the data
(interleave on dual I/O pins) shift out on both rising and falling edge of SCK. The 4-bit address can be latched-in at
one clock, and 4-bit data can be read out at one clock, which means two bits at the rising edge of clock, the other
two bits at the falling edge of clock.
The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte of data is shifted out, so the whole memory can be read out with a single FRDDTR/4FRDDTR
instruction. The address counter rolls over to 0 when the highest address is reached. Once writing
FRDDTR/4FRDDTR instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1bit.
BDh (EXTADD=0) is followed by a 3-byte address (A23-A0) or
BDh (EXTADD=1) is followed by a 4-byte address (A31-A0) or
BEh is followed by a 4-byte address (A31-A0)
The sequence of issuing FRDDTR/4FRDDTR instruction is: CE# goes low Sending FRDDTR/4FRDDTR
instruction (1-bit per clock) 24-bit or 32-bit address interleave on IO1 & IO0 (4-bit per clock) as above 4 dummy
clocks (configurable, default is 4 clocks) on IO1 & IO0 Data out interleave on IO1 & IO0 (4-bit per clock) End
FRDDTR/4FRDDTR operation via pulling CE# high at any time during data out (Please refer to Figures 8.86 and
8.87 for 2 x I/O Double Transfer Rate Read Mode Timing Waveform).
If AXh (where X is don’t care) is input for the mode bits during dummy cycles, the device will enter AX read operation
mode which enables subsequent FRDDTR/4FRDDTR execution skips command code. It saves cycles as
described in Figures 8.88 and 8.89. When the code is different from AXh (where X is don’t care), the device exits
the AX read operation. After finishing the read operation, device becomes ready to receive a new command.
If the FRDDTR/4FRDDTR instruction is issued while an Erase, Program or Write cycle is in process is in progress
(WIP=1), the instruction will be rejected without any effect on the current cycle.
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Figure 8.86 FRDDTR Sequence (BDh [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
...
13
14
SCK
Mode 0
3-byte Address
IO0
Instruction = BDh
22 20 18 16 14 12 10
4 Dummy Cycles
...
0 6 4
Mode Bits
High Impedance
IO1
23 21 19 17 15 13 11
...
1 7 5
CE #
15
16
17
18
19
20
21
22
23
24
25
26
27
28
...
29
SCK
tV
IO0
2 0
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 ...
Mode Bits
IO1
3 1
7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 ...
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode
bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.
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Figure 8.87 FRDDTR Sequence (BDh [EXTADD=1] or BEh, 4-byte address)
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
...
17
18
SCK
Mode 0
4-byte Address
IO0
Instruction = BDh/BEh
30 28 26 24 22 20 18
4 Dummy Cycles
...
0 6 4
Mode Bits
High Impedance
IO1
31 29 27 25 23 21 19
...
1 7 5
CE #
19
20
21
22
23
24
25
26
27
28
29
30
31
32
...
33
SCK
tV
IO0
2 0
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 ...
Mode Bits
IO1
3 1
7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 ...
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode
bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.
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Figure 8.88 FRDDTR AX Read Sequence (BDh [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
2
...
6
7
8
9
10
11
12
13
14
15
16
...
SCK
Mode 0
4 Dummy Cycles
tV
3-byte Address
IO0
22 20 18 16 14 12 10
...
Data Out
Data Out
Data Out
6 4 2 0 6 4 2 0 6 4 2 0 ...
0 6 4 2 0
Mode Bits
IO1
23 21 19 17 15 13 11
...
7 5 3 1 7 5 3 1 7 5 3 1 ...
1 7 5 3 1
Notes:
1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.
Figure 8.89 FRDDTR AX Read Sequence (BDh [EXTADD=1] or BEh, 4-byte address)
CE #
Mode 3 0
1
2
...
8
9
10
11
12
13
14
15
16
17
18
...
SCK
Mode 0
4 Dummy Cycles
4-byte Address
IO0
30 28 26 24 22 20 18
...
0 6 4 2 0
tV
Data Out
Data Out
Data Out
6 4 2 0 6 4 2 0 6 4 2 0 ...
Mode Bits
IO1
31 29 27 25 23 21 19
...
1 7 5 3 1
7 5 3 1 7 5 3 1 7 5 3 1 ...
Notes:
1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.
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8.44 FAST READ QUAD IO DTR MODE OPERATION IN SPI MODE (FRQDTR, EDh or 4FRQDTR, EEh)
The FRQDTR/4FRQDTR instruction enables Double Transfer Rate throughput on quad I/O of the device in read
mode.
A Quad Enable (QE) bit of Status Register must be set to "1" before sending the Fast Read Quad I/O DTR
instruction.
The address (interleave on 4 I/O pins) is latched on both rising and falling edge of SCK, and data (interleave on 4
I/O pins) shift out on both rising and falling edge of SCK. The 8-bit address can be latched-in at one clock, and 8bit data can be read out at one clock, which means four bits at the rising edge of clock, the other four bits at the
falling edge of clock.
The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte data is shifted out, so the whole memory can be read out with a single FRQDTR/4FRQDTR instruction. The address counter rolls over to 0 when the highest address is reached. Once writing FRQDTR/4FRQDTR
instruction, the following address/dummy/data out will perform as 8-bit instead of previous 1-bit.
EDh (EXTADD=0) is followed by a 3-byte address (A23-A0) or
EDh (EXTADD=1) is followed by a 4-byte address (A31-A0) or
EEh is followed by a 4-byte address (A31-A0)
The sequence of issuing FRQDTR/4FRQDTR instruction is: CE# goes low Sending FRQDTR/4FRQDTR
instruction (1-bit per clock) 24-bit or 32-bit address interleave on IO3, IO2, IO1 & IO0 (8-bit per clock) as above
6 dummy clocks (configurable, default is 6 clocks) Data out interleave on IO3, IO2, IO1 & IO0 (8-bit per clock)
End FRQDTR/4FRQDTR operation by driving CE# high at any time during data out.
If AXh (where X is don’t care) is input for the mode bits during dummy cycles, the device will enter AX read operation
mode which enables subsequent FRQDTR/4FRQDTR execution skips command code. It saves cycles as
described in Figures 8.92 and 8.93. When the code is different from AXh (where X is don’t care), the device exits
the AX read operation. After finishing the read operation, device becomes ready to receive a new command.
If the FRQDTR/4FRQDTR instruction is issued while an Erase, Program or Write cycle is in process is in progress
(WIP=1), the instruction will be rejected without any effect on the current cycle.
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Figure 8.90 FRQDTR Sequence In SPI Mode (EDh [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
11
12
SCK
Mode 0
3-byte Address
IO0
Instruction = EDh
6 Dummy Cycles
20 16 12 8 4 0 4 0
High Impedance
IO1
21 17 13 9 5 1 5 1
IO2
22 18 14 10 6 2 6 2
IO3
23 19 15 11 7 3 7 3
Mode Bits
CE #
13
14
15
16
17
18
19
20
21
22
23
24
25
26
...
SCK
Data Data Data Data Data Data Data Data Data Data
tV Out Out Out Out Out Out Out Out Out Out
IO0
4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 ...
IO1
5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 ...
IO2
6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 ...
IO3
7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 ...
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode
bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.
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Figure 8.91 FRQDTR Sequence In SPI Mode (EDh [EXTADD=1] or EEh, 4-byte address)
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
11
12
13
SCK
Mode 0
4-byte Address
IO0
Instruction = EDh/EEh
6 Dummy Cycles
28 24 20 16 12 8 4 0 4 0
High Impedance
IO1
29 25 21 17 13 9 5 1 5 1
IO2
30 26 22 18 14 10 6 2 6 2
IO3
31 27 23 19 15 11 7 3 7 3
Mode Bits
CE #
14
15
16
17
18
19
20
21
22
23
24
25
26
27
...
SCK
Data Data Data Data Data Data Data Data Data Data
tV Out Out Out Out Out Out Out Out Out Out
IO0
4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 ...
IO1
5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 ...
IO2
6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 ...
IO3
7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 ...
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode
bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.
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Figure 8.92 FRQDTR AX Read Sequence (EDh [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
...
SCK
Mode 0
6 Dummy Cycles
3-byte Address
IO0
IO1
IO2
IO3
Data Data Data Data
tV Out Out Out Out
20 16 12 8 4 0 4 0
4 0 4 0 4 0 4 0 ...
21 17 13 9 5 1 5 1
5 1 5 1 5 1 5 1 ...
22 18 14 10 6 2 6 2
6 2 6 2 6 2 6 2 ...
23 19 15 11 7 3 7 3
7 3 7 3 7 3 7 3 ...
Mode Bits
Notes:
1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.
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Figure 8.93 FRQDTR AX Read Sequence (EDh [EXTADD=1] or EEh, 4-byte address)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
...
SCK
Mode 0
6 Dummy Cycles
4-byte Address
IO0
IO1
IO2
IO3
Data Data Data Data
tV Out Out Out Out
28 24 20 16 12 8 4 0 4 0
4 0 4 0 4 0 4 0 ...
29 25 21 17 13 9 5 1 5 1
5 1 5 1 5 1 5 1 ...
30 26 22 18 14 10 6 2 6 2
6 2 6 2 6 2 6 2 ...
31 27 23 19 15 11 7 3 7 3
7 3 7 3 7 3 7 3 ...
Mode Bits
Notes:
1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.
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FAST READ QUAD IO DTR MODE OPERATION IN QPI MODE (FRQDTR, EDh OR 4FRQDTR, EEh)
The FRQDTR/4FRQDTR instruction in QPI mode utilizes all four IO lines to input the instruction code so that only
two clocks are required, while the FRQDTR/4FRQDTR instruction in SPI mode requires that the byte-long
instruction code is shifted into the device only via IO0 line in eight clocks. As a result, 6 command cycles will be
reduced by the FRQDTR/4FRQDTR instruction in QPI mode. In addition, subsequent address and data out are
shifted in/out via all four IO lines like the FRQDTR/4FRQDTR instruction. In fact, except for the command cycle,
the FRQDTR/4FRQDTR operation in QPI mode is exactly same as the FRQDTR/4FRQDTR operation in SPI mode.
It is not required to set QE bit to “1”.before Fast Read Quad I/O DTR instruction in QPI mode.
EDh (EXTADD=0) is followed by a 3-byte address (A23-A0) or
EDh (EXTADD=1) is followed by a 4-byte address (A31-A0) or
EEh is followed by a 4-byte address (A31-A0)
The sequence of issuing FRQDTR/4FRQDTR instruction is: CE# goes low Sending FRQDTR/4FRQDTR
instruction (4-bit per clock) 24-bit or 32-bit address interleave on IO3, IO2, IO1 & IO0 (8-bit per clock) as above
6 dummy clocks (configurable, default is 6 clocks) Data out interleave on IO3, IO2, IO1 & IO0 (8-bit per clock)
End FRQDTR/4FRQDTR operation by driving CE# high at any time during data out.
If AXh (where X is don’t care) is input for the mode bits during dummy cycles, the device will enter AX read operation
mode which enables subsequent FRQDTR/4FRQDTR in QPI mode execution skips command code. It saves cycles
as described in Figures 8.92 and 8.93. When the code is different from AXh (where X is don’t care), the device
exits the AX read operation. After finishing the read operation, device becomes ready to receive a new command.
If the FRQDTR/4FRQDTR instruction in QPI mode is issued while an Erase, Program or Write cycle is in process
is in progress (WIP=1), the instruction will be rejected without any effect on the current cycle.
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Figure 8.94 FRQDTR Sequence In QPI Mode (EDh [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
...
SCK
Mode 0
IO0
IO1
IO2
IO3
Instruction
= EDh
6 Dummy Cycles
3-byte Address
tV
Data Data
Out Out
4
0
20 16 12 8 4 0 4 0
4 0 4 0 ...
5
1
21 17 13 9 5 1 5 1
5 1 5 1 ...
6
2
22 18 14 10 6 2 6 2
6 2 6 2 ...
7
3
23 19 15 11 7 3 7 3
7 3 7 3 ...
Mode Bits
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode
bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.
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Figure 8.95 FRQDTR Sequence In QPI Mode (EDh [EXTADD=1] or EEh, 4-byte address)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
...
SCK
Mode 0
IO0
IO1
IO2
IO3
Instruction
= EDh/EEh
6 Dummy Cycles
4-byte Address
tV
Data
Out
4
0
28 24 20 16 12 8 4 0 4 0
4 0 ...
5
1
29 25 21 17 13 9 5 1 5 1
5 1 ...
6
2
30 26 22 18 14 10 6 2 6 2
6 2 ...
7
3
31 27 23 19 15 11 7 3 7 3
7 3 ...
Mode Bits
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode
bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.
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IS25LP512M
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8.45 SECTOR LOCK/UNLOCK FUNCTIONS
SECTOR UNLOCK OPERATION (SECUNLOCK, 26h or 4SECUNLOCK, 25h)
The Sector Unlock command allows the user to select a specific sector to allow program and erase operations.
This instruction is effective when the blocks are designated as write-protected through the BP0-BP3 bits in the
Status Register and TBS bit in the Function Register. Only one sector can be enabled at any time. To enable a
different sector, a previously enabled sector must be disabled by executing a Sector Lock command.
26h (EXTADD=0) is followed by a 3-byte address (A23-A0) or
26h (EXTADD=1) is followed by a 4-byte address (A31-A0) or
25h is followed by a 4-byte address (A31-A0)
The instruction code is followed by a 24-bit or 32-bit address specifying the target sector as above, but A0 through
A11 are not decoded. The remaining sectors within the same block remain as read-only.
Figure 8.96 Sector Unlock Sequence In SPI Mode (26h [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
...
28
29
30
31
1
0
SCK
Mode 0
3-byte Address
SI
Instruction = 26h
23
22
21
...
3
2
High Impedance
SO
Figure 8.97 Sector Unlock Sequence In SPI Mode (26h [EXTADD=1] or 25h, 4-byte address)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
...
36
37
38
39
1
0
SCK
Mode 0
4-byte Address
SI
SO
Instruction = 26h/25h
31
30
29
...
3
2
High Impedance
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IS25LP512M
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Figure 8.98 Sector Unlock Sequence In QPI Mode (26h [EXTADD=0], 3-byte address)
CE#
Mode 3 0
1
2
3
4
6
7
7:4
3:0
5
SCK
Mode 0
Instruction
IO[3:0]
3-byte Address
23:20 19:16 15:12 11:8
26h
Figure 8.99 Sector Unlock Sequence In QPI Mode (26h [EXTADD=1] or 25h, 4-byte address)
CE#
Mode 3 0
1
2
3
4
5
6
7
8
9
7:4
3:0
SCK
Mode 0
IO[3:0]
4-byte Address
26h/25h
31:28 27:24 23:20 19:16 15:12 11:8
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IS25LP512M
IS25WP512M
SECTOR LOCK OPERATION (SECLOCK, 24h)
The Sector Lock command relocks a sector that was previously unlocked by the Sector Unlock command. The
instruction code does not require an address to be specified, as only one sector can be enabled at a time. The
remaining sectors within the same block remain in read-only mode.
Figure 8.100 Sector Lock Sequence In SPI mode
CE#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Instruction = 24h
SI
High Impedance
SO
Figure 8.101 Sector Lock Sequence In QPI mode
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
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141
IS25LP512M
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8.46 READ BANK ADDRESS REGISTER OPERATION (RDBR: 16h/C8h)
The Read Bank Address Register (RDBR) instruction allows the Bank Address Register contents to be read. RDBR
is used to read only a volatile Bank Address Register.
The instruction code is first shifted in. Then the 8-bit Bank Register is shifted out. It is possible to read the Bank
Address Register continuously by providing multiples of eight bits.
Data is shifted in from SI and data is shifted out from SO in SPI sequence whereas data in and out is via four pins
(IO0-IO3) in QPI sequence.
Figure 8.102 Read Bank Address Register Sequence In SPI Mode
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Mode 0
SI
Instruction = 16h/C8h
tV
SO
Data Out
7
6
5
4
3
2
1
Figure 8.103 Read Bank Address Register Sequence In QPI Mode
CE#
Mode 3 0
1
2
3
SCK
Mode 0
tV
IO[3:0]
16h/C8h
7:4
3:0
Data Out
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0
IS25LP512M
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8.47 WRITE BANK ADDRESS REGISTER OPERATION (WRBRNV: 18h, WRBRV: 17h/C5h)
The Write Bank Address Register (WRBRNV and WRBRV) instruction is used to write address bits above A23, into
the Bank Address Register (BAR). WRBRNV is used to write the non-volatile Bank Address Register and WRBRV
is used to write the volatile Bank Address Register. The instruction is also used to write the Extended Address
Control bit (EXTADD) that is also in BAR [7]. BAR provides the high order addresses needed by devices having
more than 128Mbits (16Mbytes), when using 3-byte address commands without extended addressing enabled
(BAR [7] EXTADD = 0).
To write non-volatile Bank Address Register, a standard Write Enable (06h) instruction must previously have been
executed for the device to accept WRBRNV(18h) instruction (Status Register bit WEL must equal “1”).
To write volatile Bank Address Register, C5h or 17h command can be used.
When using C5h instruction, a standard Write Enable (06h) instruction must previously have been executed for the
device to accept C5h instruction (Status Register bit WEL must equal “1”).
But 17h instruction does not require a standard Write Enable (06h) operation. (Status Register bit WEL remains
“0”).
The WRBRNV/WRBRV instructions are followed by the data byte. The Bank Address Register is one data byte in
length. The Write In Progress (WIP) bit is “1” during WRBRNV/WRBRV operation, and is “0” when it is completed.
Any bank address bit reserved for the future should always be written as “0”. Data is shifted in from SI and in SPI
whereas data is shifted in via four pins (IO0-IO3) in QPI.
Bit 7 (EXTADD) of volatile Bank Address Register is also writable with EN4B (B7h)/EX4B (29h) instruction.
But B7h/29h instruction does not require a standard Write Enable (06h) (Status Register bit WEL remains 0).
Note: When WRBRNV is executed, the volatile Bank Address Register is set as well as the non-volatile Bank Address
Register.
Figure 8.104 Write Bank Address Register Sequence In SPI Mode
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2
1
0
SCK
Mode 0
Data In
SI
SO
Instruction = 18h or 17h/C5h
7
6
5
4
3
High Impedence
Figure 8.105 Write Bank Address Register Sequence In QPI Mode
CE#
Mode 3 0
1
2
3
7:4
3:0
SCK
Mode 0
IO[3:0]
18h or
17h/C5h
Data In
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8.48 ENTER 4-BYTE ADDRESS MODE OPERATION (EN4B, B7h)
The Enter 4-byte Address Mode instruction allows 32bit address (A31-A0) to be used to access the memory array
beyond 128Mb. To execute EN4B operation, the host drives CE# low, sends the instruction code and then drives
CE# high. The Exit 4-byte Address Mode instruction can be used to exit the 4-byte address mode.
A Write Enable (WREN, 06h) command is not required prior to EN4B (B7h) command.
Note: The EN4B instruction will set the Bit 7 (EXTADD) of the volatile Bank Address Register to “1”, but will not change
the non-volatile Bank Address Register.
Figure 8.106 Enter 4-byte Address Mode Sequence In SPI Mode
CE#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Instruction = B7h
SI
High Impedance
SO
Figure 8.107 Enter 4-byte Address Mode Sequence In QPI Mode
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
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B7h
144
IS25LP512M
IS25WP512M
8.49 EXIT 4-BYTE ADDRESS MODE OPERATION (EX4B, 29h)
In order to be backward compatible, the Exit 4-byte Address Mode instruction allows 24bit address (A23-A0) to be
used to access the memory array up to 128Mb. The Bank Address Register must be used to access the memory
array beyond 128Mb. To execute EX4B operation, the host drives CE# low, sends the instruction code and then
drives CE# high.
A Write Enable (WREN, 06h) command is not required prior to EX4B (29h) command.
Note: The EX4B instruction will reset the Bit 7 (EXTADD) of the volatile Bank Address Register to “0” ”, but will not
change the non-volatile Bank Address Register.
Figure 8.108 Exit 4-byte Address Mode Sequence In SPI Mode
CE#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Instruction = 29h
SI
High Impedance
SO
Figure 8.109 Exit 4-byte Address Mode Sequence In QPI Mode
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
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29h
145
IS25LP512M
IS25WP512M
8.50 READ DYB OPERATION (RDDYB, FAh or 4RDDYB, E0h)
FAh (EXTADD=0) is followed by a 3-byte address (A23-A0) or
FAh (EXTADD=1) is followed by a 4-byte address (A31-A0) or
E0h is followed by a 4-byte address (A31-A0)
The instruction is used to read Dynamic Protection Bit (DYB) status of the given sector/block. The instruction code
is entered first, followed by the 24-bit or 32-bit address selecting location zero within the desired sector/block as
above. Then the 8-bit DYB access register contents are shifted out. Each bit (SPI) is shifted out at the SCK
frequency by the falling edge of the SCK signal. It is possible to read the same DYB access register continuously
by providing multiples of eight bits. The address of the DYB register does not increment so this is not a means to
read the entire DYB array. Each location must be read with a separate Read DYB instruction.
Note: Data must be either 00h (protected) or FFh (unprotected).
Figure 8.110 Read DYB Sequence In SPI Mode (FAh [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
...
7
8
9
...
31
32
33
34
35
36
37
38
39
SCK
Mode 0
SI
Instruction = FAh
3-byte Address
tV
SO
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7
6
5
4
3
2
1
146
0
IS25LP512M
IS25WP512M
Figure 8.111 Read DYB Sequence In SPI Mode(FAh [EXTADD=1] or E0h, 4-byte address)
CE #
Mode 3 0
1
...
7
8
9
...
39
40
41
42
43
44
45
46
47
SCK
Mode 0
SI
Instruction = FAh/E0h
4-byte Address
tV
SO
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7
6
5
4
3
2
1
147
0
IS25LP512M
IS25WP512M
8.51 WRITE DYB OPERATION (WRDYB, FBh or 4WRDYB, E1h)
Before the WRDYB/4WRDYB command can be accepted by the device, a standard Write Enable (06h) instruction
must previously have been executed for the device to accept Write DYB instruction (Status Register bit WEL must
equal 1).
FBh (EXTADD=0) is followed by a 3-byte address (A23-A0) or
FBh (EXTADD=1) is followed by a 4-byte address (A31-A0) or
E1h is followed by a 4-byte address (A31-A0)
The WRDYB/4WRDYB command is entered by driving CE# low, followed by the instruction code, the 24-bit or 32bit address selecting location zero within the desired sector/block as above, then the data byte. The DYB Access
Register is one data byte in length.
CE# must be driven high after the eighth bit of data has been latched in. As soon as CE# is driven high, the
WRDYB/4WRDYB operation is initiated.
Note: Data must be either 00h (protected) or FFh (unprotected).
Figure 8.112 Write DYB Sequence In SPI Mode (FBh [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
...
7
8
9
...
31
32
33
34
35
36
37
38
39
2
1
0
SCK
Mode 0
Data In
SI
SO
Instruction = FBh
3-byte Address
7
6
5
4
3
High Impedence
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IS25LP512M
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Figure 8.113 Write DYB Sequence In SPI Mode (FBh [EXTADD=1] or E1h, 4-byte address)
CE #
Mode 3 0
1
...
7
8
9
39
...
40
41
42
43
44
45
46
47
2
1
0
SCK
Mode 0
Data In
SI
Instruction = FBh/E1h
4-byte Address
7
6
5
4
3
High Impedence
SO
Figure 8.114 Write DYB Sequence In QPI Mode (FBh [EXTADD=0], 3-byte address)
CE#
Mode 3 0
1
2
3
4
5
6
7
8
9
SCK
Mode 0
3-byte Address
FBh
IO[3:0]
Data In
Figure 8.115 Write DYB Sequence In QPI Mode (FBh [EXTADD=1] or E1h, 4-byte address)
CE#
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
SCK
Mode 0
IO[3:0]
FBh/E1h
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4-byte Address
Data In
149
IS25LP512M
IS25WP512M
8.52 READ PPB OPERATION (RDPPB, FCh or 4RDPPB, E2h)
FCh (EXTADD=0) is followed by a 3-byte address (A23-A0) or
FCh (EXTADD=1) is followed by a 4-byte address (A31-A0) or
E2h is followed by a 4-byte address (A31-A0)
The instruction code is shifted into SI by the rising edges of the SCK signal, followed by the 24-bit or 32-bit address
selecting location zero within the desired sector/block as above. Then the 8-bit PPB Access Register contents are
shifted out on SO. The RDPPB/4RDPPB is supporting only SPI, not supporting QPI.
It is possible to read the same PPB Access Register continuously by providing multiples of eight bits. The address
of the PPB Access Register does not increment so this is not a means to read the entire PPB array. Each location
must be read with a separate Read PPB command.
Note: Data must be either 00h (protected) or FFh (unprotected).
Figure 8.116 Read PPB Sequence (FCh [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
...
7
8
9
...
31
32
33
34
35
36
37
38
39
SCK
Mode 0
SI
Instruction = FCh
3-byte Address
tV
SO
7
6
5
2
3
4
1
0
Figure 8.117 Read PPB Sequence (FCh [EXTADD=1] or E2h, 4-byte address)
CE #
Mode 3 0
1
...
7
8
9
...
39
40
41
42
43
44
45
46
47
SCK
Mode 0
SI
Instruction = FCh/E2h
4-byte Address
tV
SO
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7
6
5
4
3
2
1
150
0
IS25LP512M
IS25WP512M
8.53 PROGRAM PPB OPERATION (PGPPB, FDh or 4PGPPB, E3h)
Before the Program PPB (PGPPB/4PGPPB) command is sent, a Write Enable (WREN) command must be issued.
After the WREN command has been decoded, the device will set the Write Enable Latch (WEL) in the Status
Register.
FDh (EXTADD=0) is followed by a 3-byte address (A23-A0) or
FDh (EXTADD=1) is followed by a 4-byte address (A31-A0) or
E3h is followed by a 4-byte address (A31-A0)
The PGPPB/4PGPPB command is entered by driving CE# low, followed by the instruction code, followed by the
24-bit or 32-bit address selecting location zero within the desired sector/block as above.
The PGPPB/4PGPPB command affects the WIP bit in the same manner as any other programming operation. CE#
must be driven high after the last bit of address has been latched in. As soon as CE# is driven high, the
PGPPB/4PGPPB operation is initiated. While the PGPPB/4PGPPB operation is in progress, the Status Register
may be read to check the value of the Write In Progress (WIP) bit. The WIP bit is “1” during the PGPPB/4PGPPB
operation, and is “0” when it is completed. When the PGPPB/4PGPPB operation is completed, the WEL is set to
“0”.
Note: Data must be either 00h (protected) or FFh (unprotected).
Figure 8.118 Program PPB Sequence In SPI Mode (FDh [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
...
7
8
9
...
31
SCK
Mode 0
SI
Instruction = FDh
3-byte Address
High Impedence
SO
Figure 8.119 Program PPB Sequence In SPI Mode (FDh [EXTADD=1] or E3h, 4-byte address)
CE #
Mode 3 0
1
...
7
8
9
...
39
SCK
Mode 0
SI
Instruction = FDh/E3h
SO
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Rev.A5
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4-byte Address
High Impedence
151
IS25LP512M
IS25WP512M
Figure 8.120 Program PPB Sequence In QPI Mode (FDh [EXTADD=0], 3-byte address)
CE#
Mode 3 0
1
2
3
4
5
6
7
SCK
Mode 0
3-byte Address
FDh
IO[3:0]
Figure 8.121 Program PPB Sequence In QPI Mode (FDh [EXTADD=1] or E3h, 4-byte address)
CE#
Mode 3 0
1
2
3
4
5
6
7
8
9
SCK
Mode 0
IO[3:0]
FDh/E3h
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4-byte Address
152
IS25LP512M
IS25WP512M
8.54 ERASE PPB OPERATION (ERPPB, E4h)
The Erase PPB (ERPPB) command sets all PPB bits to “1”. Before the ERPPB command can be accepted by the
device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable
Latch (WEL) in the Status Register to enable any write operations.
The instruction code is shifted in by the rising edges of the SCK signal. CE# must be driven high after the eighth
bit of the instruction byte has been latched in. This will initiate the beginning of internal erase cycle, which involves
the pre-programming and erase of the entire PPB memory array. Without CE# being driven high after the eighth
bit of the instruction, the PPB erase operation will not be executed.
With the internal erase cycle in progress, the user can read the value of the Write In Progress (WIP) bit to check if
the operation has been completed. The WIP bit will indicate “1” when the erase cycle is in progress and “0” when
the erase cycle has been completed. When the ERPPB operation is completed, the WEL is set to “0”. Erase
suspend is not allowed during PPB Erase.
Figure 8.122 Erase PPB Sequence In SPI Mode
CE#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Instruction = E4h
SI
High Impedance
SO
Figure 8.123 Erase PPB Sequence In QPI Mode
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
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E4h
153
IS25LP512M
IS25WP512M
8.55 READ ASP OPERATION (RDASP, 2Bh)
The RDASP instruction code is shifted in by the rising edge of the SCK signal. Then the 16-bit ASP register contents
is shifted out, least significant byte first, most significant bit of each byte first. Each bit is shifted out at the SCK
frequency by the falling edge of the SCK signal. It is possible to read the ASP register continuously by providing
multiples of 16 bits.
Figure 8.124 Read ASP Sequence In SPI Mode
CE #
Mode 3 0
1
2
3
4
5
6
8
7
9
...
15
16
17
...
23
SCK
Mode 0
SI
Instruction = 2Bh
1st byte Data Out
tV
SO
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Rev.A5
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7
6
...
2nd byte Data Out
0
15
14
...
154
8
IS25LP512M
IS25WP512M
8.56 PROGRAM ASP OPERATION (PGASP, 2Fh)
Before the Program ASP (PGASP) command can be accepted by the device, a Write Enable (WREN) command
must be issued. After the WREN command has been decoded, the device will set the Write Enable Latch (WEL) in
the Status Register to enable any write operations.
The PGASP command is entered by driving CE# low, followed by the instruction code and two data bytes, least
significant byte first, most significant bit of each byte first. The ASP Register is two data bytes in length. The PGASP
command affects the Write In Progress (WIP) bit in the same manner as any other programming operation.
CE# input must be driven high after the sixteenth bit of data has been latched in. If not, the PGASP command is
not executed. As soon as CE# is driven high, the PGASP operation is initiated. While the PGASP operation is in
progress, the Status Register may be read to check the value of WIP bit. The WIP bit is “1” during the PGASP
operation, and is “0” when it is completed. When the PGASP operation is completed, the WEL is set to “0”.
Figure 8.125 Program ASP Sequence In SPI Mode
CE #
Mode 3 0
1
...
7
8
9
...
13
14
15
16
17
...
21
22
23
9
8
SCK
Mode 0
SI
1st byte Data In
Instruction = 2Fh
7
6
...
2
2nd byte Data In
1
0
15
3
4
5
14
...
10
High Impedence
SO
Figure 8.126 Program ASP Sequence In QPI Mode
CE#
Mode 3 0
1
2
SCK
Mode 0
IO[3:0]
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2Fh
1st byte
Data In
2nd byte
Data In
155
IS25LP512M
IS25WP512M
8.57 READ PPB LOCK BIT OPERATION (RDPLB, A7h)
The Read PPB Lock Bit (RDPLB) command allows the PPB Lock Register contents to be read. It is possible to
read the PPB Lock Register continuously by providing multiples of eight bits. The PPB Lock Register contents may
only be read when the device is in standby state with no other operation in progress. It is recommended to check
the Write In Progress (WIP) bit before issuing a new command to the device.
RDPLB operation is valid only at SPI mode only.
Figure 8.127 Read PPB Lock Bit Sequence In SPI Mode
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Mode 0
SI
Instruction = A7h
tV
SO
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Rev.A5
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Data Out
7
6
5
4
3
2
1
156
0
IS25LP512M
IS25WP512M
8.58 WRITE PPB LOCK BIT OPERATION (WRPLB, A6h)
The Write PPB Lock Bit (WRPLB) command clears the PPB Lock (PPBLK) bit to zero. Before the WRPLB command
can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device,
which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The WRPLB command is entered by driving CE# low, followed by the instruction code. CE# must be driven high
after the eighth bit of instruction has been latched in. If not, the WRPLB command is not executed. As soon as CE#
is driven high, the WRPLB operation is initiated. While the WRPLB operation is in progress, the Status Register
may still be read to check the value of the Write In Progress (WIP) bit. The WIP bit is “1” during the WRPLB
operation, and is “0” when it is completed. When the WRPLB operation is completed, the WEL is set to “0”.
Figure 8.128 Write PPB Lock Bit Sequence In SPI Mode
CE#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Instruction = A6h
SI
High Impedance
SO
Figure 8.129 Write PPB Lock Bit Sequence In QPI Mode
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
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157
IS25LP512M
IS25WP512M
8.59 SET FREEZE BIT OPERATION (SFRZ, 91h)
The Set FREEZE Bit (SFRZ) command sets FREEZE (PPB Lock Register bit7) to one. Please refer to the section
6.6.3 PPB Lock Register for more detail. Before the SFRZ command can be accepted by the device, a Write Enable
(WREN) command must be issued and decoded by the device, which sets the Write Enable Latch (WEL) in the
Status Register to enable any write operations.
The SFRZ command is entered by driving CE# low, followed by the instruction code. CE# must be driven high after
the eighth bit of instruction has been latched in. If not, the SFRZ command is not executed. As soon as CE# is
driven high, the SFRZ operation is initiated. While the SFRZ operation is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The WIP bit is “1” during the SFRZ operation, and is
“0” when it is completed. When the SFRZ operation is completed, the WEL is set to “0”.
Figure 8.130 Set FREEZE Bit Sequence In SPI Mode
CE#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Instruction = 91h
SI
High Impedance
SO
Figure 8.131 Set FREEZE Bit Sequence In QPI Mode
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
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IS25LP512M
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8.60 READ PASSWORD OPERATION (RDPWD, E7h)
The correct password value may be read only after it is programmed and before the Password Mode has been
selected by programming the Password Protection Mode bit to “0” in the ASP Register (ASP[2]). After the Password
Protection Mode is selected the RDPWD command is ignored.
The RDPWD command is shifted in. Then the 64-bit Password is shifted out, least significant byte first, most
significant bit of each byte first. Each bit is shifted out at the SCK frequency by the falling edge of the SCK signal.
It is possible to read the Password continuously by providing multiples of 64bits.
RDPWD operation is valid only at SPI mode only.
Figure 8.132 Read password Sequence In SPI Mode
CE #
Mode 3 0
1
...
7
8
9
15
...
16
17
...
23
...
64
65
71
...
SCK
Mode 0
SI
Instruction = E7h
1st byte Data Out
tV
SO
7
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Rev.A5
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6
...
...
2nd byte Data Out
0
15
14
...
8
...
8th byte Data Out
63
62
159
...
56
IS25LP512M
IS25WP512M
8.61 PROGRAM PASSWORD OPERATION (PGPWD, E8h)
Before the Program Password (PGPWD) command can be accepted by the device, a Write Enable (WREN)
command must be issued and decoded by the device which sets the Write Enable Latch (WEL) to enable the
PGPWD operation. The password can only be programmed before the Password Mode is selected by programming
the Password Protection Mode bit to “0” in the ASP Register (ASP[2]). After the Password Protection Mode is
selected the PGPWD command is ignored.
The PGPWD command is entered by driving CE# low, followed by the instruction code and the password data
bytes, least significant byte first, most significant bit of each byte first. The password is 64bits in length.
CE# must be driven high after the 64th bit of data has been latched. If not, the PGPWD command is not executed.
As soon as CE# is driven high, the PGPWD operation is initiated. While the PGPWD operation is in progress, the
Status Register may be read to check the value of the Write In Progress (WIP) bit. The WIP bit is “1” during the
PGPWD operation, and is “0” when it is completed. When the PGPWD operation is completed, the Write Enable
Latch (WEL) is set to “0”.
Figure 8.133 Program Password Sequence In SPI Mode
CE #
Mode 3 0
1
...
7
8
9
15
...
16
17
...
23
...
64
65
...
71
SCK
Mode 0
1st byte Data In
SI
Instruction = E8h
7
...
6
...
2nd byte Data In
...
14
15
0
...
8
8th byte Data In
63
62
High Impedence
SO
Figure 8.134 Program Password Sequence In QPI Mode
CE#
Mode 3 0
1
2
3
5
...
2nd byte
Data In
...
4
16
17
SCK
Mode 0
IO[3:0]
E8h
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Data In
8th byte
Data In
160
...
56
IS25LP512M
IS25WP512M
8.62 UNLOCK PASSWORD OPERATION (UNPWD, E9h)
The UNPWD command is entered by driving CE# low, followed by the instruction code and the password data
bytes, least significant byte first, most significant bit of each byte first. The password is 64bits in length.
CE# must be driven high after the 64th bit of data has been latched. If not, the UNPWD command is not executed.
As soon as CE# is driven high, the UNPWD operation is initiated. While the UNPWD operation is in progress, the
Status Register may be read to check the value of the Write In Progress (WIP) bit. The WIP bit is “1” during the
UNPWD operation, and is “0” when it is completed.
If the UNPWD command supplied password does not match the hidden password in the Password Register, the
UNPWD command is ignored. This returns the device to standby state, ready for a new command such as a retry
of the UNPWD command. If the password does match, the PPB Lock bit is set to “1”.
Figure 8.135 Unlock Password Sequence In SPI Mode
CE #
Mode 3 0
1
...
7
8
9
15
...
16
17
...
23
...
64
65
...
71
SCK
Mode 0
1st byte Data In
SI
Instruction = E9h
7
...
6
...
2nd byte Data In
...
14
15
0
...
8
8th byte Data In
63
62
High Impedence
SO
Figure 8.136 Unlock Password Sequence In QPI Mode
CE#
Mode 3 0
1
2
3
5
...
2nd byte
Data In
...
4
16
17
SCK
Mode 0
IO[3:0]
E9h
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1st byte
Data In
8th byte
Data In
161
...
56
IS25LP512M
IS25WP512M
8.63 GANG SECTOR/BLOCK LOCK OPERATION (GBLK, 7Eh)
The Gang Sector/Block Lock (GBLK) instruction provides a quick method to set all DYB (Dynamic Protection Bit)
bits to “0” at once.
Before the GBLK (7Eh) command can be accepted by the device, a Write Enable (WREN) command must be
issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any
write operations.
The sequence of issuing GBLK instruction is: drive CE# low send GBLK instruction code drive CE# high.
The instruction code will be shifted into the device on the rising edge of SCK.
The GBLK command is accepted in both SPI and QPI mode. The CE# must go high exactly at the byte boundary,
otherwise, the instruction will be ignored. While the GBLK operation is in progress, the Status Register may be read
to check the value of the Write In Progress (WIP) bit. The WIP bit is “1” during the GBLK operation, and is “0” when
it is completed.
Figure 8.137 Gang Sector/Block Lock Sequence In SPI Mode
CE#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Instruction = 7Eh
SI
High Impedance
SO
Figure 8.138 Gang Sector/Block Lock Sequence In QPI Mode
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
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162
IS25LP512M
IS25WP512M
8.64 GANG SECTOR/BLOCK UNLOCK OPERATION (GBUN, 98h)
The Gang Sector/Block Unlock (GBUN) instruction provides a quick method to clear all DYB (Dynamic Protection
Bit) bits to “1” at once.
Before the GBUN (98h) command can be accepted by the device, a Write Enable (WREN) command must be
issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any
write operations.
The sequence of issuing GBUN instruction is: drive CE# low send GBUN instruction code drive CE# high.
The instruction code will be shifted into the device on the rising edge of SCK.
The GBUN command is accepted in both SPI and QPI mode. The CE# must go high exactly at the byte boundary,
otherwise, the instruction will be ignored and not be executed. While the GBUN operation is in progress, the Status
Register may be read to check the value of the Write In Progress (WIP) bit. The WIP bit is “1” during the GBUN
operation, and is “0” when it is completed.
Figure 8.139 Gang Sector/Block Unlock Sequence In SPI Mode
CE#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Instruction = 98h
SI
High Impedance
SO
Figure 8.140 Gang Sector/Block Unlock Sequence In QPI Mode
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
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163
IS25LP512M
IS25WP512M
8.65 DATA LEARNING PATTERN (DLP)
The Data Learning Pattern is a preamble, and it can help host controller to determine the phase shift from SCK to
data edges so that controller can capture data at the center of the data eye at high frequency DTR operation.
DLP can be enabled or disabled by setting the bit EB4 of Extended Read register (DLPEN bit).
When enabled, the device drives all IO bus during last 4 dummy cycles immediately before data is output in DTR
operation. (No DLP operation in STR operation). The host must be sure to stop driving the IO bus at least 1 cycle
prior to the time that the memory starts outputting the DLP during dummy cycles. That is why, when using DDR IO
commands with DLP enabled, 5 or more dummy cycles must be selected.
If there are mode bits for AX read operation, still more than 5 clock cycles are required for DLP operation between
last mode bit and first read data.
DLP operation is valid in DTR operation with valid dummy cycles in SPI mode and QPI mode with below command;
FRDTR (Fast Read DTR) command in SPI and QPI mode.
FRDDTR (Fast Read Dual IO DTR) command in SPI mode only
FRQDTR (Fast Read Quad IO DTR) command in SPI and QPI mode
Data Learning Pattern is programmable, and fixed length of 8-bit in DTR operation.
For example, DLP 34h is programmed, then (0011 0100) data will start output from all IOs before data is output
during 4 clock cycles. All IOs will output 0 at the first clock edge, subsequently, all IOs will output 0, the 3 rd will
output 1, etc.
The Data Learning Pattern (DLP) resides in an 8-bit Non-Volatile Data Learning Register (NVDLR) as well as an
8-bit Volatile Data Learning Register (VDLR). NVDLR can be programmed with Program NVDLR (PNVDLR 43h)
command, and VDLR can be written by Write VDLR (WRVDLR 4Ah) command. Also DLP register value can be
read out by Data Learning Pattern Read (RDDLP) command. All 3 commands (PNVDLR, WRVDLR, RDDLP) are
valid in SPI mode and QPI mode.
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Figure 8.141 FRDTR Sequence with DLP In SPI Mode (0Dh [EXTADD=0], 3-byte address)
CE#
Mode3 0
1
2
3
4
5
6
7
8
9
10
...
19
20
21
SCK
Mode0
3- byte Address
SI
Instruction= 0Dh
23 22 21 20 19 18 17
...
0
High Impedance
SO
CE#
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
...
SCK
8 Dummy Cycles
DLP Cycles
SI
tV
tV
Data Out1
SO
Data Out 2
Data Out ...
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 ...
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Figure 8.142 FRDTR Sequence with DLP In QPI Mode (0Dh [EXTADD=0], 3-byte address)
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
11
12
...
SCK
Mode 0
6 Dummy Cycles
Instruction
= 0Dh
IO0
IO1
IO2
IO3
DLP Cycles
3-byte Address
tV
Data Data
tV Out Out
7 6 5 4 3 2 1 0 4 0 4 0 ...
4
0
20 16 12 8 4 0
5
1
21 17 13 9 5 1
7 6 5 4 3 2 1 0 5 1 5 1 ...
6
2
22 18 14 10 6 2
7 6 5 4 3 2 1 0 6 2 6 2 ...
7
3
23 19 15 11 7 3
7 6 5 4 3 2 1 0 7 3 7 3 ...
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8.66 PROGRAM NVDLR OPERATION (PNVDLR, 43h)
Before the Program NVDLR (PNVDLR) command can be accepted by the device, a Write Enable (WREN)
command must be issued and decoded by the device. After the Write Enable (WREN) command has been decoded
successfully, the device will set the Write Enable Latch (WEL) to enable the PNVDLR operation.
The PNVDLR command (43h) is entered by shifting the instruction and data byte on SI.
CE# must be driven to the logic high state after the eighth (8 th) bit of data has been latched. If not, the PNVDLR
command is not executed. As soon as CE# is driven to the logic high state, the self-timed PNVDLR operation is
initiated. While the PNVDLR operation is in progress, the Status Register may be read to check the value of the
Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the PNVDLR cycle, and is 0 when it is
completed. The PNVDLR operation can report a program error in the P_ERR bit of the Extended Read Register.
When the PNVDLR operation is completed, the Write Enable Latch (WEL) is set to 0 .
Figure 8.143 PNVDLR Sequence In SPI Mode
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2
1
0
SCK
Mode 0
SI
SO
Data In
Instruction = 43h
7
6
5
1
2
3
7:4
3:0
4
3
High Impedence
Figure 8.144 PNVDLR Sequence In QPI Mode
CE#
Mode 3 0
SCK
Mode 0
IO[3:0]
43h
Data In
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IS25LP512M
IS25WP512M
8.67 WRITE VDLR OPERATION (WRVDLR, 4Ah)
Before the Write VDLR (WRVDLR) command can be accepted by the device, a Write Enable (WREN) command
must be issued and decoded by the device. After the Write Enable (WREN) command has been decoded
successfully, the device will set the Write Enable Latch (WEL) to enable the WRVDLR operation.
The WRVDLR command (4Ah) is entered by shifting the instruction and data byte on SI.
CE# must be driven to the logic high state after the eighth (8th) bit of data has been latched. If not, the WRVDLR
command is not executed. As soon as CE# is driven to the logic high state, the WRVDLR operation is initiated
with no delays.
Figure 8.145 WRVDLR Sequence In SPI Mode
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2
1
0
SCK
Mode 0
SI
SO
Data In
Instruction = 4Ah
7
6
5
4
3
High Impedence
Figure 8.146 WRVDLR Sequence In QPI Mode
CE#
Mode 3 0
1
2
3
7:4
3:0
SCK
Mode 0
IO[3:0]
4Ah
Data In
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IS25LP512M
IS25WP512M
8.68 READ DLP OPERATION (RDDLP, 41h)
The instruction is shifted on SI, then the 8-bit DLP from VDLR is shifted out on SO. It is possible to read the DLP
continuously by providing multiples of eight clock cycles.
Figure 8.147 RDDLP Sequence In SPI Mode
CE #
Mode 3 0
1
...
7
8
9
15
...
16
17
...
23
...
64
65
71
...
SCK
Mode 0
SI
Instruction = 41h
tV
SO
Register Read
7
...
6
Repeat Register Read
7
0
6
...
0
...
...
Repeat Register Read
7
6
Figure 8.148 RDDLP Sequence In QPI Mode
CE#
Mode 3 0
1
2
3
4
5
...
16
17
SCK
Mode 0
tV
IO[3:0]
41h
7:0
7:0
Register
Read
Repeat
Register
Read
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...
7:0
Repeat
Register
Read
169
...
0
IS25LP512M
IS25WP512M
9. ELECTRICAL CHARACTERISTICS
9.1 ABSOLUTE MAXIMUM RATINGS (1)
Storage Temperature
-65°C to +150°C
Surface Mount Lead Soldering Temperature
Standard Package
240°C 3 Seconds
Lead-free Package
260°C 3 Seconds
Input Voltage with Respect to Ground on All Pins
-0.5V to VCC + 0.5V
All Output Voltage with Respect to Ground
-0.5V to VCC + 0.5V
VCC
IS25LP
-0.5V to +6.0V
IS25WP
-0.5V to +2.5V
Note:
1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
9.2 OPERATING RANGE
Ambient Operating Temperature
VCC Power Supply
Extended Grade E
-40°C to 105°C
Automotive Grade A3
-40°C to 125°C
IS25LP
2.3V (VMIN) – 3.6V (VMAX); 3.0V (Typ)
IS25WP
1.7V (VMIN) –1.95V (VMAX); 1.8V (Typ)
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IS25LP512M
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9.3 DC CHARACTERISTICS
(Under operating range)
Symbol
ICC1
Typ(2)
Max
NORD
13
16
FRD Single at 133MHz
16
20
FRD Dual at 133MHz
18
22
FRD Quad at 133MHz
22
27
FRD Single at 104MHz
15
19
FRD Dual at 104MHz
17
21
FRD Quad at 104MHz
20
24
FRD Single DTR at 66MHz
15
19
FRD Dual DTR at 66MHz
17
21
21
26
Parameter
Condition
VCC Active Read current(3)
Min
FRD Quad DTR at 66MHz
85°C
ICC2
VCC Program Current
CE# = VCC
105°C
30
35
35
85°C
ICC4
ICC5
VCC WRSR Current
CE# = VCC
VCC Erase Current
(SER/4SER/BER32/4BER32/
BER64/4BER64)
VCC Erase Current (CE)
CE# = VCC
CE# = VCC
IS25LP
ISB1
VCC Standby
Current CMOS
IS25WP
Deep power down
current
60
80
85°C
35
105°C
30
35
85°C
80
105°C
IS25WP
60
80
125°C
80
85°C
90 (6)
140 (6)
21
125°C
260
85°C
90(6)
140 (6)
21
125°C
260
85°C
35 (6)
125°C
90
85°C
35 (6)
Input Leakage Current
uA
µA
50 (6)
1
125°C
ILI
µA
50 (6)
17
105°C
mA
35
125°C
105°C
CE# = VCC,
VIN = GND or VCC (4)
80
125°C
105°C
IS25LP
ISB2
80
105°C
105°C
CE# = VCC,
VIN = GND or VCC (4)
mA
35
125°C
ICC3
Units
90
VIN = 0V to VCC
±25)
µA
VIN = 0V to VCC
(5)
µA
ILO
Output Leakage Current
VIL(1)
Input Low Voltage
VIH(1)
Input High Voltage
VOL
Output Low Voltage
IOL = 100 µA
VOH
Output High Voltage
IOH = -100 µA
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±2
-0.5
0.3VCC
V
0.7VCC
VCC + 0.3
V
0.2
V
VCC - 0.2
V
171
IS25LP512M
IS25WP512M
Notes:
1. Maximum DC voltage on input or I/O pins is VCC + 0.5V. During voltage transitions, input or I/O pins may overshoot
VCC by +2.0V for a period of time not to exceed 20ns. Minimum DC voltage on input or I/O pins is
-0.5V. During voltage transitions, input or I/O pins may undershoot GND by -2.0V for a period of time not to exceed
20ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC
= VCC (Typ), TA=25°C.
3. Outputs are unconnected during reading data so that output switching current is not included.
4. VIN = Vcc for the dedicated RESET# pin (or ball).
5. The Max of ILI and ILO for the additional RESET# pin (or ball) is ±4 µA.
6. These parameters are characterized and are not 100% tested.
9.4 AC MEASUREMENT CONDITIONS
Symbol
Max
Units
Load Capacitance up to 104MHz/52MHz DTR
30
pF
Load Capacitance up to 133MHz/66MHz DTR
10
pF
TR,TF
Input Rise and Fall Times
5
ns
VIN
Input Pulse Voltages
0.2VCC to 0.8VCC
V
VREFI
Input Timing Reference Voltages
0.3VCC to 0.7VCC
V
VREFO
Output Timing Reference Voltages
0.5VCC
V
CL
Parameter
Min
Figure 9.1 Output test load & AC measurement I/O Waveform
0.8VCC
VCC/2
AC
Measurement
Level
IS25LP
IS25WP
Input
1.8k
0.2VCC
OUTPUT PIN
1.2k
10/30pf
9.5 PIN CAPACITANCE
(TA = 25°C, VCC=3V for IS25LP, VCC=1.8V for IS25WP, 1MHz)
Symbol
CIN
CIN/OUT
Parameter
Test Condition
Input Capacitance
(CE#, SCK)
Input/Output
Capacitance
(other pins)
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Units
Min
Max
Min
Max
VIN = 0V
-
12
-
12
pF
VIN/OUT = 0V
-
16
-
24
pF
172
IS25LP512M
IS25WP512M
9.6 AC CHARACTERISTICS
(-40°C to 125°C, 2.3V – 3.6V for 3.0V device & 1.70V– 1.95V for 1.8V device)
Symbol
Parameter
Min
Clock Frequency except for
fast read DTR and read (03h)
fCT
Typ(2)
Max
Units
IS25LP
0
133
MHz
IS25WP
0
112(5).
MHz
0
66
MHz
0
50
MHz
fC
Clock Frequency for fast read DTR:
SPI DTR, Dual DTR, Dual I/O DTR, Quad I/O DTR, and
QPI DTR.
Clock Frequency for read (03h)
tCLCH(1)
SCK Rise Time (peak to peak)
0.1
V/ns
(1)
SCK Fall Time ( peak to peak)
0.1
V/ns
tCHCL
For read (03h)
0.45 x 1/fCmax
For others
0.45 x 1/fCTmax
For read (03h)
0.45 x 1/fCmax
For others
0.45 x 1/fCTmax
tCKH
SCK High Time
tCKL
SCK Low Time
tCEH
CE# High Time
7
ns
tCS
CE# Setup Time
5
ns
tCH
CE# Hold Time
3
ns
tCHSL
CE# Not Active Hold Time
3
ns
tSHCH
CE# Not Active Setup Time
3
ns
tDS
Data In Setup Time
STR
2
ns
DTR
1.5
tDH
Data in Hold Time
IS25LP
Output
Valid
tV
2.7~3.6V,
-40°C to 85°C
2.3~3.6V,
-40°C to 125°C
IS25WP
tOH
Output Hold Time
tDIS(1)
Output Disable Time
1.70~1.95V,
-40°C to 125°C
STR
2
DTR
1.5
ns
ns
@ CL = 10pF
6.0(4).
ns
@ CL = 30pF
@ CL = 10pF
7.5(4).
7.0
ns
ns
@ CL = 30pF
@ CL = 10pF
8.5.
7.5
ns
ns
@ CL = 30pF
9.0
ns
1
ns
8
ns
tWHSL
(3)
Write Protect Setup Time
20
ns
tSHWL
(3)
Write Protect Hold Time
100
ns
tHLCH
HOLD Active Setup Time relative to SCK
2
ns
tCHHH
HOLD Active Hold Time relative to SCK
2
ns
tHHCH
HOLD Not Active Setup Time relative to SCK
2
ns
tCHHL
HOLD Not Active Hold Time relative to SCK
2
tLZ(1)
HOLD to Output Low Z
8
ns
HOLD to Output High Z
8
ns
tHZ
(1)
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Rev.A5
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ns
173
IS25LP512M
IS25WP512M
Symbol
tEC
Typ(2)
Max
Units
Sector Erase Time (4Kbyte)
100
300
ms
Block Erase Time (32Kbyte)
0.14
0.5
s
Block Erase time (64Kbyte)
0.17
1.0
s
Block Erase time (256Kbyte)
0.68
4.0
s
s
Parameter
Min
Chip Erase Time
tPP
Page Program Time
tRES1(1)
Release deep power down
tDP(1)
Deep power down
tW
Write Status Register time
tSUS(1)
tRS(1)
tSRST(1)
Software Reset recovery time
tRESET
(1),
tHWRST(1),
80
270
256byte
0.3
1.0
512byte
0.6
2.0
IS25LP
3
IS25WP
5
ms
µs
3
µs
2
15
ms
Suspend to read ready
100
-
µs
Resume to next suspend
80
RESET# pin low pulse width
-
µs
35
µs
35
µs
100
ns
Hardware Reset recovery time
Notes:
1. These parameters are characterized and not 100% tested.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V CC = VCC
(Typ), TA=25°C.
3. Only applicable as a constraint for a WRITE STATUS REGISTER command when SRWD is set at 1.
4. Values are guaranteed by characterization and not 100% tested in production.
5. RDSR(05h), RDID(ABh), RDJDID(9Fh), RDJDIDQ(AFh, QPI mode only), RDRP(61h), RDFR(48h) QPI mode operation
frequency is105MHz at 105°C, and 104MHz at 125°C.
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IS25LP512M
IS25WP512M
9.7 SERIAL INPUT/OUTPUT TIMING
Figure 9.2 SERIAL INPUT/OUTPUT TIMING (Normal Mode) (1)
tCEH
CE#
tCS
t CHSL
tCH
tCKH
SCK
tDS
SI
tCKL
tDH
VALID IN
VALID IN
tV
HI-Z
SO
tSHCH
tOH
tDIS
HI-Z
VALID OUTPUT
Note1: For SPI Mode 0 (0,0)
Figure 9.3 SERIAL INPUT/OUTPUT TIMING (DTR Mode)
(1)
tCEH
CE#
tCS
t CHSL
tCH
tCKH
SCK
tDS
SI
tCKL
tDH
VALID IN
VALID IN
VALID IN
tV
SO
tSHCH
HI-Z
tV
Output
tOH
Output
tDIS
HI-Z
Note1: For SPI Mode 0 (0,0)
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IS25LP512M
IS25WP512M
Figure 9.4 HOLD TIMING
CE#
tHLCH
tCHHL
tHHCH
SCK
tCHHH
tHZ
tLZ
SO
SI
HOLD#
Figure 9.5 WRITE PROTECT SETUP AND HOLD TIMIMNG DURING WRITE STATUS REGISTER (SRWD=1)
WP#
tWHSL
tSHWL
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2
1
0
SCK
Mode 0
SI
SO
Data In
Instruction = 01h
7
6
5
4
3
High Impedence
Note: WP# must be kept high until the embedded operation finish.
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IS25LP512M
IS25WP512M
9.8 POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must be NOT SELECTED until Vcc reaches at the right level. (Adding a
simple pull-up resistor on CE# is recommended.)
Power up timing
VCC
VCC ( max)
Chip Selection Not Allowed
VCC(min)
tVCE
= Vcc min. to CE# Low
Device is fully
accessible
VWI
Time
Symbol
Parameter
tVCE(1)
Vcc(min) to CE# Low
VWI(1)
Write Inhibit Voltage
Min.
Max
300
us
IS25LP
2.1
IS25WP
1.5
Note: These parameters are characterized and not 100% tested.
Integrated Silicon Solution, Inc.- www.issi.com
Rev.A5
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Unit
177
V
IS25LP512M
IS25WP512M
9.9 PROGRAM/ERASE PERFORMANCE
Parameter
Sector Erase Time (4Kbyte)
Block Erase Time (32Kbyte)
Block Erase Time (64Kbyte)
Block Erase Time (256Kbyte)
Chip Erase Time
256byte
Page Programming Time
512byte
Byte Program
Typ
Max
Unit
100
300
ms
0.14
0.5
s
0.17
1.0
s
0.68
4.0
s
80
270
s
0.3
1.0
ms
0.6
2.0
ms
10
50
µs
Note: These parameters are characterized and not 100% tested.
9.10 RELIABILITY CHARACTERISTICS
Parameter
Min
Max
Unit
Test Method
Endurance
100,000
-
Cycles
JEDEC Standard A117
Data Retention
20
-
Years
JEDEC Standard A117
Latch-Up
-100
+100
mA
JEDEC Standard 78
Note: These parameters are characterized and not 100% tested.
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IS25LP512M
IS25WP512M
10. PACKAGE TYPE INFORMATION
10.1 8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD (WSON) PACKAGE 8X6MM (L)
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IS25LP512M
IS25WP512M
10.2 16-LEAD PLASTIC SMALL OUTLINE PACKAGE (300 MILS BODY WIDTH) (M)
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IS25LP512M
IS25WP512M
10.3 24-BALL THIN PROFILE FINE PITCH BGA 6X8MM 4X6 BALL ARRAY (G)
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IS25LP512M
IS25WP512M
10.4 24-BALL THIN PROFILE FINE PITCH BGA 6X8MM 5X5 BALL ARRAY (H)
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IS25LP512M
IS25WP512M
11. ORDERING INFORMATION – Valid Part Numbers
IS25LP 512M
-
R H L E
TEMPERATURE RANGE
E = Extended (-40°C to +105°C)
A3 = Automotive Grade (-40°C to +125°C)
PACKAGING CONTENT
L = RoHS compliant
PACKAGE Type (1)
L = 8-contact WSON (8x6mm)
M = 16-pin SOIC 300mil
G = 24-ball TFBGA (6x8mm) 4x6 ball array
H = 24-ball TFBGA (6x8mm) 5x5 ball array
Option
J = Standard
R = Dedicated RESET# in 16-pin SOIC, 24-ball BGA
Q = QE bit set to 1
P = Dedicated RESET# + QE bit set to 1
K = Optional 512-byte Page & 256KB Sector
T = Optional 512-byte Page & 256KB Sector with dedicated
RESET# for SOIC/TFBGA
Die Revision
Blank = First Gen.
Density
512M = 512 Mb
BASE PART NUMBER
IS = Integrated Silicon Solution Inc.
25LP = FLASH, 2.30V ~ 3.60V, QPI
25WP = FLASH, 1.70V ~ 1.95V, QPI
Note:
1. No dedicated RESET# for 8x6mm WSON PKG
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IS25LP512M
IS25WP512M
Density,
Voltage
512M,
3V
Frequency (MHz)
STR 133,
DTR 66
Order Part Number
Package
IS25LP512M-JLLE
8-contact WSON 8x6mm
IS25LP512M-JMLE
16-pin SOIC 300mil
IS25LP512M-JGLE
24-ball TFBGA 6x8mm 4x6 ball array (Call Factory)
IS25LP512M-JHLE
24-ball TFBGA 6x8mm 5x5 ball array
IS25LP512M-RMLE
16-pin SOIC 300mil
IS25LP512M-RGLE
24-ball TFBGA 6x8mm 4x6 ball array (Call Factory)
IS25LP512M-RHLE
24-ball TFBGA 6x8mm 5x5 ball array
IS25LP512M-QLLE
8-contact WSON 8x6mm
IS25LP512M-QMLE
16-pin SOIC 300mil
IS25LP512M-QHLE
24-ball TFBGA 6x8mm 5x5 ball array
IS25LP512M-PMLE
16-pin SOIC 300mil
IS25LP512M-PHLE
24-ball TFBGA 6x8mm 5x5 ball array
IS25LP512M-KMLE
16-pin SOIC 300mil
IS25LP512M-KGLE
24-ball TFBGA 6x8mm 4x6 ball array (Call Factory)
IS25LP512M-KHLE
24-ball TFBGA 6x8mm 5x5 ball array
IS25LP512M-TMLE
16-pin SOIC 300mil
IS25LP512M-TGLE
24-ball TFBGA 6x8mm 4x6 ball array (Call Factory)
IS25LP512M-THLE
24-ball TFBGA 6x8mm 5x5 ball array
IS25LP512M-JLLA3
8-contact WSON (8x6mm)
IS25LP512M-JMLA3
16-pin SOIC 300mil
IS25LP512M-JGLA3
24-ball TFBGA 6x8mm 4x6 ball array (Call Factory)
IS25LP512M-JHLA3
24-ball TFBGA 6x8mm 5x5 ball array
IS25LP512M-RMLA3
16-pin SOIC 300mil
IS25LP512M-RGLA3
24-ball TFBGA 6x8mm 4x6 ball array (Call Factory)
IS25LP512M-RHLA3
24-ball TFBGA 6x8mm 5x5 ball array
IS25LP512M-QLLA3
8-contact WSON (8x6mm)
IS25LP512M-QMLA3
16-pin SOIC 300mil
IS25LP512M-QHLA3
24-ball TFBGA 6x8mm 5x5 ball array
IS25LP512M-FMLA3
16-pin SOIC 300mil
IS25LP512M-FHLA3
24-ball TFBGA 6x8mm 5x5 ball array
IS25LP512M-KLLA3
8-contact WSON (8x6mm)
IS25LP512M-KMLA3
16-pin SOIC 300mil
IS25LP512M-KGLA3
24-ball TFBGA 6x8mm 4x6 ball array (Call Factory)
IS25LP512M-KHLA3
24-ball TFBGA 6x8mm 5x5 ball array
IS25LP512M-TMLA3
16-pin SOIC 300mil
IS25LP512M-TGLA3
24-ball TFBGA 6x8mm 4x6 ball array (Call Factory)
IS25LP512M-THLA3
24-ball TFBGA 6x8mm 5x5 ball array
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IS25LP512M
IS25WP512M
Density,
Voltage
512M,
1.8V
Frequency (MHz)
STR 112,
DTR 66
Order Part Number
Package
IS25WP512M-JLLE
8-contact WSON 8x6mm
IS25WP512M-JMLE
16-pin SOIC 300mil
IS25WP512M-JGLE
24-ball TFBGA 6x8mm 4x6 ball array (Call Factory)
IS25WP512M-JHLE
24-ball TFBGA 6x8mm 5x5 ball array
IS25WP512M-RMLE
16-pin SOIC 300mil
IS25WP512M-RGLE
24-ball TFBGA 6x8mm 4x6 ball array (Call Factory)
IS25WP512M-RHLE
24-ball TFBGA 6x8mm 5x5 ball array
IS25WP512M-QLLE
8-contact WSON 8x6mm
IS25WP512M-QMLE
16-pin SOIC 300mil
IS25WP512M-QHLE
24-ball TFBGA 6x8mm 5x5 ball array
IS25WP512M-PMLE
16-pin SOIC 300mil
IS25WP512M-PHLE
24-ball TFBGA 6x8mm 5x5 ball array
IS25WP512M-KLLE
8-contact WSON 8x6mm
IS25WP512M-KMLE
16-pin SOIC 300mil
IS25WP512M-KGLE
24-ball TFBGA 6x8mm 4x6 ball array (Call Factory)
IS25WP512M-KHLE
24-ball TFBGA 6x8mm 5x5 ball array
IS25WP512M-TMLE
16-pin SOIC 300mil
IS25WP512M-TGLE
24-ball TFBGA 6x8mm 4x6 ball array (Call Factory)
IS25WP512M-THLE
24-ball TFBGA 6x8mm 5x5 ball array
IS25WP512M-JLLA3
8-contact WSON (8x6mm)
IS25WP512M-JMLA3
16-pin SOIC 300mil
IS25WP512M-JGLA3
24-ball TFBGA 6x8mm 4x6 ball array (Call Factory)
IS25WP512M-JHLA3
24-ball TFBGA 6x8mm 5x5 ball array
IS25WP512M-RMLA3
16-pin SOIC 300mil
IS25WP512M-RGLA3
24-ball TFBGA 6x8mm 4x6 ball array (Call Factory)
IS25WP512M-RHLA3
24-ball TFBGA 6x8mm 5x5 ball array
IS25WP512M-QLLA3
8-contact WSON (8x6mm)
IS25WP512M-QMLA3
16-pin SOIC 300mil
IS25WP512M-QHLA3
24-ball TFBGA 6x8mm 5x5 ball array
IS25WP512M-PMLA3
16-pin SOIC 300mil
IS25WP512M-PHLA3
24-ball TFBGA 6x8mm 5x5 ball array
IS25WP512M-KLLA3
8-contact WSON (8x6mm)
IS25WP512M-KMLA3
16-pin SOIC 300mil
IS25WP512M-KGLA3
24-ball TFBGA 6x8mm 4x6 ball array (Call Factory)
IS25WP512M-KHLA3
24-ball TFBGA 6x8mm 5x5 ball array
IS25WP512M-TMLA3
16-pin SOIC 300mil
IS25WP512M-TGLA3
24-ball TFBGA 6x8mm 4x6 ball array (Call Factory)
IS25WP512M-THLA3
24-ball TFBGA 6x8mm 5x5 ball array
Note:
1. A3 meets AEC-Q100 requirements with PPAP.
Temp Grades: E= -40 to 105°C, A3= -40 to 125°C
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