IS25LQ020/040
2 Mbit / 4 Mbit Single Operating Voltage Serial Flash Memory
With 104 MHz Dual- or 100MHz Quad-Output SPI Bus Interface
FEATURES
• Single Power Supply Operation
- Low voltage range: 2.3 V - 3.6 V
• Memory Organization
- IS25LQ020: 256K x 8 (2 Mbit)
- IS25LQ040: 512K x 8 (4 Mbit)
• Cost Effective Sector/Block Architecture
- 2Mb / 4Mb : Uniform 4KByte sectors / sixteen
uniform 64KByte blocks
• Serial Peripheral Interface (SPI) Compatible
- Supports single-, dual- or quad-output
- Supports SPI Modes 0 and 3
- Maximum 33 MHz clock rate for normal read
- Maximum 104 MHz clock rate for fast read
- Maximum 208MHz clock rate
- Maximum 400MHz clock rate equivalent Quad SPI
• Byte Program Operation
- Typical 10 us/Byte
• Page Program (up to 256 Bytes) Operation
- Maximum 0.7ms per page program
• Sector, Block or Chip Erase Operation
- Sector Erase (4KB)150ms (Typ)
- Block Erase (64KB)500ms (Typ)
- Chip Erase 0.5s (2Mb)
- Chip Erase 1s (4Mb)
PRELIMINARY DATASHEET
• Low Power Consumption
- Max 12 mA active read current
- Max 20 mA program/erase current
- Max 50 uA standby current
• Hardware Write Protection
- Protect and unprotect the device from write
operation by Write Protect (WP#) Pin
• Software Write Protection
- The Block Protect (BP3, BP2, BP1, BP0) bits
allow partial or entire memory to be configured as
read-only
• High Product Endurance
- Guaranteed 100,000 program/erase cycles per
single sector
- Minimum 20 years data retention
• Industrial Standard Pin-out and Package
- 8-pin 208mil SOIC
- 8-pin 150mil SOIC
- 8-pin 150mil VVSOP
- 8-contact WSON
- PDIP
- Lead-free (Pb-free), package
•Additional 256-byte Security information one-time
programmable (OTP) area
•Special protect function
- Safe guard function (Appendix 1)
- Sector unlock function (Appendix 2)
GENERAL DESCRIPTION
The IS25LQ020/040 is 2 Mbit / 4 Mbit Serial Peripheral Interface (SPI) Flash memories, providing single-, dual
or quad-output. The devices are designed to support a 33 MHz fclock rate in normal read mode, and 104 MHz in
fast read (Quad output is 100MHz), the fastest in the industry. The devices use a single low voltage power
supply, ranging from 2.3 Volt to 3.6 Volt, to perform read, erase and program operations. The devices can be
programmed in standard EPROM programmers.
The IS25LQ020/040 are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output (Sl),
Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. The devices support page program
mode, where 1 to 256 bytes data can be programmed into the memory in one program operation. These
devices are divided into uniform 4 KByte sectors or uniform 64 KByte blocks.
The IS25LQ020/040 are offered in 8-pin SOIC 208mil, 8-pin PDIP, 8-pin VVSOP and 8-contact WSON.
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1
IS25LQ020/040
CONNECTION DIAGRAMS
CE#
1
8
SO (IO1)
2
7
Vcc
HOLD# (IO3)
WP# (IO2)
3
6
SCK
GND
4
5
SI (IO0)
8-Pin SOIC/VVSOP
1
8
SO (IO1)
2
7
WP# (IO 2)
3
6
GND
4
5
CE #
CE#
1
8 Vcc
SO (IO1)
2
7 HOLD#(IO3)
WP# (IO2)
3
6 SCK
GND
4
5 SI (IO0)
8-Contact WSON
Vcc
HOLD#(IO3)
SCK
SI ( IO 0 )
8-Pin PDIP
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2
IS25LQ020/040
PIN DESCRIPTIONS
SYMBOL
TYPE
DESCRIPTION
CE#
INPUT
SCK
SI (IO0)
SO (IO1)
GND
Vcc
WP#
(IO2)
INPUT
INPUT/OUTPUT
INPUT/OUTPUT
Chip Enable: CE# low activates the devices internal circuitries for
device operation. CE# high deselects the devices and switches into
standby mode to reduce the power consumption. When a device is not
selected, data will not be accepted via the serial input pin (Sl), and the
serial output pin (SO) will remain in a high impedance state.
Serial Data Clock
Serial Data Input/Output
Serial Data Input/Output
Ground
Device Power Supply
Write Protect/Serial Data Output: A hardware program/erase protection for all or
part of a memory array. When the WP# pin is low, memory array write-protection
depends on the setting of BP3, BP2, BP1 and BP0 bits in the Status Register.
When the WP# is high, the status register are not write-protected.
HOLD#
(IO3)
INPUT/OUTPUT
INPUT/OUTPUT
Hold: Pause serial communication by the master device without resetting
the serial sequence.
Serial Data
Input & Output (for 4xI/O read mode)
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IS25LQ020/040
BLOCK DIAGRAM
WP# (IO2)
SI (IO0)
SO (IO1)
HOLD#
(IO3)
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4
IS25LQ020/040
SPI MODES DESCRIPTION
Multiple IS25LQ020/040 devices can be connected on
the SPI serial bus and controlled by a SPI Master, i.e.
microcontroller, as shown in Figure 1. The devices
support either of two SPI modes:
Mode 0 (0, 0)
Mode 3 (1, 1)
The difference between these two modes is the clock
polarity when the SPI master is in Stand-by mode: the
serial clock remains at “0” (SCK = 0) for Mode 0 and
the clock remains at “1” (SCK = 1) for Mode 3. Please
refer to Figure 2. For both modes, the input data is
latched on the rising edge of Serial Clock (SCK), and
the output data is available from the falling edge of
SCK.
Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices)
SDI
SPI Interface with
(0,0) or (1,1)
SDI
SCK
SCK
SPI Master
(i.e. Microcontroller)
CS3
CS2
SO
SI
SCK
SPI Memory
Device
CS1
CE#
WP#
SO
SI
SCK
CE#
WP#
CE#
HOLD#
SI
SPI Memory
Device
SPI Memory
Device
HOLD#
SO
WP#
HOLD#
Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as
appropriate.
Figure 2. SPI Modes Supported
SCK
Mode 0 (0,0)
SCK
Mode 3 (1,1)
SI
MSb
Input mode
SO
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MSb
5
IS25LQ020/040
SYSTEM CONFIGURATION
The IS25LQ020/040 devices are designed to interface directly with the synchronous Serial Peripheral Interface
(SPI) of the Motorola MC68HCxx series of microcontrollers or any SPI interface-equipped system controllers.
The devices have two superset features that can be enabled through specific software instructions and the
Configuration Register:
1. Configurable sector size: The memory array of
IS25LQ020/040 is divided into uniform 4 KByte sectors or uniform 64 KByte blocks (a block consists of sixteen
adjacent sectors).
Table 1 illustrates the memory map of the devices.
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6
IS25LQ020/040
BLOCK/SECTOR ADDRESSES
Table 1. Block/Sector Addresses of IS25LQ020
Memory Density
Block No.
(64Kbyte)
Block 0
2Mbit
Block 1
:
Block 3
Sector No.
Sector 0
Sector 1
:
Sector 15
Sector 16
Sector 17
:
Sector 31
:
Sector 63
Sector
Size
(KBytes)
4
4
:
4
4
4
:
4
:
4
Address Range
000000h - 000FFFh
001000h - 001FFFh
:
00F000h - 00FFFFh
010000h - 010FFFh
011000h - 011FFFh
:
01F000h - 01FFFFh
:
03F000h – 03FFFFh
Table 2. Block/Sector Addresses of IS25LQ040
Memory Density
Block No.
(64Kbyte)
Block 0
4Mbit
Block 1
:
Block 7
Sector No.
Sector 0
Sector 1
:
Sector 15
Sector 16
Sector 17
:
Sector 31
:
Sector 127
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Sector
Size
(KBytes)
4
4
:
4
4
4
:
4
:
4
Address Range
000000h - 000FFFh
001000h - 001FFFh
:
00F000h - 00FFFFh
010000h - 010FFFh
011000h - 011FFFh
:
01F000h - 01FFFFh
:
070000h – 07FFFFh
7
IS25LQ020/040
REGISTERS (CONTINUED)
STATUS REGISTER
Refer to Tables 5 and 6 for Status Register Format and BP3, BP2, BP1, BP0 bits: The Block Protection (BP3,
Status Register Bit Definitions.
BP2, BP1 and BP0) bits are used to define the portion
of the memory area to be protected. Refer to Tables 7,
The BP0, BP1, BP2, BP3 and SRWD are non-volatile
8 and 9 for the Block Write Protection bit settings.
memory cells that can be written by a Write Status
When a defined combination of BP3, BP2, BP1 and
Register (WRSR) instruction. The default value of the
BP0 bits are set, the corresponding memory area is
BP2, BP1, BP0, and SRWD bits were set to “0” at
protected. Any program or erase operation to that area
factory. The Status Register can be read by the Read
will be inhibited.Note: a Chip Erase (CHIP_ER)
Status Register (RDSR). Refer to Table 10 for
instruction is executed only if all the Block Protection
Instruction Set.
Bits are set as “0”s.
The function of Status Register bits are described as
follows:
WIP bit: The Write In Progress (WIP) bit is read-only,
and can be used to detect the progress or completion
of a program or erase operation. When the WIP bit is
“0”, the device is ready for a write status register,
program or erase operation. When the WIP bit is “1”,
the device is busy.
WEL bit: The Write Enable Latch (WEL) bit indicates
the status of the internal write enable latch. When the
WEL is “0”, the write enable latch is disabled, and all
write operations, including write status register, write
configuration register, page program, sector erase,
block and chip erase operations are inhibited. When
the WEL bit is “1”, write operations are allowed. The
WEL bit is set by a Write Enable (WREN) instruction.
Each write register, program and erase instruction
must be preceded by a WREN instruction. The WEL bit
can be reset by a Write Disable (WRDI) instruction. It
will automatically be the reset after the completion of a
write instruction.
SRWD bit: The Status Register Write Disable (SRWD)
bits operates in conjunction with the Write Protection
(WP#) signal to provide a Hardware Protection Mode.
When the SRWD is set to “0”, the Status Register is
not write-protected. When the SRWD is set to “1” and
the WP# is pulled low (VIL), the bits of Status Register
(SRWD, BP3, BP2, BP1, BP0) become read-only, and
a WRSR instruction will be ignored. If the SRWD is set
to “1” and WP# is pulled high (VIH), the Status Register
can be changed by a WRSR instruction.
QE bit: The Quad Enable (QE) is a non-volatile bit in
the status register that allows Quad operation. When
the QE bit is set to “0”,the pin WP# and HOLD# are
enable. When the QE bit is set to “1”, the pin IO2 and
IO3 are enable.
Table 5. Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRWD
QE
BP3
BP2
BP1
BP0
WEL
WIP
Default (flash bit)
0
0
0
0
0
0
0
* The default value of the BP3, BP2, BP1, BP0, and SRWD bits were set to “0” at factory.
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0
8
IS25LQ020/040
REGISTERS (CONTINUED)
Table 6. Status Register Bit Definition
Bit
Name
Definition
Bit 0
WIP
Bit 1
WEL
Bit 2
Bit 3
Bit 4
Bit 5
BP0
BP1
BP2
BP3
Bit 6
QE
Bit 7
SRWD
Write In Progress Bit:
"0" indicates the device is ready
"1" indicates a write cycle is in progress and the device is busy
Write Enable Latch:
"0" indicates the device is not write enabled (default)
"1" indicates the device is write enabled
Block Protection Bit: (See Tables 7, 8 and 9 for details)
"0" indicates the specific blocks are not write-protected (default)
"1" indicates the specific blocks are write-protected
Quad Enable bit:
“0” indicates the Quad output function disable (default)
“1” indicates the Quad output function enable
Status Register Write Disable: (See Table 10 for details)
"0" indicates the Status Register is not write-protected (default)
"1" indicates the Status Register is write-protected
Read/Write
Non-Volatile
bit
R
No
R/W
No
R/W
Yes
R/W
Yes
R/W
Yes
Table 9. Block Write Protect Bits for IS25LQ020/040
Status Register Bits
Protected Memory Area
BP3
BP2
BP1
BP0
2 Mbit
4 Mbit
0
0
0
0
None
None
0
0
0
1
(1 block : 7th)
(1 block : 7th):
0
0
1
0
(2 blocks :6th to 7th)
(2 blocks :6th to 7th)
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
(4 blocks :4th to 7th)
All blocks ( 3 blocks : 0 to 3)
All blocks (8blocks : 0 to 7)
1
(2 blocks :0th to 1th)
(2 blocks :0th to 1th):
1
0
(1 blocks :0th )
(1 blocks :0th )
1
1
None
None
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(4 blocks :0th to 3th)
9
IS25LQ020/040
REGISTERS (CONTINUED)
PROTECTION MODE
The IS25LQ020/040 have two types of writeprotection mechanisms: hardware and software.
These are used to prevent irrelevant operation in a
possibly noisy environment and protect the data
integrity.
HARDWARE WRITE-PROTECTION
The devices provide two hardware write-protection
features:
a. When inputting a program, erase or write status
register instruction, the number of clock pulse is
checked to determine whether it is a multiple of
eight before the executing. Any incomplete
instruction command sequence will be ignored.
b. Write inhibit is 2.0V, all write sequence will be
ignored when Vcc drop to 2.0V and lower.
c. The Write Protection (WP#) pin provides a
hardware write protection method for BP3, BP2,
BP1, BP0 and SRWD in the Status Register. Refer
to the STATUS REGISTER description.
SOFTWARE WRITE PROTECTION
The IS25LQ020/040 also provides two software
write protection features:
a. Before the execution of any program, erase or
write status register instruction, the Write Enable
Latch (WEL) bit must be enabled by executing a
Write Enable (WREN) instruction. If the WEL bit is
not enabled first, the program, erase or write
register instruction will be ignored.
b. The Block Protection (BP3, BP2, BP1, BP0) bits
allow part or the whole memory area to be writeprotected.
Table 10. Hardware Write Protection on Status
Register
SRWD
WP#
Status Register
0
1
0
1
Low
Low
High
High
Writable
Protected
Writable
Writable
DEVICE OPERATION
The IS25LQ020/040 utilize an 8-bit instruction register.
Refer to Table 11 Instruction Set for details of the
Instructions and Instruction Codes. All instructions,
addresses, and data are shifted in with the most
significant bit (MSB) first on Serial Data Input (SI). The
input data on SI is latched on the rising edge of Serial
Clock (SCK) after Chip Enable (CE#) is driven low
(VIL). Every instruction sequence starts with a one-byte
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instruction code and is followed by address bytes, data
bytes, or both address bytes and data bytes,
depending on the type of instruction. CE# must be
driven high (VIH) after the last bit of the instruction
sequence has been shifted in.
The timing for each instruction is illustrated in the
following operational descriptions.
10
IS25LQ020/040
Table 11. Instruction Set
Instruction Name
Hex
Code
Operation
Comman
d Cycle
Maximum
Frequency
RDID
JEDEC ID READ
RDMDID
WREN
WRDI
RDSR
WRSR
READ
FAST_READ
FRDO
FRDIO
FRQO
FRQIO
MR
PAGE_ PROG
ABh
9Fh
90h
06h
04h
05h
01h
03h
0Bh
3Bh
BBh
6Bh
EBh
FFh
02h
Read Manufacturer and Product ID
Read Manufacturer and Product ID by JEDEC ID Command
Read Manufacturer and Device ID
Write Enable
Write Disable
Read Status Register
Write Status Register
Read Data Bytes from Memory at Normal Read Mode
Read Data Bytes from Memory at Fast Read Mode
Fast Read Dual Output
Fast Read Dual I/O
Fast Read Quad Output
Fast Read Quad I/O
Mode Reset
Page Program Data Bytes Into Memory
104 MHz
104 MHz
104 MHz
104 MHz
104 MHz
104 MHz
104 MHz
33 MHz
104 MHz
104 MHz
104MHz
100 MHz
100MHz
104MHz
104 MHz
SECTOR_ER
D7h/
20h
D8h
C7h/
60h
32h
Sector Erase
4 Bytes
1 Byte
4 Bytes
1 Byte
1 Byte
1 Byte
2 Bytes
4 Bytes
5 Bytes
5 Bytes
3 Bytes
5 Bytes
2 Bytes
2 Byte
4 Bytes
+ 256B
4 Bytes
Block Erase 64K byte
Chip Erase
4 Bytes
1 Byte
104 MHz
104 MHz
Page Program Data Bytes Into Memory with Quad interface
4 Bytes
+ 256B
75h
/B0h
7Ah
/30h
B1h
Suspend during the program/erase
104MHz
Resume program/erase
104MHz
Program 256 bytes of Security area
4 Bytes
104 MHz
4Bh
Read 256 bytes of Security area
4 Bytes
33 MHz
BLOCK_ER (64KB)
CHIP_ER
Quad page program
Program/Erase
suspend
Program/Erase
resume
Program information
Raw
Read information
Raw
104 MHz
HOLD OPERATION
HOLD# is used in conjunction with CE# to select
the IS25LQ020/040. When the devices are selected
and a serial sequence is underway, HOLD# can be
used to pause the serial communication with the
master device without resetting the serial sequence.
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To pause, HOLD# is brought low while the SCK
signal is low. To resume serial communication,
HOLD# is brought high while the SCK signal is low
(SCK may still toggle during HOLD). Inputs to Sl will
be ignored while SO is in the high impedance state.
11
IS25LQ020/040
DEVICE OPERATION (CONTINUED)
RDID COMMAND (READ PRODUCT
IDENTIFICATION)/
OPERATION
The Read Product Identification (RDID)
instruction is for reading out the old style of 8-bit
Electronic Signature, whose values are shown as table
of ID Definitions. This is not same as RDID or JEDEC
ID instruction. It’s not recommended to use for new
design. For new design, please use RDID or JEDEC ID
instruction.
The RDES instruction code is followed by three dummy
bytes, each bit being latched-in on SI during the rising Table 12. Product Identification
edge of SCK. Then the Device ID is shifted out on SO
with the MSB first, each bit been shifted out during the
Product Identification
falling edge of SCK. The RDES instruction is ended by
First Byte
CE# goes high. The Device ID outputs repeatedly if
Manufacturer ID
continuously send the additional clock cycles on SCK
Second Byte
while CE# is at low.
Device ID:
Device ID1
IS25LQ020C
IS25LQ040C
Data
11h
12h
9Dh
7Fh
Device ID2
42h
43h
Figure 3. Read Product Identification Sequence
CE#
0
1
7
8
9
38
31
46
39
47
54
SCK
INSTRUCTION
SI
SO
3 Dummy Bytes
1010 1011b
HIGH IMPEDANCE
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Device ID1
Device ID1
Device ID1
12
IS25LQ020/040
DEVICE OPERATION (CONTINUED)
JEDEC ID READ COMMAND (READ PRODUCT IDENTIFICATION BY JEDEC ID)
OPERATION
The JEDEC ID READ instruction allows the user to
read the manufacturer and product ID of devices. Refer
to Table 10 Product Identification for pFlash
Manufacturer ID and Device ID. After the JEDEC ID
READ command is input, the Manufacturer ID1 is
shifted out on SO with the MSB first, followed by the
first Device ID1and the Device ID2, in the case of the,
each bit shifted out during the falling edge of SCK. If
CE# stays low after the last bit of the Device ID is
shifted out, the Manufacturer ID and Device ID will loop
until CE# is pulled high.
Figure 4. Read Product Identification by JEDEC ID READ Sequence
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IS25LQ020/040
DEVICE OPERATION (CONTINUED)
RDMDID COMMAND (READ DEVICE MANUFACTURER AND DEVICE ID)
OPERATION
The Read Product Identification (RDID) instruction
allows the user to read the manufacturer and product
ID of the devices. Refer to Table 12 Product
Identification for pFLASH™ manufacturer ID and
device ID. The RDID instruction code is followed by
two dummy bytes and one byte address (A7~A0), each
bit being latched-in on SI during the rising edge of SCK.
If one byte address is initially set to A0 = 0, then the
first manufacturer ID (9Dh) is shifted out on SO with
the MSB first, the device ID1 and the second
manufacturer ID (7Fh), each bit been shifted out during
the falling edge of SCK. If one byte address is initially
set to A0 = 1, then device ID1 will be read first, then
followed by the first manufacture ID (9Dh) and then
second manufacture ID (7Fh). The manufacture and
device ID can be read continuously, alternating from
one to the others. The instruction is completed by
driving CE# high.
Figure 5. Read Product Identification by RDMDID READ Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10
11
SCK
28
29
30
31
1
A0
...
3 - BYTE ADDRESS
SIO
INSTRUCTION = 1001 0000b
23
22
42
43
... 3
21
2
HIGH IMPEDANCE
SO
CE#
32
33
34
35
36
37
38
39
40
41
44
45
46
47
2
1
0
SCK
SIO
Data Out1
SO
7
6
5
4
3
Data Out2
2
1
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7
6
5
4
3
14
IS25LQ020/040
CE#
48
49
50
51
52
53
54
55
4
3
2
1
0
56
SCK
SIO
Data Out3
SO
7
6
5
Note :
(1) ADDRESS A0 = 0, will output the 1st manufacture ID (9Dh) first -> device ID1 -> 2nd manufacture ID (7Fh)
ADDRESS A0 = 1, will output the device ID1 -> 1st manufacture ID (9D) -> 2nd manufacture ID (7Fh)
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IS25LQ020/040
DEVICE OPERATION (CONTINUED)
WRITE ENABLE OPERATION
The Write Enable (WREN) instruction is used to set the
Write Enable Latch (WEL) bit. The WEL bit of the
IS25LQ016 is reset to the write –protected state after
power-up. The WEL bit must be write enabled before
any write operation, including sector, block erase, chip
erase, page program, write status register, and write
configuration register operations. The WEL bit will be
reset to the write-protect state automatically upon
completion of a write operation. The WREN instruction
is required before any above operation is executed.
Figure 6. Write Enable Sequence
WRDI COMMAND (WRITE DISABLE) OPERATION
The Write Disable (WRDI) instruction resets the WEL
bit and disables all write instructions. The WRDI
instruction is not required after the execution of a write
instruction, since the WEL bit is automatically reset.
Figure 7. Write Disable Sequence
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IS25LQ020/040
DEVICE OPERATION (CONTINUED)
RDSR COMMAND (READ STATUS REGISTER) OPERATION
The Read Status Register (RDSR) instruction provides
access to the Status Register. During the execution of
a program, erase or write status register operation, all
other instructions will be ignored except the RDSR
instruction, which can be used to check the progress or
completion of an operation by reading the WIP bit of
Status Register.
Figure 8. Read Status Register Sequence
WRSR COMMAND (WRITE STATUS REGISTER) OPERATION
The Write Status Register (WRSR) instruction allows
the user to enable or disable the block protection and
status register write protection features by writing “0”s
or “1”s into the non-volatile BP3, BP2, BP1, BP0 and
SRWD bits.
Figure 9. Write Status Register Sequence
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IS25LQ020/040
DEVICE OPERATION (CONTINUED)
READ COMMAND (READ DATA) OPERATION
The Read Data (READ) instruction is used to read
memory data of a IS25LQ020/040under normal mode
running up to 33 MHz.
The READ instruction code is transmitted via the Sl
line, followed by three address bytes (A23 - A0) of the
first memory location to be read. A total of 24 address
bits are shifted in, but only AMS (most significant
address) - A0 are decoded. The remaining bits (A23 –
AMS) are ignored. The first byte addressed can be at
any memory location. Upon completion, any data on
the Sl will be ignored. Refer to Table 13 for the related
Address Key.
out on the SO line, MSb first. A single byte of data, or
up to the whole memory array, can be read out in one
READ instruction. The address is automatically
incremented after each byte of data is shifted out. The
read operation can be terminated at any time by driving
CE# high (VIH) after the data comes out. When the
highest address of the devices is reached, the address
counter will roll over to the 000000h address, allowing
the entire memory to be read in one continuous READ
instruction.
If a Read Data instruction is issued while an Erase,
Program or Write cycle is in process (BUSY=1) the
instruction is ignored and will not have any effects on the
current cycle
The first byte data (D7 - D0) addressed is then shifted
Table 13. Address Key
Address
IS25LQ020/040
AN (AMS – A0)
Don't Care Bits
A19 - A0
A23 – A20
Figure 12. Read Data Sequence
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IS25LQ020/040
DEVICE OPERATION (CONTINUED)
FAST_READ COMMAND (FAST READ DATA) OPERATION
The FAST_READ instruction is used to read memory
data at up to a 104 MHz clock.
The first byte addressed can be at any memory
location. The address is automatically incremented
after each byte of data is shifted out. When the highest
The FAST_READ instruction code is followed by three address is reached, the address counter will roll over to
address bytes (A23 - A0) and a dummy byte (8 clocks), the 000000h address, allowing the entire memory to be
transmitted via the SI line, with each bit latched-in
read with a single FAST_READ instruction. The
during the rising edge of SCK. Then the first data byte FAST_READ instruction is terminated by driving CE#
addressed is shifted out on the SO line, with each bit
high (VIH). If a Fast Read Data instruction is issued while
an Erase, Program or Write cycle is in process (BUSY=1)
shifted out at a maximum frequency fCT, during the
the instruction is ignored and will not have any effects on
falling edge of SCK.
the current cycle
Figure 13. Fast Read Data Sequence
SIO
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IS25LQ020/040
DEVICE OPERATION (CONTINUED)
FRDO COMMAND (FAST READ DUAL OUTPUT) OPERATION
The FRDO instruction is used to read memory data on
two output pins each at up to a 104 MHz clock.
The first byte addressed can be at any memory
location. The address is automatically incremented
after each byte of data is shifted out. When the highest
address is reached, the address counter will roll over to
the 000000h address, allowing the entire memory to be
read with a single FRDO instruction. FRDO instruction
is terminated by driving CE# high (VIH). If a FRDO
instruction is issued while an Erase, Program or Write
cycle is in process (BUSY=1) the instruction is ignored
and will not have any effects on the current cycle
The FRDO instruction code is followed by three
address bytes (A23 – A0) and a dummy byte (8
clocks), transmitted via the SI line, with each bit
latched-in during the rising edge of SCK. Then the first
data byte addressed is shifted out on the SO and SIO
lines, with each pair of bits shifted out at a maximum
frequency fCT, during the falling edge of SCK. The first
bit (MSb) is output on SO, while simultaneously the
second bit is output on SIO.
Figure 14. Fast Read Dual-Output Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10
11
SCK
28
30
31
2
1
0
29
...
3 - BYTE ADDRESS
SI
INSTRUCTION = 0011 1011b
23
22 21
... 3
HIGH IMPEDANCE
SO
CE#
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
6
4
2
0
6
4
2
0
6
1
7
SCK
IO0
HIGH IMPEDANCE
DATA OUT 1
IO1
HIGH IMPEDANCE
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7
5
3
DATA OUT 2
1
7
5
3
20
IS25LQ020/040
DEVICE OPERATION (CONTINUED)
FRDIO COMMAND (FAST READ DUAL I/O) OPERATION
The FRDIO instruction is similar to the FRDO
instruction, but allows the address bits to be input two
bits at a time. This may allow for code to be executed
directly from the SPI in some applications.
The FRDIO instruction code is followed by three
address bytes (A23 – A0) and a mode byte,
transmitted via the IO0 and IO1 lines, with each pair of
bits latched-in during the rising edge of SCK. The
address MSb is input on IO1, the next bit on IO0, and
continues to shift in alternating on the two lines. The
mode byte contains the value Ax, where x is a “don’t
care” value. Then the first data byte addressed is
shifted out on the IO1 and IO0 lines, with each pair of
bits shifted out at a maximum frequency fCT, during the
falling edge of SCK. The MSb is output on IO1, while
simultaneously the second bit is output on IO0. Figure
15 illustrates the timing sequence.
The first byte addressed can be at any memory
location. The address is automatically incremented
after each byte of data is shifted out. When the highest
address is reached, the address counter will roll over to
the 000000h address, allowing the entire memory to be
read with a single FRDIO instruction. FRDIO
instruction is terminated by driving CE# high (VIH).
The device expects the next operation will be another
FRDIO. It remains in this mode until it receives a
Mode Reset (FFh) command. In subsequent FRDIO
execution, the command code is not input, saving
timing cycles as described in Figure 16. If a FRDIO
instruction is issued while an Erase, Program or Write
cycle is in process (BUSY=1) the instruction is ignored
and will not have any effects on the current cycle
Figure 15. Fast Read Dual I/O Sequence (with command decode cycles)
CE#
0
2
1
3
4
5
6
8
7
9
10
SCK
11
18
19
20
21
...
3 - BYTE ADDRESS
IO0
INSTRUCTION = 1011 1011b
MODE BITS
22
21
19
... 2
0
6
4
23
22
20
... 3
1
7
5
IO1
CE#
22
23
24
25
26
6
4
2
27
28
29
30
4
2
31
SCK
IO0
0
6
DATA OUT 1
IO1
7
5
3
0
6
1
7
DATA OUT 2
1
7
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3
21
IS25LQ020/040
DEVICE OPERATION (CONTINUED)
Figure 16. Fast Read Dual I/O Sequence (without command decode cycles)
CE#
0
1
2
SCK
3
10
11
13
14
15
16
17
18
19
20
21
6
4
2
0
6
4
...
3 - BYTE ADDRESS
IO0
12
22
21 19
... 2
MODE BITS
0
6
4
DATA OUT 1
IO1
23 22
20
... 3
1
7
5
7
5
3
DATA OUT 2
1
7
5
FRQO COMMAND (FAST READ QUAD OUTPUT) OPERATION
The FRQO instruction is used to read memory data on
four output pins each at up to a 100 MHz clock.
simultaneously the second bit is output on IO2, the
third bit is output on IO1, etc.
The FRQO instruction code is followed by three
address bytes (A23 – A0) and a dummy byte (8
clocks), transmitted via the SI line, with each bit
latched-in during the rising edge of SCK. Then the first
data byte addressed is shifted out on the IO3, IO2, IO1
and IO0 lines, with each group of four bits shifted out at
a maximum frequency fCT, during the falling edge of
SCK. The first bit (MSb) is output on IO3, while
The first byte addressed can be at any memory
location. The address is automatically incremented
after each byte of data is shifted out. When the highest
address is reached, the address counter will roll over to
the 000000h address, allowing the entire memory to be
read with a single FRQO instruction. FRQO instruction
is terminated by driving CE# high (VIH). If a FRQO
instruction is issued while an Erase, Program or Write
cycle is in process (BUSY=1) the instruction is ignored
and will not have any effects on the current cycle
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IS25LQ020/040
DEVICE OPERATION (CONTINUED)
Figure 17. Fast Read Quad-Output Sequence
CE#
0
1
2
3
4
5
6
7
8
9
10
11
SCK
28
30
31
2
1
0
47
48
29
...
3 - BYTE ADDRESS
SI
INSTRUCTION = 0110 1011b
23
22 21
42
43
... 3
HIGH IMPEDANCE
SO
CE#
32
33
34
35
36
37
38
39
40
41
44
45
46
SCK
DATA OUT 1
IO0
IO1
HIGH IMPEDANCE
IO2
HIGH IMPEDANCE
IO3
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DATA OUT 2
...
DATA OUT n
4
0
4
0
4
0
4
0
4
5
1
5
1
5
1
5
1
5
6
2
6
2
6
2
6
2
6
7
3
7
3
7
3
7
3
7
23
IS25LQ020/040
DEVICE OPERATION (CONTINUED)
FRQIO COMMAND (FAST READ QUAD I/O) OPERATION
The FRQIO instruction is similar to the FRQO
instruction, but allows the address bits to be input four
bits at a time. This may allow for code to be executed
directly from the SPI in some applications.
third bit is output on IO1, etc. Figure 18 illustrates the
timing sequence.
The first byte addressed can be at any memory
location. The address is automatically incremented
The FRQIO instruction code is followed by three
after each byte of data is shifted out. When the highest
address bytes (A23 – A0) and a mode byte,
address is reached, the address counter will roll over to
transmitted via the IO3, IO2, IO0 and IO1 lines, with
the 000000h address, allowing the entire memory to be
each group of four bits latched-in during the rising edge read with a single FRQIO instruction. FRQIO
of SCK. The address MSb is input on IO3, the next bit instruction is terminated by driving CE# high (VIH).
on IO2, the next bit on IO1, the next bit on IO0, and
continue to shift in alternating on the four. The mode
The device expects the next operation will be another
byte contains the value Ax, where x is a “don’t care”
FRQIO. It remains in this mode until it receives a
value. After four dummy clocks, the first data byte
Mode Reset (FFh) command. In subsequent FRDIO
addressed is shifted out on the IO3, IO2, IO1 and IO0
execution, the command code is not input, saving
lines, with each group of four bits shifted out at a
cycles as described in Figure 19. If a FRQIO instruction
maximum frequency fCT, during the falling edge of SCK. is issued while an Erase, Program or Write cycle is in
process (BUSY=1) the instruction is ignored and will not
The first bit (MSb) is output on IO3, while
have any effects on the current cycle
simultaneously the second bit is output on IO2, the
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IS25LQ020/040
Figure 18. Fast Read Quad I/O Sequence (with command decode cycles)
CE#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
3 - BYTE ADDRESS
IO0
INSTRUCTION = 1110 1011b
20
16 12
MODE BITS
8
4
0
4
IO1
21 17
13
9
5
1
5
IO2
22 18
14
10
6
2
6
IO3
23 19
15
11
7
3
7
CE#
16
17
18
19
20
21
22
23
24
25
26
27
SCK
4 dummy cycles
DATA OUT 1 DATA OUT 2 DATA OUT 3 DATA OUT 4
IO0
4
0
4
0
4
0
4
0
4
IO1
5
1
5
1
5
1
5
1
5
IO2
6
2
6
2
6
2
6
2
6
IO3
7
3
7
3
7
3
7
3
7
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IS25LQ020/040
DEVICE OPERATION (CONTINUED)
Figure 19. Fast Read Quad I/O Sequence (without command decode cycles)
CE#
0
2
1
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
DATA OUT 1
3 - BYTE ADDRESS MODE BITS 4 Dummy Clock
IO0
20
16 12
8
4
0
4
IO1
21
17
13
9
5
1
5
IO2
22
18
14
10
6
2
6
IO3
23
19
15
11
7
3
7
DATA OUT 2
MR COMMAND (MODE RESET) OPERATION
The Mode Reset command is used to conclude
subsequent FRDIO and FRQIO operations. It
resets the Mode bits to a value that is not Ax. It
should be executed after an FRDIO or FRQIO
operation, and is recommended also as the first
command after a system reset. The timing
sequence is different depending whether the MR
command is used after an FRDIO or FRQIO, as
shown in Figure 20.
Figure 20, Mode Reset Command
Mode Reset for
Dual I/O
Mode Reset for
Quad I/O
CE#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SIO
SO
INSTRUCTION = 1111 1111b
INSTRUCTION = 1111 1111b
HIGH IMPEDANCE
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IS25LQ020/040
DEVICE OPERATION (CONTINUED)
PAGE_PROG COMMAND (PAGE PROGRAM) OPERATION
The Page Program (PAGE_PROG) instruction allows
up to 256 bytes data to be programmed into memory in
a single operation. The destination of the memory to be
programmed must be outside the protected memory
area set by the Block Protection (BP2, BP1, BP0) bits.
A PAGE_PROG instruction which attempts to program
into a page that is write-protected will be ignored.
Before the execution of PAGE_PROG instruction, the
Write Enable Latch (WEL) must be enabled through a
Write Enable (WREN) instruction.
The PAGE_PROG instruction code, three address
bytes and program data (1 to 256 bytes) are input via
the Sl line. Program operation will start immediately
after the CE# is brought high, otherwise the
PAGE_PROG instruction will not be executed. The
internal control logic automatically handles the
programming voltages and timing. During a program
operation, all instructions will be ignored except the
RDSR instruction. The progress or completion of the
program operation can be determined by reading the
WIP bit in Status Register via a RDSR instruction. If
the WIP bit is “1”, the program operation is still in
progress. If WIP bit is “0”, the program operation has
completed.
If more than 256 bytes data are sent to a device, the
address counter rolls over within the same page, the
previously latched data are discarded, and the last 256
bytes data are kept to be programmed into the page.
The starting byte can be anywhere within the page.
When the end of the page is reached, the address will
wrap around to the beginning of the same page. If the
data to be programmed are less than a full page, the
data of all other bytes on the same page will remain
unchanged.
Note: A program operation can alter “1”s into “0”s, but
an erase operation is required to change “0”s back to
“1”s. A byte cannot be reprogrammed without first
erasing the whole sector or block.
Figure 21. Page Program Sequence
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IS25LQ020/040
DEVICE OPERATION (CONTINUED)
The Quad Input Page Program instruction allows up
to 256 bytes data to be programmed into memory in
a single operation with four pins (IO0, IO1, IO2 and
IO3). The destination of the memory to be
programmed must be outside the protected memory
area set by the Block Protection (BP3, BP2, BP1,
BP0) bits. A Quad Input Page Program instruction
which attempts to program into a page that is writeprotected will be ignored. Before the execution of
Quad Input Page Program instruction, the QE bit in
the status register must be set to “1” and the Write
Enable Latch (WEL) must be enabled through a Write
Enable (WREN) instruction.
The Quad Input Page Program instruction code,
three address bytes and program data (1 to 256
bytes) are input via the four pins (IO0, IO1, IO2 and
IO3). Program operation will start immediately after
the CE# is brought high, otherwise the Quad Input
Page Program instruction will not be executed. The
internal control logic automatically handles the
programming voltages and timing. During a program
operation, all instructions will be ignored except the
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RDSR instruction. The progress or completion of the
program operation can be determined by reading the
WIP bit in Status Register via a RDSR instruction. If
the WIP bit is “1”, the program operation is still in
progress. If WIP bit is “0”, the program operation has
completed.
If more than 256 bytes data are sent to a device, the
address counter rolls over within the same page, the
previously latched data are discarded, and the last
256 bytes data are kept to be programmed into the
page. The starting byte can be anywhere within the
page. When the end of the page is reached, the
address will wrap around to the beginning of the
same page. If the data to be programmed are less
than a full page, the data of all other bytes on the
same page will remain unchanged.
Note: A program operation can alter “1”s into “0”s,
but an erase operation is required to change “0”s
back to “1”s. A byte cannot be reprogrammed without
first erasing the whole sector or block.
28
IS25LQ020/040
CE#
0
2
1
3
4
5
6
7
8
9
10
SCK
11
28
29
30
31
1
0
...
3 - BYTE ADDRESS
IO0
INSTRUCTION = 0101
0010b
00110010b
23
22 21
... 3
2
IO1
IO2
IO3
CE#
32
33
34
35
36
37
38
39
SCK
DATA IN 1
IO0
DATA IN 2
...
DATA IN n
4
0
4
0
4
0
4
0
4
5
1
5
1
5
1
5
1
5
IO2
6
2
6
2
6
2
6
2
6
IO3
7
3
7
3
7
3
7
3
7
IO1
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IS25LQ020/040
DEVICE OPERATION (CONTINUED)
ERASE OPERATION
The memory array of the IS25LQ020/040 is organized
into uniform 4 Kbyte sectors or 64 Kbyte uniform
blocks (a block consists of sixteen adjacent sectors).
Before a byte can be reprogrammed, the sector or
block that contains the byte must be erased (erasing
sets bits to “1”). In order to erase the devices, there are
three erase instructions available: Sector Erase
(SECTOR_ER), Block Erase (BLOCK_ER) and Chip
Erase (CHIP_ER). A sector erase operation allows any
individual sector to be erased without affecting the data
in other sectors. A block erase operation erases any
individual block. A chip erase operation erases the
whole memory array of a device. A sector erase, block
erase or chip erase operation can be executed prior to
any programming operation.
SECTOR_ER COMMAND (SECTOR ERASE)
OPERATION
operation can be determined by reading the WIP bit in
the Status Register using a RDSR instruction. If the
WIP bit is “1”, the erase operation is still in progress. If
the WIP bit is “0”, the erase operation has been
completed.
BLOCK_ER COMMAND (BLOCK ERASE)
OPERATION
A Block Erase (BLOCK_ER) instruction erases a 64
Kbyte block of the IS25LQ016. Before the execution of
a BLOCK_ER instruction, the Write Enable Latch
(WEL) must be set via a Write Enable (WREN)
instruction. The WEL is reset automatically after the
completion of a block erase operation.
The BLOCK_ER instruction code and three address
bytes are input via SI. Erase operation will start
immediately after the CE# is pulled high, otherwise the
BLOCK_ER instruction will not be executed. The
internal control logic automatically handles the erase
voltage and timing. Refer to Figure 23 for Block Erase
Sequence.
A SECTOR_ER instruction erases a 4 Kbyte sector
Before the execution of a SECTOR_ER instruction, the
Write Enable Latch (WEL) must be set via a Write
CHIP_ER COMMAND (CHIP ERASE) OPERATION
Enable (WREN) instruction. The WEL bit is reset
automatically after the completion of sector an erase
A Chip Erase (CHIP_ER) instruction erases the entire
operation.
memory array of a IS25LQ016. Before the execution of
CHIP_ER instruction, the Write Enable Latch (WEL)
A SECTOR_ER instruction is entered, after CE# is
must be set via a Write Enable (WREN) instruction.
pulled low to select the device and stays low during the The WEL is reset automatically after completion of a
entire instruction sequence The SECTOR_ER
chip erase operation.
instruction code, and three address bytes are input via
SI. Erase operation will start immediately after CE# is
The CHIP_ER instruction code is input via the SI.
pulled high. The internal control logic automatically
Erase operation will start immediately after CE# is
handles the erase voltage and timing. Refer to Figure
pulled high, otherwise the CHIP_ER instruction will not
22 for Sector Erase Sequence.
be executed. The internal control logic automatically
handles the erase voltage and timing. Refer to Figure
During an erase operation, all instruction will be
24 for Chip Erase Sequence.
ignored except the Read Status Register (RDSR)
instruction. The progress or completion of the erase
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IS25LQ020/040
DEVICE OPERATION (CONTINUED)
Figure 22. Sector Erase Sequence
Figure 23. Block Erase Sequence
Figure 24. Chip Erase Sequence
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IS25LQ020/040
DEVICE OPERATION (CONTINUED)
Program Security information Row instruction (PSIR)
The PSIR instructions can read and programmed (Erase) using three dedicated instructions. The program
information Raw instruction is used to program at most 256 bytes to the security memory area (by changing bits
from ‘1’ to ‘0’, only). Before it can be accepted, a write enable (WREN) instruction must previously have been
executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch
(WEL) bit. The program information Row instruction is entered by driving CE# pin Low, followed by the
instruction code, three address bytes and at least one data byte on serial data input (SI). CE# pin must be
driven High after the eighth bits of the last data byte has been latched in, otherwise the Program information
Row instruction is not executed. If more than 256 bytes data are sent to a device, the address counter can not
roll over.
After CE# pin is driven High, the self-timed page program cycle (whose duration is tpotp) is initiated. While the
program OTP cycle is in progress, the status register may be read to check the value of the write in progress
(WIP) bit. The write in progress (WIP) bit is 1 during the self-timed program cycle, and it is 0 when it is
completed. At some unspecified time before the cycle is complete, the write enable latch (WEL) bit is reset.
CE#
0
1
2
3
4
5
6
7
8
9
10
11
28
29
30
31
2
1
0
...
SCK
SI
INSTRUCTION = 1011 0001b
23
22
MSB
...
21
24-bit address
CE#
32
33
34
35
36
37
38
39
40
41
42
43
...
SCK
MSB
SI
7
6
5
4
3
2
1
0
Data Byte 1
7
6
5
Data Byte 2
...
Data Byte n
Note: 1 n 256
Figure 30. Program information Raw Sequence
Note: 1. The SIR address is from 000000h to 0000FFh.
2. The SIR protection bit is in the address 000100h.
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IS25LQ020/040
DEVICE OPERATION (CONTINUED)
To lock the OTP memory:
Bit 0 of the OTP control byte, that is byte 256, is used to permanently lock the OTP memory array.
When bit 0 of byte 256 = ’1’, the 256 bytes of the OTP memory array can be programmed.
When bit 0 of byte 256 = ‘0’, the 256 bytes of the OTP memory array are read-only and
cannot be programmed anymore.
Once a bit of the OTP memory has been programmed to ‘0’, it can no longer be set to ‘1’.
Therefore, as soon as bit 0 of byte 256 (control byte) is set to ‘0’, the 256 bytes of the OTP
memory array become read-only in a permanent way.
Any program OTP (POTP) instruction issued while an erase, program or write cycle is in
progress is rejected without having any effect on the cycle that is in progress
OTP control byte
Byte1 Byte2
Byte255Byte256
X
X
X
X
X
Bit 1~bit 7 do not care
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X
X
Bit 0
When bit 0 = 0
the 256 OTP bytes
become read only
33
IS25LQ020/040
DEVICE OPERATION (CONTINUED)
Read Security Information Row (RSIR)
The RSIR instruction read the security information Row. There is no rollover mechanism with the read OTP
(ROTP) instruction. This means that the read OTP (ROTP) instruction must be sent with a maximum of 256
th
th
bytes to read, since once the 256 byte has been read, the same (256 ) byte keeps being read on the SO pin.
Fig 33. Read Security information Row instruction
CE#
0
2
1
3
4
5
6
8
7
9
10
11
28
29
30
31
2
1
0
32
33
7
6
34
35
36
37
38 39
4
3
2
1
...
SCK
SI
INSTRUCTION = 0100 1011b
23
22
MSB
21
...
24-bit address
SO
5
0
Data Out0
CE#
40
41
42
43
44
45
46
47
...
SCK
SI
MSB
SO
7
6
5
4
3
2
1
0
Data outpur 1
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
11/13/2012
7
6
5
Data output 2
...
Data output N
34
IS25LQ020/040
DEVICE OPERATION (CONTINUED)
The device allow the interruption of Sector-Erase, Block-Erase or Page-Program operations and conduct other
operations.
To enter the suspend/ resume mode: issuing 75h/B0h for suspend; 7Ah/30h for resume
Suspend to suspend ready timing: 20us.
Resume to another suspend timing: 1ms.
*Note: It needs 500ns delay time from write command to suspend command
After erase suspend, WEL bit will be clear, only read related and resume command can be accepted.
(03h, 0Bh, BBh, EBh, 05h, ABh, 9Fh, 90h, 4Bh)
To execute a Program/Erase Suspend operation, the host drives CE# low, sends the Program/Erase Suspend
command cycle (75H/B0h), then drives CE# high. The device will not accept another command until it is ready.
To determine when the device will accept a new command, poll the WIP bit in the Status register or wait TWS.
Program suspend allows the interruption of all program operations.
After program suspend, WEL bit will be cleared, only read related and resume command can be accepted.
(03h, 0Bh, BBh, EBh, 05h, ABh, 9Fh, 90h, 4Bh)
To execute a Program/Erase Suspend operation, the host drives CE# low, sends the Program/Erase Suspend
command cycle (75H/B0h), then drives CE# high. The device will not accept another command until it is ready.
To determine when the device will accept a new command, poll the WIP bit in the Status register or wait TWS.
Program/Erase Resume restarts a Program/Erase command that was suspended. To execute a Program/Erase
Resume operation, the host drives CE# low, sends the Program/Erase Resume command cycle (7AH/30h),
then drives CE# high. To determine if the internal, self-timed Write operation completed, poll the WIP bit in the
Status register, or wait the specified time TSE, TBE or TPP for Sector- Erase, Block-Erase, or Page-Programming,
respectively. The total write time before suspend and after resume will not exceed the uninterrupted write times
TSE, TBE or TPP.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
11/13/2012
35
IS25LQ020/040
ABSOLUTE MAXIMUM RATINGS (1)
o
Storage Temperature
Standard Package
Lead-free Package
Input Voltage with Respect to Ground on All Pins (2)
All Output Voltage with Respect to Ground
VCC (2)
Surface Mount Lead Soldering Temperature
o
-55 C to +125 C
o
240 C 3 Seconds
o
260 C 3 Seconds
-0.5 V to VCC + 0.5 V
-0.5 V to VCC + 0.5 V
-0.5 V to +6.0 V
Notes:
1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only. The functional operation of the device conditions that exceed those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
condition for extended periods may affect device reliability.
2. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may
overshoot VCC by + 2.0 V for a period of time not to exceed 20 ns. Minimum DC voltage on input or I/O pins is
-0.5 V. During voltage transitions, input or I/O pins may undershoot GND by -2.0 V for a period of time not to
exceed 20 ns.
DC AND AC OPERATING RANGE
Part Number
IS25LQ020/040
Operating Temperature (Extended Grade)
Operating Temperature (Industrial Grade)
-40 C to 105 C
o
o
-40 C to 85 C
Operating Temperature (Automotive, A1 Grade)
Operating Temperature (Automotive, A2 Grade)
Operating Temperature (Automotive, A3 Grade)
Vcc Power Supply
-40 C to 85 C
o
o
-40 C to 105 C
o
o
-40 C to 125 C
2.3 V – 3.6 V
o
o
o
o
DC CHARACTERISTICS
Applicable over recommended operating range from:
VCC = 2.3 V to 3.6 V (unless otherwise noted).
Symbol
Parameter
Condition
ICC1
ICC2
ISB1
Vcc Active Read Current
Vcc Program/Erase Current
Vcc Standby Current CMOS
VCC = 3.6V at 33 MHz, SO = Open
VCC = 3.6V at 33 MHz, SO = Open
VCC = 3.6V, CE# = VCC
ISB3
ILI
ILO
VIL
VIH
VOL
Vcc Standby Current TTL
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
VCC = 3.6V, CE# = VIH to VCC
VIN = 0V to VCC
o
o
VIN = 0V to VCC, TAC = 0 C to 130 C
VOH
Output High Voltage
Min
-0.5
0.7VCC
2.3V < VCC < 3.6V
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
11/13/2012
IOL = 2.1 mA
IOH = -100 A
Ty
p
10
15
10
Max
Units
12
20
30
mA
mA
3
1
1
0.3Vcc
VCC + 0.3
0.45
A
mA
A
A
V
V
V
VCC – 0.2
V
36
IS25LQ020/040
AC CHARACTERISTICS
Applicable over recommended operating range from VCC = 2.3 V to 3.6 V
CL = 1 TTL Gate and 30 pF (unless otherwise noted).
Symbol
Parameter
fCT
fC
tRI
tFI
Clock Frequency for fast read mode
Clock Frequency for read mode
Input Rise Time
Input Fall Time
0
0
tCKH
tCKL
tCEH
tCS
tCH
tDS
SCK High Time
SCK Low Time
CE# High Time
CE# Setup Time
CE# Hold Time
Data In Setup Time
4
4
25
10
5
2
ns
ns
ns
ns
ns
ns
tDH
tHS
tHD
tV
tOH
tLZ
Data in Hold Time
Hold Setup Time
Hold Time
Output Valid
Output Hold Time Normal Mode
Hold to Output Low Z
2
15
15
200
ns
ns
ns
ns
ns
ns
tHZ
tDIS
Hold to Output High Z
Output Disable Time
200
100
ns
ns
50
0.25
0.5
150
1
1.3
ms
s
s
1
2.5
s
0.5
0.7
3
3
15
20
ms
tEC
Sector Erase Time
Block Erase Time(64Kbyte)
Chip Erase Time (2Mb)
Chip Erase Time (4Mb)
tPP
tres1
tdp
tw
Tws
Page Program Time
Write Status Register time
Suspend time
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
11/13/2012
Min
Typ
Max
Units
104
33
8
8
MHz
MHz
ns
ns
8
0
10
s
s
ms
us
37
IS25LQ020/040
AC CHARACTERISTICS (CONTINUED)
SERIAL INPUT/OUTPUT TIMING (1)
Note: 1. For SPI Mode 0 (0,0)
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
11/13/2012
38
IS25LQ020/040
AC CHARACTERISTICS (CONTINUED)
HOLD TIMING
PIN CAPACITANCE (f = 1 MHz, T = 25°C )
CIN
COUT
Typ
Max
Units
Conditions
4
8
6
12
pF
pF
VIN = 0 V
VOUT = 0 V
Note: These parameters are characterized but not 100% tested.
OUTPUT TEST LOAD
INPUT TEST WAVEFORMS
AND MEASUREMENT LEVEL
30pf
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
11/13/2012
39
IS25LQ020/040
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must not be
selected (CE# must follow the voltage applied on Vcc)
until Vcc reaches the correct value:
- Vcc(min) at Power-up, and then for a further delay of
tVCE
- Vss at Power-down
Usually a simple pull-up resistor on CE# can be used
to insure safe and proper Power-up and Power-down.
To avoid data corruption and inadvertent write
operations during power up, a Power On Reset (POR)
circuit is included. The logic inside the device is held
reset while Vcc is less than the POR threshold value
(Vwi) during power up, the device does not respond to
any instruction until a time delay of tPUW has elapsed
after the moment that Vcc rised above the VWI
threshold. However, the correct operation of the device
is not guaranteed if, by this time, Vcc is still below
Vcc(min). No Write Status Register, Program or Erase
instructions should be sent until the later of:
- tPUW after Vcc passed the VWI threshold
- tVCE after Vcc passed the Vcc(min) level
At Power-up, the device is in the following state:
- The device is in the Standby mode
- The Write Enable Latch (WEL) bit is reset
At Power-down, when Vcc drops from the operating
voltage, to below the Vwi, all write operations are
disabled
and the device does not respond to any write
instruction.
Vcc
Vcc(max)
All Write Commands are Rejected
Chip Selection Not Allowed
Vcc(min)
Reset State
tVCE
V (write inhibit)
Read Access Allowed
Device fully accessible
tPUW
Time
Symbol
Parameter
tVCE
*1
Vcc(min) to CE# Low
tPUW
*1
Power-Up time delay to Write instruction
VWI*1
Write Inhibit Voltage
Note : *1. These parameters are characterized only.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
11/13/2012
Min.
Max.
150
10
1
2.0
2.4
Unit
us
10
ms
V
40
IS25LQ020/040
PROGRAM/ERASE PERFORMANCE
Parameter
Unit
Typ
Max
Remarks
Sector Erase Time
Block Erase Time (64KB)
ms
ms
50
250
150
1000
From writing erase command to erase completion
From writing erase command to erase completion
Chip Erase Time (2Mb)
s
0.5
1.3
From writing erase command to erase completion
Chip Erase Time (4Mb)
s
1
2.5
From writing erase command to erase completion
Page Programming Time
ms
0.5
0.7
From writing program command to program completion
Byte Program
us
8
25
Note: These parameters are characterized and are not 100% tested.
RELIABILITY CHARACTERISTICS
Parameter
Endurance
Data Retention
ESD – Human Body Model
ESD – Machine Model
Latch-Up
Min
100,000
20
2,000
200
100 + ICC1
Typ
Unit
Cycles
Years
Volts
Volts
mA
Test Method
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard A114
JEDEC Standard A115
JEDEC Standard 78
Note: These parameters are characterized and are not 100% tested.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
11/13/2012
41
IS25LQ020/040
PACKAGE TYPE INFORMATION
JN
8-Pin JEDEC 150mil Broad Small Outline Integrated Circuit (SOIC) Package
(measure in millimeters)
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
11/13/2012
42
IS25LQ020/040
PACKAGE TYPE INFORMATION (CONTINUED)
JB
8-Pin JEDEC 208mil Broad Small Outline Integrated Circuit (SOIC) Package
(measure in millimeters)
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
11/13/2012
43
IS25LQ020/040
PACKAGE TYPE INFORMATION (CONTINUED)
JK
8-Contact Ulta-Thin Small Outline No-Lead (WSON) Package (measure in millimeters)
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
11/13/2012
44
IS25LQ020/040
PACKAGE TYPE INFORMATION (CONTINUED)
JV
8-pin VVSOP 150mil
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
11/13/2012
45
IS25LQ020/040
PACKAGE TYPE INFORMATION (CONTINUED)
JA
8-pin 300mil wide body, Plastic Dual In-Line Package PDIP (measure in millimeters)
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
11/13/2012
46
IS25LQ020/040
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
11/13/2012
47
IS25LQ020/040
Appendix1: Safe Guard function
Safe Guard function is a security function for customer to protect by sector (4Kbyte).
Every sector has one bit register to decide it will under safe guard protect or not. (“0”means protect and “1”
means not protect by safe guard.)
IS25LQ020 (sector 0~sector 63)
IS25LQ040 (sector 0~sector 127)
Mapping table for safe guard register
Sector 0
Sector 1
Sector 2
Sector 3
Sector 4
Sector 5
Sector 6
Sector 7
D6
1
1
1
1
1
1
1
0
D5
1
1
1
1
1
1
0
1
D4
1
1
1
1
1
0
1
1
D3
1
1
1
1
0
1
1
1
D2
1
1
1
0
1
1
1
1
D1
1
1
0
1
1
1
1
1
D0
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
…
…
…
…
…
…
…
…
00Fh
00Fh
00Fh
00Fh
00Fh
00Fh
00Fh
00Fh
D7
…
…
…
…
…
…
…
…
006h
006h
006h
006h
006h
006h
006h
006h
…
…
Sector 120
Sector 121
Sector 122
Sector 123
Sector 124
Sector 125
Sector 126
Sector 127
…
…
Sector 56
Sector 57
Sector 58
Sector 59
Sector 60
Sector 61
Sector 62
Sector 63
Address
000h
000h
000h
000h
000h
000h
000h
000h
1
1
1
1
1
1
1
0
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
11/13/2012
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
48
IS25LQ020/040
Read Safe Guard register
The READ Safe Guard instruction code is transmitted via the SlO line, followed by three address bytes (A23 - A0) of
the first register location to be read. The first byte data (D7 - D0) addressed is then shifted out on the SO line, MSb
first. The address is automatically incremented after each byte of data is shifted out. The read operation can be
terminated at any time by driving CE# high (VIH) after the data comes out.
CS
1
2
7 8 9 10
23 24 25 26
31 32 33 34
39 40 41 42
47 48
SCK
SI
2Fh
A23-A0
SO
1st byte
2nd byte
D7-D0
D7-D0
Fig a. Timing waveform of Read Safe guard register
Erase Safe Guard register
If we want to erase the safe guard register to let the flash into unprotect status, it needs five continuous
instructions. If any instruction is wrong, the erase command will be ignored. Erase wait time follow product erase
timing spec.
Fig b. shows the complete steps for Erase safe guard register.
Program Safe Guard register
If we want to erase the safe guard register to let the flash into unprotect status, it needs five continuous
instructions. If any instruction is wrong, the program command will be ignored. The Program safe guard
instruction allows up to 256 bytes data to be programmed into memory in a single operation. Program wait time
follow product program timing spec.
Fig c. shows the complete steps for program safe guard register.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
11/13/2012
49
IS25LQ020/040
Sector Protection Mode Erase
CS
1
2
7 8
9 10
31 32
SCK
SI
55h
A23-A0
CS
1
2
7 8
9 10
31 32
SCK
SI
AAh
A23-A0
CS
1
2
7 8
9 10
31 32
SCK
SI
80h
A23-A0
CS
1
2
7 8
9 10
31 32
SCK
SI
AAh
A23-A0
CS
1
2
7 8
SCK
SI
2Bh
Fig b. Erase safe guard register
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
11/13/2012
50
IS25LQ020/040
CS
1
2
7 8
9 10
31 32
SCK
SI
55h
A23-A0
CS
1
2
7 8
9 10
31 32
SCK
SI
AAh
A23-A0
CS
1
2
7 8
9 10
31 32
SCK
SI
A0h
A23-A0
CS
1
2
7 8
9 10
31 32
SCK
SI
55h
A23-A0
CS
1
2
7 8 9 10
31 32 33 34
39 40
41 42
47 48
SCK
st
SI
23h
A23-A0
nd
1 byte
2
byte
D7-D0
D7-D0
Fig c. program safe guard register
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
11/13/2012
51
IS25LQ020/040
Appendix2: Sector Unlock function
Instruction Name
Hex
Code
26h
24h
SECT_UNLOCK
SECT_LOCK
Operation
Command
Cycle
4 Bytes
1 Byte
Sector unlock
Sector lock
Maximum
Frequency
100 MHz
100 MHz
SEC_UNLOCK COMMAND OPERATION
The Sector unlock command allows the user to
select a specific sector to allow program and erase
operations. This instruction is effective when the
blocks are designated as write-protected through
the BP0, BP1, BP2 and BP3 bits in the status
register. Only one sector can be enabled at any
time. To enable a different sector, a previously
enabled sector must be disabled by executing a
Sector Lock command. The instruction code is
followed by a 24-bit address specifying the target
sector, but A0 through A11 are not decoded. The
remaining sectors within the same block remain in
read-only mode.
Figure d. Sector Unlock Sequence
Sector unlock
CS
1
2
7 8
1
2
7 8 9
10
15 16 17 18
23 24 25 26
31 32
SCK
SI
06h
26h
A23-A16
A15-A8
A7-A0
In the sector unlock procedure, [A11:A0] needs equal to “0”, unlock procedure is
completed, otherwise chip will regard it as illegal command.
Note: 1.If the clock number will not match 8 clocks(command)+ 24 clocks (address), it will be ignored.
2.It must be executed write enable (06h) before sector unlock instructions.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
11/13/2012
52
IS25LQ020/040
SECT_LOCK COMMAND OPERATION
The Sector Lock command reverses the function of
the Sector Unlock command. The instruction code
does not require an address to be specified, as only
one sector can be enabled at a time. The remaining
sectors within the same block remain in read-only
mode.
Figure e. Sector Lock Sequence
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
11/13/2012
53
IS25LQ020/040
ORDERING INFORMATION:
Density
Frequency
(MHz)
2M
104
4M
104
Order Part Number
Package
IS25LQ020/040-JBLE
IS25LQ020/040-JNLE
IS25LQ020/040-JKLE
IS25LQ020/040-JALE
IS25LQ020/040-JVLE
IS25LQ020/040-JBLI
IS25LQ020/040-JNLI
IS25LQ020/040-JKLI
IS25LQ020/040-JALI
IS25LQ020/040-JVLI
IS25LQ020/040-JBLA1
IS25LQ020/040-JNLA1
IS25LQ020/040-JKLA1
IS25LQ020/040-JALA1
IS25LQ020/040-JVLA1
IS25LQ020/040-JBLA2
IS25LQ020/040-JNLA2
IS25LQ020/040-JKLA2
IS25LQ020/040-JALA2
IS25LQ020/040-JVLA2
IS25LQ020/040-JBLA3
IS25LQ020/040-JNLA3
IS25LQ020/040-JKLA3
IS25LQ020/040-JALA3
IS25LQ020/040-JVLA3
IS25LQ020/040-JBLE
IS25LQ020/040-JNLE
IS25LQ020/040-JKLE
IS25LQ020/040-JALE
IS25LQ020/040-JVLE
IS25LQ020/040-JBLI
IS25LQ020/040-JNLI
IS25LQ020/040-JKLI
IS25LQ020/040-JALI
IS25LQ020/040-JVLI
IS25LQ020/040-JBLA1
IS25LQ020/040-JNLA1
IS25LQ020/040-JKLA1
IS25LQ020/040-JALA1
IS25LQ020/040-JVLA1
IS25LQ020/040-JBLA2
IS25LQ020/040-JNLA2
IS25LQ020/040-JKLA2
IS25LQ020/040-JALA2
IS25LQ020/040-JVLA2
IS25LQ020/040-JBLA3
IS25LQ020/040-JNLA3
IS25LQ020/040-JKLA3
IS25LQ020/040-JALA3
IS25LQ020/040-JVLA3
8-pin SOIC 208-mil
8-pin SOIC 150mil
8-pin WSON
8-pin PDIP 300mil
8-pin VVSOP 150-mil
8-pin SOIC 208-mil
8-pin SOIC 150mil
8-pin WSON
8-pin PDIP 300mil
8-pin VVSOP 150-mil
8-pin SOIC 208-mil
8-pin SOIC 150mil
8-pin WSON
8-pin PDIP 300mil
8-pin VVSOP 150-mil
8-pin SOIC 208-mil
8-pin SOIC 150mil
8-pin WSON
8-pin PDIP 300mil
8-pin VVSOP 150-mil
8-pin SOIC 208-mil
8-pin SOIC 150mil
8-pin WSON
8-pin PDIP 300mil
8-pin VVSOP 150-mil
8-pin SOIC 208-mil
8-pin SOIC 150mil
8-pin WSON
8-pin PDIP 300mil
8-pin VVSOP 150-mil
8-pin SOIC 208-mil
8-pin SOIC 150mil
8-pin WSON
8-pin PDIP 300mil
8-pin VVSOP 150-mil
8-pin SOIC 208-mil
8-pin SOIC 150mil
8-pin WSON
8-pin PDIP 300mil
8-pin VVSOP 150-mil
8-pin SOIC 208-mil
8-pin SOIC 150mil
8-pin WSON
8-pin PDIP 300mil
8-pin VVSOP 150-mil
8-pin SOIC 208-mil
8-pin SOIC 150mil
8-pin WSON
8-pin PDIP 300mil
8-pin VVSOP 150-mil
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
11/13/2012
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