IS25LQ032B
IS25LQ016B
IS25LQ080B
32/16/8Mb
3V QUAD SERIAL FLASH MEMORY WITH
MULTI-I/O SPI
DATA SHEET
IS25LQ032B/016B/080B
32/16/8Mb
3V QUAD SERIAL FLASH MEMORY MULTI-I/O SPI
FEATURES
Industry Standard Serial Interface
- IS25LQ032B: 32Mbit/4Mbyte
- IS25LQ016B: 16Mbit/2Mbyte
- IS25LQ080B: 8Mbit/1Mbyte
- 256-bytes per Programmable Page Standard
- Standard SPI/Dual/Quad Multi-I/O SPI
- Supports Serial Flash Discoverable Parameters
(SFDP)
High Performance Serial Flash (SPI)
- 104 MHz SPI/Dual/Quad Multi-I/O SPI
- 416 MHz equivalent Quad SPI
- 52MB/S Continuous Data Throughput
- Supports SPI Modes 0 and 3
- More than 100,000 erase/program cycles
- More than 20-year data retention
Efficient Read and Program modes
- Low Instruction Overhead Operations
- Continuous data read with Byte Wrap around
- Allows XIP operations (execute in place)
- Outperforms X16 Parallel Flash
Flexible & Cost Efficient Memory Architecture
- Uniform 4 Kbyte Sectors or 32/64 Kbyte Blocks
- Flexible 4, 32, 64 Kbytes, or Chip Erase
- Standard Page Program 1 to 256 bytes
- Program/Erase Suspend and Resume
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Low Power with Wide Temp. Ranges
- Single 2.3V to 3.6V Voltage Supply
- 10 mA Active Read Current
- 8 µA Standby Current
- 5 µA Deep Power Down
- Temp Grades:
Extended: -40°C to +105°C
Auto Grade A3: -40°C to +125°C
Note: Extended+ should not be used for Automotive.
Advanced Security Protection
- Software and Hardware Write Protection
- 4x256-Byte dedicated security area with
OTP user-lockable bits.
- 128 bit Unique ID for each device (Call Factory)
Industry Standard Pin-out & Pb-Free Packages1
- M = 16-pin SOIC 300mil
- B = 8-pin SOIC 208mil
- N = 8-pin SOIC 150mil
- F = 8-pin VSOP 208mil
- K = 8-contact WSON 6x5mm
- L = 8-contact WSON 8x6mm
- T = 8-contact USON 4x3mm
- G = 24-ball TFBGA 6x8mm 4x6 (Call Factory)
- H = 24-ball TFBGA 6x8mm 5x5 (Call Factory)
- KGD (Call Factory)
Note1: IS25LQ080B (not available in M, L, G, H)
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IS25LQ032B/016B/080B
GENERAL DESCRIPTION
The IS25LQ032B/016B/080B (32/16/8M-bit) Serial Flash memory offers a storage solution with flexibility and
performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” is for systems that have limited
space, pins, and power. The device is accessed through a 4-wire SPI Interface consisting of a Serial Data Input (SI),
Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins, which also serve as multi-function I/O pins
in Dual and Quad modes (see pin descriptions). The IS25xQ series of Flash is ideal for code shadowing to RAM, execute
in place (XIP) operations, and storing non-volatile data.
The memory array is organized into programmable pages of 256-bytes each. The device supports page program mode
where 1 to 256 bytes of data can be programmed into the memory with one command. Pages can be erased in groups
of 4Kbyte sectors, 32Kbyte blocks, 64Kbyte blocks, and/or the entire chip. The uniform sectors and blocks allow greater
flexibility for a variety of applications requiring solid data retention.
The device supports the standard Serial Peripheral Interface (SPI), Dual/Quad output (SPI), and Dual/Quad I/O (SPI).
Clock frequencies of up to 104MHz for all read modes allow for equivalent clock rates of up to 416MHz (104MHz x 4)
which equates to 52Mbytes/S of throughput. These transfer rates can outperform 16-bit Parallel Flash memories
allowing for efficient memory access for a XIP (execute in place) operation. The device is manufactured using industry
leading non-volatile memory technology and offered in industry standard lead-free packages. See Ordering Information
for the density and package combinations available.
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IS25LQ032B/016B/080B
TABLE OF CONTENTS
FEATURES .......................................................................................................................................................... 2
GENERAL DESCRIPTION .................................................................................................................................. 3
TABLE OF CONTENTS ....................................................................................................................................... 4
1.
PIN CONFIGURATION ................................................................................................................................. 6
2.
PIN DESCRIPTIONS .................................................................................................................................... 8
3.
BLOCK DIAGRAM ........................................................................................................................................ 9
4.
SPI MODES DESCRIPTION ...................................................................................................................... 10
5.
SYSTEM CONFIGURATION ...................................................................................................................... 12
5.1 BLOCK/SECTOR ADDRESSES .......................................................................................................... 13
6.
REGISTERS ............................................................................................................................................... 14
6.1. STATUS REGISTER ........................................................................................................................... 14
6.2. FUNCTION REGISTER ....................................................................................................................... 17
7.
PROTECTION MODE................................................................................................................................. 18
7.1 HARDWARE WRITE PROTECTION.................................................................................................... 18
7.2 SOFTWARE WRITE PROTECTION .................................................................................................... 18
8.
DEVICE OPERATION ................................................................................................................................ 19
8.1 READ DATA OPERATION (RD, 03h) .................................................................................................. 20
8.2 FAST READ DATA OPERATION (FR, 0Bh) ........................................................................................ 22
8.3 HOLD OPERATION .............................................................................................................................. 23
8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBh) ........................................................................... 23
8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh) .................................................................. 26
8.6 FAST READ QUAD OUTPUT (FRQO, 6Bh) ........................................................................................ 28
8.7 FAST READ QUAD I/O OPERATION (FRQIO, EBh) .......................................................................... 30
8.8 PAGE PROGRAM OPERATION (PP, 02h) .......................................................................................... 33
8.9 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h/38h) ........................................................ 34
8.10 ERASE OPERATION ......................................................................................................................... 35
8.11 SECTOR ERASE OPERATION (SER, D7h/20h) ............................................................................... 35
8.12 BLOCK ERASE OPERATION (BER32K:52h, BER64K:D8h) ............................................................ 36
8.13 CHIP ERASE OPERATION (CER, C7h/60h) ..................................................................................... 37
8.14 WRITE ENABLE OPERATION (WREN, 06h) .................................................................................... 38
8.15 WRITE DISABLE OPERATION (WRDI, 04h) ..................................................................................... 38
8.16 READ STATUS REGISTER OPERATION (RDSR, 05h) ................................................................... 39
8.17 WRITE STATUS REGISTER OPERATION (WRSR, 01h) ................................................................. 39
8.18 READ FUNCTION REGISTER OPERATION (RDFR, 48h) ............................................................... 40
8.19 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h)............................................................. 40
8.20 PROGRAM/ERASE SUSPEND & RESUME ...................................................................................... 41
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8.21 DEEP POWER DOWN (DP, B9h) ...................................................................................................... 43
8.22 RELEASE DEEP POWER DOWN (RDPD, ABh) ............................................................................... 44
8.23 READ PRODUCT IDENTIFICATION (RDID, ABh) ............................................................................ 45
8.24 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9Fh) ........................... 46
8.25 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90h) ........................ 47
8.26 READ UNIQUE ID NUMBER (RDUID, 4Bh) ...................................................................................... 48
8.27 READ SFDP OPERATION (RDSFDP, 5Ah) ...................................................................................... 49
8.28 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h) ............................ 50
8.29 SECURITY INFORMATION ROW (OTP AREA) ................................................................................ 51
8.30 INFORMATION ROW PROGRAM OPERATION (IRP, 62h) ............................................................. 51
8.31 INFORMATION ROW READ OPERATION (IRRD, 68h) ................................................................... 53
8.32 SECTOR LOCK/UNLOCK FUNCTIONS ............................................................................................ 54
9.
ELECTRICAL CHARACTERISTICS........................................................................................................... 56
9.1 ABSOLUTE MAXIMUM RATINGS (1) ................................................................................................... 56
9.2 OPERATING RANGE ........................................................................................................................... 56
9.3 DC CHARACTERISTICS ...................................................................................................................... 57
9.4 AC MEASUREMENT CONDITIONS .................................................................................................... 58
9.5 PIN CAPACITANCE (TA = 25°C, VCC=3V , 1MHz) ............................................................................ 58
9.6 AC CHARACTERISTICS ...................................................................................................................... 59
9.7 SERIAL INPUT/OUTPUT TIMING ........................................................................................................ 60
9.8 POWER-UP AND POWER-DOWN ...................................................................................................... 61
9.9 PROGRAM/ERASE PERFORMANCE ................................................................................................. 62
9.10 RELIABILITY CHARACTERISTICS ................................................................................................... 62
10.
PACKAGE TYPE INFORMATION ......................................................................................................... 63
10.1 16-Pin JEDEC 300mil Small Outline Integrated Circuit (SOIC) Package (M) .................................... 63
10.2 8-Pin JEDEC 208mil Broad Small Outline Integrated Circuit (SOIC) Package (B) ............................ 64
10.3 8-Pin JEDEC 150mil Broad Small Outline Integrated Circuit (SOIC) Package (N) ............................ 65
10.4 8-Pin 208mil VSOP Package (F) ........................................................................................................ 66
10.5 8-Contact Ultra-Thin Small Outline No-Lead (WSON) Package 6x5mm (K)...................................... 67
10.6 8-Contact Ultra-Thin Small Outline No-Lead (WSON) Package 8x6mm (L) ...................................... 68
10.7 24-Ball Thin Profile Fine Pitch BGA 6x8mm 4x6 array (G)................................................................. 69
10.8 8-Contact Ultra-Thin Small Outline No-Lead (USON) Package 4x3mm (T)....................................... 70
10.9 24-Ball Thin Profile Fine Pitch BGA 6x8mm 5x5 array (H) ................................................................. 71
11.
ORDERING INFORMATION - Valid Part Numbers ............................................................................... 72
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IS25LQ032B/016B/080B
1. PIN CONFIGURATION
CE#
1
SO (IO1)
2
Vcc
8
7
CE#
1
8 Vcc
SO (IO1)
2
7 HOLD# (IO3)
WP# (IO2)
3
6 SCK
GND
4
5 SI (IO0)
HOLD# (IO3)
WP# (IO2)
3
6
SCK
GND
4
5
SI (IO0)
8-pin WSON 6x5mm (Package: K)
8-pin WSON 8x6mm (Package: L)
8-pin USON 4x3mm (Package: T)
8-pin SOIC 208mil (Package: B)
8-pin SOIC 150mil (Package: N)
8-pin VSOP 208mil (Package: F)
HOLD# (IO3)
1
16
SCK
Vcc
2
15
SI (IO0)
NC
3
14
NC
NC
4
13
NC
NC
5
12
NC
NC
6
11
NC
CE#
7
10
GND
SO (IO1)
8
9
WP# (IO2)
16-pin SOIC 300mil (Package: M)
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IS25LQ032B/016B/080B
Top View, Balls Facing Down
Top View, Balls Facing Down
Top View, Balls Facing Down
A1
A2
A3
A4
NC
NC
NC
NC
B1
B2
B3
B4
NC
SCK
GND
VCC
C1
C2
C3
C4
NC
CE#
NC
WP#(IO2)
D1
D2
D3
D4
NC
SO(IO1)
SI(IO0) HOLD# (IO3)
E1
E2
E3
E4
NC
NC
NC
NC
F1
F2
F3
F4
NC
NC
NC
NC
24-ball TFBGA 4 x 6 ball array (Package: G)
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A2
A3
A4
A5
NC
NC
NC
NC
B1
B2
B3
B4
B5
NC
SCK
GND
VCC
NC
C1
C2
C3
C4
C5
NC
CE#
NC
WP#(IO2)
NC
D3
D4
D5
D1
D2
NC
SO(IO1)
SI(IO0) HOLD# (IO3) NC
E1
E2
E3
E4
E5
NC
NC
NC
NC
NC
24-ball TFBGA 5 x 5 ball array (Package: H)
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IS25LQ032B/016B/080B
2. PIN DESCRIPTIONS
SYMBOL
TYPE
DESCRIPTION
Chip Enable: The Chip Enable (CE#) pin enables and disables the devices
operation. When CE# is high the device is deselected and output pins are in a high
impedance state. When deselected the devices non-critical internal circuitry power
down to allow minimal levels of power consumption while in a standby state.
CE#
INPUT
When CE# is pulled low the device will be selected and brought out of standby mode.
The device is considered active and instructions can be written to, data read, and
written to the device. After power-up, CE# must transition from high to low before a
new instruction will be accepted.
Keeping CE# in a high state deselects the device and switches it into its low power
state. Data will not be accepted when CE# is high.
SI (IO0),
SO (IO1)
INPUT/OUTPUT
Serial Data Input, Serial Output, and IOs (SI, SO, IO0, and IO1):
This device supports standard SPI, Dual SPI, and Quad SPI operation. Standard
SPI instructions use the unidirectional SI (Serial Input) pin to write instructions,
addresses, or data to the device on the rising edge of the Serial Clock (SCK).
Standard SPI also uses the unidirectional SO (Serial Output) to read data or status
from the device on the falling edge of the serial clock (SCK).
In Dual and Quad SPI mode, SI and SO become bidirectional IO pins to write
instructions, addresses or data to the device on the rising edge of the Serial Clock
(SCK) and read data or status from the device on the falling edge of SCK. Quad SPI
instructions use the WP# and HOLD# pins as IO2 and IO3 respectively.
WP# (IO2)
INPUT/OUTPUT
Write Protect/Serial Data IO (IO2): The WP# pin protects the Status Register from
being written in conjunction with the SRWD bit. When the SRWD is set to “1” and
the WP# is pulled low, the Status Register bits (SRWD, QE, BP3, BP2, BP1, BP0)
are write-protected and vice-versa for WP# high. When the SRWD is set to “0”, the
Status Register is not write-protected regardless of WP# state.
When the QE bit is set to “1”, the WP# pin (Write Protect) function is not available
since this pin is used for IO2.
Hold/Serial Data IO (IO3): Pauses serial communication by the master device
without resetting the serial sequence. When the QE bit of Status Register is set to
“1”, HOLD# pin is not available since it becomes IO3.
HOLD# (IO3)
INPUT/OUTPUT
The HOLD# pin allows the device to be paused while it is selected. The HOLD# pin
is active low. When HOLD# is in a low state, and CE# is low, the SO pin will be at
high impedance.
Device operation can resume when HOLD# pin is brought to a high state. When the
QE bit of Status Register is set for Quad I/O, the HOLD# pin function is not available
and becomes IO3 for Multi-I/O SPI mode.
SCK
INPUT
Vcc
POWER
GND
GROUND
NC
Unused
Serial Data Clock: Synchronized Clock for input and output timing operations.
Power: Device Core Power Supply
Ground: Connect to ground when referenced to Vcc
NC: Pins labeled “NC” stand for “No Connect” and should be left uncommitted.
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IS25LQ032B/016B/080B
3. BLOCK DIAGRAM
Control Logic
High Voltage Generator
Status
Register
I/O Buffers and
Data Latches
256 Bytes
Page Buffer
SCK
WP#
(IO2)
SI
(IO0)
SO
(IO1)
Serial Peripheral Interface
CE#
X-Decoder
HOLD#
(IO3)
Y-Decoder
Memory Array
Address Latch &
Counter
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IS25LQ032B/016B/080B
4. SPI MODES DESCRIPTION
Multiple IS25LQ032B/016B/080B devices can be connected on the SPI serial bus and controlled by a SPI Master,
i.e. microcontroller, as shown in Figure 4.1 the devices support either of two SPI modes:
Mode 0 (0, 0)
Mode 3 (1, 1)
The difference between these two modes is the clock polarity. When the SPI master is in stand-by mode, the
serial clock remains at “0” (SCK = 0) for Mode 0 and the clock remains at “1” (SCK = 1) for Mode 3. Please refer
to Figure 4.2 for SPI mode. In SPI mode, the input data is latched on the rising edge of Serial Clock (SCK), and
the output data is available from the falling edge of SCK.
Figure 4.1 Connection Diagram among SPI Master and SPI Slaves (Memory Devices)
SDO
SPI interface with
(0,0) or (1,1)
SDI
SCK
SCK SO
SI
SCK SO
SI
SCK SO
SI
SPI Master
(i.e. Microcontroller)
CS3
CS2
SPI
Memory
Device
CS1
CE#
SPI
Memory
Device
CE#
WP# HOLD#
SPI
Memory
Device
CE#
WP# HOLD#
WP# HOLD#
Notes:
1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as necessary.
2. SI and SO pins become bidirectional IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3 respectively
during Multi-IO mode.
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IS25LQ032B/016B/080B
Figure 4.2 SPI Mode Support
SCK
Mode 0 (0,0)
SCK
Mode 3 (1,1)
SI
MSB
SO
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IS25LQ032B/016B/080B
5. SYSTEM CONFIGURATION
The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) microcontrollers
or any SPI interface-equipped system controllers.
The memory array is divided into uniform 4 Kbyte sectors or uniform 32/64 Kbyte blocks (a block consists of
eight/sixteen adjacent sectors respectively).
Table 5.1 illustrates the memory map of the device. The Status Register controls how the memory is protected.
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IS25LQ032B/016B/080B
5.1 BLOCK/SECTOR ADDRESSES
Table 5.1 Block/Sector Addresses of IS25LQ032B/016B/080B
Memory Density
Block No.
(64Kbyte)
Block No.
(32Kbyte)
Block 0
Block 0
Block 1
Block 2
Block 1
Block 3
8Mb
Block 4
Block 2
16Mb
Block 5
:
:
Block 30
32Mb
Block 15
Block 31
:
:
Block 62
Block 31
Block 63
:
:
Block 124
Block 62
Block 125
Block 126
Block 63
Block 127
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Sector No.
Sector Size
(Kbyte)
Address Range
Sector 0
4
000000h – 000FFFh
:
:
:
:
:
:
Sector 15
4
00F000h – 00FFFFh
Sector 16
4
010000h – 010FFFh
:
:
:
:
:
:
Sector 31
4
01F000h – 01FFFFh
Sector 32
4
020000h – 020FFFh
:
:
:
:
:
:
Sector 47
4
02F000h – 02FFFFh
:
:
:
Sector 240
4
0F0000h – 0F0FFFh
:
:
:
:
:
:
Sector 255
4
0FF000h – 0FFFFFh
:
:
:
Sector 496
4
1F0000h – 1F0FFFh
:
:
:
:
:
:
Sector 511
4
1FF000h – 1FFFFFh
:
:
:
Sector 992
4
3E0000h – 3E0FFFh
:
:
:
:
:
:
Sector 1007
4
3EF000h – 3EFFFFh
Sector 1008
4
3F0000h – 3F0FFFh
:
:
:
:
:
:
Sector 1023
4
3FF000h – 3FFFFFh
13
IS25LQ032B/016B/080B
6. REGISTERS
The device has two sets of Registers: Status, Function.
6.1. STATUS REGISTER
Status Register Format and Status Register Bit Definitions are described in Tables 6.1 & 6.2.
Table 6.1 Status Register Format
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRWD
QE
BP3
BP2
BP1
BP0
WEL
WIP
0
0
0
0
0
0
0
0
Table 6.2 Status Register Bit Definition
Bit
Name
Bit 0
WIP
Bit 1
WEL
Bit 2
BP0
Bit 3
BP1
Bit 4
BP2
Bit 5
BP3
Bit 6
QE
Bit 7
SRWD
Definition
Write In Progress Bit:
"0" indicates the device is ready(default)
"1" indicates a write cycle is in progress and the device is busy
Write Enable Latch:
"0" indicates the device is not write enabled (default)
"1" indicates the device is write enabled
Block Protection Bit: (See Table 6.4 for details)
"0" indicates the specific blocks are not write-protected (default)
"1" indicates the specific blocks are write-protected
Quad Enable bit:
“0” indicates the Quad output function disable (default)
“1” indicates the Quad output function enable
Status Register Write Disable: (See Table 7.1 for details)
"0" indicates the Status Register is not write-protected (default)
"1" indicates the Status Register is write-protected
Read/Write
Type
R
Volatile
R/W 1
Volatile
R/W
Non-Volatile
R/W
Non-Volatile
R/W
Non-Volatile
Note1: WEL bit can be written by WREN and WRDI commands, but cannot by WRSR command.
The BP0, BP1, BP2, BP3, QE, and SRWD are non-volatile memory cells that can be written by a Write Status
Register (WRSR) instruction. The default value of the BP0, BP1, BP2, BP3, QE, and SRWD bits were set to “0”
at factory. The Status Register can be read by the Read Status Register (RDSR).
The function of Status Register bits are described as follows:
WIP bit: The Write In Progress (WIP) bit is read-only, and can be used to detect the progress or completion of a
program or erase operation. When the WIP bit is “0”, the device is ready for Write Status Register, program or
erase operation. When the WIP bit is “1”, the device is busy.
WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal write enable latch. When the WEL
is “0”, the write enable latch is disabled and all write operations described in Table 6.3 are inhibited. When the
WEL bit is “1”, write operations are allowed. The WEL bit is set by a Write Enable (WREN) instruction. Each write
register, program and erase instruction must be preceded by a WREN instruction. The WEL bit can be reset by a
Write Disable (WRDI) instruction. It will automatically be reset after the completion of any write operation.
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IS25LQ032B/016B/080B
Table 6.3 Instructions requiring WREN instruction ahead
Instructions must be preceded by the WREN instruction
Name
PP
Hex Code
Operation
02h
Serial Input Page Program
PPQ
32h/38h
Quad Input Page Program
SER
D7h/20h
Sector Erase
BER32 (32Kb)
BER64 (64Kb)
CER
52h
Block Erase 32K
D8h
Block Erase 64K
C7h/60h
Chip Erase
WRSR
01h
Write Status Register
WRFR
42h
Write Function Register
IRP
62h
Program Information Row
BP3, BP2, BP1, BP0 bits: The Block Protection (BP3, BP2, BP1 and BP0) bits are used to define the portion of
the memory area to be protected. Refer to Table 6.4 for the Block Write Protection (BP) bit settings. When a
defined combination of BP3, BP2, BP1 and BP0 bits are set, the corresponding memory area is protected. Any
program or erase operation to that area will be inhibited.
Note: A Chip Erase (CER) instruction will be ignored unless all the Block Protection Bits are “0”s.
SRWD bit: The Status Register Write Disable (SRWD) bit operates in conjunction with the Write Protection (WP#)
signal to provide a Hardware Protection Mode. When the SRWD is set to “0”, the Status Register is not writeprotected. When the SRWD is set to “1” and the WP# is pulled low (V IL), the bits of Status Register (SRWD, QE,
BP3, BP2, BP1, BP0) become read-only, and a WRSR instruction will be ignored. If the SRWD is set to “1” and
WP# is pulled high (VIH), the Status Register can be changed by a WRSR instruction.
QE bit: The Quad Enable (QE) is a non-volatile bit in the Status Register that allows quad operation. When the
QE bit is set to “0”, the pin WP# and HOLD# are enabled. When the QE bit is set to “1”, the IO2 and IO3 pins are
enabled.
WARNING: The QE bit must be set to 0 if WP# or HOLD# pin is tied directly to the power supply.
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IS25LQ032B/016B/080B
Table 6.4 Block (64Kbyte) assignment by Block Write Protect (BP) Bits.
Status Register Bits
Protected Memory Area
BP3
BP2
BP1
BP0
32Mb
16Mb
8Mb
0
0
0
0
None
None
None
0
0
0
1
1 block : 63
1 block : 31
1 block : 15
0
0
1
0
2 blocks : 62 - 63
2 blocks : 30 - 31
2 blocks : 14-15
0
0
1
1
4 blocks : 60 - 63
4 blocks : 28 - 31
4 blocks : 12-15
0
1
0
0
8 blocks : 56 - 63
8 blocks : 24 - 31
8 blocks : 8-15
0
1
0
1
16 blocks : 48 - 63
16 blocks : 16 -31
0
1
1
0
32 blocks : 32 - 63
0
1
1
1
1
0
0
0
1
0
0
1
32 blocks : 0 - 31
1
0
1
0
16 blocks : 0 - 15
16 blocks : 0 - 15
1
0
1
1
8 blocks : 0 - 7
8 blocks : 0 - 7
8 blocks : 0 - 7
1
1
0
0
4 blocks 0 - 3
4 blocks 0 - 3
4 blocks 0 - 3
1
1
0
1
2 blocks : 0 - 1
2 blocks : 0 - 1
2 blocks : 0 -1
1
1
1
0
1 block : 0
1 block : 0
1 block : 0
1
1
1
1
None
None
None
All Blocks
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6.2. FUNCTION REGISTER
Function Register Format and Bit definition are described in Table 6.5 and Table 6.6
Table 6.5 Function Register Format
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRL3
IRL2
IRL1
IRL0
ESUS
PSUS
Reserved
Reserved
0
0
0
0
0
0
0
0
Table 6.6 Function Register Bit Definition
Bit
Name
Definition
Bit 0
Reserved
Reserved
Bit 1
Reserved
Bit 2
PSUS
Bit 3
ESUS
Bit 4
IR Lock 0
Bit 5
IR Lock 1
Bit 6
IR Lock 2
Bit 7
IR Lock 3
Reserved
Program suspend bit:
“0” indicates program is not suspend
“1” indicates program is suspend
Erase suspend bit:
"0" indicates Erase is not suspend
"1" indicates Erase is suspend
Lock the Information Row 0:
“0” indicates the Information Row can be programmed
“1” indicates the Information Row cannot be programmed
Lock the Information Row 1:
“0” indicates the Information Row can be programmed
“1” indicates the Information Row cannot be programmed
Lock the Information Row 2:
“0” indicates the Information Row can be programmed
“1” indicates the Information Row cannot be programmed
Lock the Information Row 3:
“0” indicates the Information Row can be programmed
“1” indicates the Information Row cannot be programmed
Read/Write
R
Reserved
R
Reserved
R
Volatile
R
Volatile
R/W
OTP
R/W
OTP
R/W
OTP
R/W
OTP
Type
Note: Once OTP bits of Function Register are written to “1”, it cannot be modified to “0” any more.
PSUS bit: The Program Suspend Status bit indicates when a Program operation has been suspended. The
PSUS changes to “1” after a suspend command is issued during the program operation. Once the suspended
Program resumes, the PSUS bit is reset to “0”.
ESUS bit: The Erase Suspend Status indicates when an Erase operation has been suspended. The ESUS bit is
“1” after a suspend command is issued during an Erase operation. Once the suspended Erase resumes, the
ESUS bit is reset to “0”.
IR Lock bit 0 ~ 3: The default is “0” so that the Information Row can be programmed. If the bit set to “1”, the
Information Row can’t be programmed. Once it set to “1”, it cannot be changed back to “0” since IR Lock bits are
OTP.
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7. PROTECTION MODE
The device supports hardware and software write-protection mechanisms.
7.1 HARDWARE WRITE PROTECTION
The Write Protection (WP#) pin provides a hardware write protection method for BP3, BP2, BP1, BP0, QE, and
SRWD in the Status Register. Refer to the section 6.1 STATUS REGISTER.
Write inhibit voltage (VWI) is specified in the section 9.8 POWER-UP AND POWER-DOWN. All write sequence will
be ignored when Vcc drops to VWI.
Table 7.1 Hardware Write Protection on Status Register
SRWD
WP#
Status Register
0
Low
Writable
1
Low
Protected
0
High
Writable
1
High
Writable
Note: Before the execution of any program, erase or Write Status/Function Register instruction, the Write Enable
Latch (WEL) bit must be enabled by executing a Write Enable (WREN) instruction. If the WEL bit is not enabled,
the program, erase or write register instruction will be ignored.
7.2 SOFTWARE WRITE PROTECTION
The device also provides a software write protection feature. The Block Protection (BP3, BP2, BP1, and BP0) bits
allow part or the whole memory area to be write-protected.
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8. DEVICE OPERATION
The device utilizes an 8-bit instruction register. Refer to Table 8.1. Instruction Set for details on Instructions and
Instruction Codes. All instructions, addresses, and data are shifted in with the most significant bit (MSB) first on
Serial Data Input (SI) or Serial Data IOs (IO0, IO1, IO2, IO3). The input data on SI or IOs is latched on the rising
edge of Serial Clock (SCK) after Chip Enable (CE#) is driven low (V IL). Every instruction sequence starts with a
one-byte instruction code and is followed by address bytes, data bytes, or both address bytes and data bytes,
depending on the type of instruction. CE# must be driven high (V IH) after the last bit of the instruction sequence
has been shifted in to end the operation.
Table 8.1 Instruction Set
Instruction Name
Hex Code
Operation
Mode
RD
03h
Read Data Bytes from Memory at Normal Read Mode
SPI
Maximum
Frequency
33MHz
FR
0Bh
Read Data Bytes from Memory at Fast Read Mode
SPI
104MHz
FRDIO
BBh
Fast Read Dual I/O
SPI
104MHz
FRDO
3Bh
Fast Read Dual Output
SPI
104MHz
FRQIO
EBh
Fast Read Quad I/O
SPI
104MHz
FRQO
6Bh
Fast Read Quad Output
SPI
104MHz
PP
02h
Page Program Data Bytes Into Memory
SPI
104MHz
PPQ
32h/38h
Page Program Data Bytes Into Memory with Quad interface
SPI
104MHz
SER
D7h/20h
Sector Erase 4KB
SPI
104MHz
BER32 (32Kbyte)
52h
Block Erase 32KB
SPI
104MHz
BER64 (64Kbyte)
D8h
Block Erase 64KB
SPI
104MHz
CER
C7h/60h
Chip Erase
SPI
104MHz
WREN
06h
Write Enable
SPI
104MHz
WRDI
04h
Write Disable
SPI
104MHz
RDSR
05h
Read Status Register
SPI
104MHz
WRSR
01h
Write Status Register
SPI
104MHz
RDFR
48h
Read Function Register
SPI
104MHz
WRFR
42h
Write Function Register
SPI
104MHz
PERSUS
75h/B0h
Suspend during the program/erase
SPI
104MHz
PERRSM
7Ah/30h
Resume program/erase
SPI
104MHz
DP
B9h
Deep power down mode
SPI
104MHz
RDID, RDPD
ABh
Read Manufacturer and Product ID/release Deep power down
SPI
104MHz
RDUID
4Bh
Read Unique ID Number
SPI
104MHz
RDJDID
9Fh
Read Manufacturer and Product ID by JEDEC ID Command
SPI
104MHz
RDMDID
90h
Read Manufacturer and Device ID
SPI
104MHz
RDSFDP
5Ah
SFDP Read
SPI
104MHz
RSTEN
66h
Software reset enable
SPI
104MHz
RST
99h
Reset
SPI
104MHz
IRP
62h
Program Information Row
SPI
104MHz
IRRD
68h
Read Information Row
SPI
104MHz
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IS25LQ032B/016B/080B
Instruction Name
Hex Code
Operation
SECUNLOCK
26h
Sector Unlock
SPI
Maximum
Frequency
104MHz
SECLOCK
24h
Sector Lock
SPI
104MHz
Mode
8.1 READ DATA OPERATION (RD, 03H)
The Read Data (RD) instruction is used to read memory contents of the device at a maximum frequency of 33MHz.
The RD instruction code is transmitted via the SI line, followed by three address bytes (A23 - A0) of the first
memory location to be read. A total of 24 address bits are shifted in, but only AVMSB (Valid Most Significant Bit) A0 are decoded. The remaining bits (A23 – AVMSB+1) are ignored. The first byte address can be at any memory
location. Upon completion, any data on the SI will be ignored. Refer to Table 8.2 for the related Address Key.
The first byte data (D7 - D0) address is shifted out on the SO line, MSB first. A single byte of data, or up to the
whole memory array, can be read out in one READ instruction. The address is automatically incremented after
each byte of data is shifted out. The read operation can be terminated at any time by driving CE# high (VIH) after
the data comes out. When the highest address of the device is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read in one continuous READ instruction.
If a Read Data instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction
is ignored and will not have any effects on the current cycle.
Table 8.2 Address Key
Valid Address
AVMSB–A0
IS25LQ032B
A21-A0
(A23-A22=X)
IS25LQ016B
A20-A0
(A23-A21=X)
IS25LQ080B
A19-A0
(A23-A20=X)
Note: X=Don’t Care
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Figure 8.1 Read Data Sequence
CE #
Mode 3
0
1
2
3
4
5
7
6
8
9
10
...
28
29
30
31
SCK
Mode 0
3-byte Address
SI
Instruction = 03h
23
22
21
...
3
2
1
0
44
45
46
47
48
High Impedance
SO
CE #
32
33
34
35
36
37
39
38
40
41
42
43
SCK
SI
Data Out 1
SO
tV
7
6
5
4
3
Data Out 2
2
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0
7
6
5
4
3
2
1
0
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8.2 FAST READ DATA OPERATION (FR, 0BH)
The FAST_READ instruction is used to read memory data at up to a 104MHZ clock.
The FAST_READ instruction code is followed by three address bytes (A23 - A0) and a dummy byte (8 clocks),
transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte from the
address is shifted out on the SO line, with each bit shifted out at a maximum frequency f CT, during the falling edge
of SCK.
The first byte addressed can be at any memory location. The address is automatically incremented after each
byte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h
address, allowing the entire memory to be read with a single FAST_READ instruction. The FAST_READ
instruction is terminated by driving CE# high (VIH).
If a Fast Read Data instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the
instruction is ignored and will not have any effects on the current cycle.
Figure 8.2 Fast Read Data Sequence
CE #
Mode 3
0
1
2
3
4
5
7
6
8
9
10
...
28
29
30
31
SCK
Mode 0
3-byte Address
SI
Instruction = 0Bh
23
22
21
...
3
2
1
0
44
45
46
47
48
High Impedance
SO
CE #
32
33
34
35
36
37
38
39
40
41
42
43
SCK
SI
Dummy Byte
Data Out
tV
SO
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5
4
3
2
1
0
...
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8.3 HOLD OPERATION
HOLD# is used in conjunction with CE# to select the device. When the device is selected and a serial sequence
is underway, HOLD# can be used to pause the serial communication with the master device without resetting the
serial sequence. To pause, HOLD# is brought low while the SCK signal is low. To resume serial communication,
HOLD# is brought high while the SCK signal is low (SCK may still toggle during HOLD). Inputs to SI will be ignored
while SO is in the high impedance state, during HOLD.
Timing graph can be referenced in AC Parameters Figure 9.3.
8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBH)
The FRDIO instruction allows the address bits to be input two bits at a time. This may allow for code to be executed
directly from the SPI in some applications.
The FRDIO instruction code is followed by three address bytes (A23 – A0) and a mode byte, transmitted via the
IO1 and IO0 lines, with each pair of bits latched-in during the rising edge of SCK. The address MSB is input on
IO1, the next bit on IO0, and continue to shift in alternating on the two lines. If AXh (where X is don’t care) is input
for the mode byte, the device will enter AX read mode. In the AX read mode, the next instruction expected from
the device will be another FRDIO instruction and will not need the BBh instruction code so that it saves cycles as
described in Figure 8.4. If the following mode byte is not set to AXh, the device will exit AX read mode. To avoid
any I/O contention problem, X should be Hi-Z.
Once address and mode byte are input the device will read out data at the specified address. The first data byte
addressed is shifted out on the IO1 and IO0 lines, with each pair of bits shifted out at a maximum frequency f CT,
during the falling edge of SCK. The first bit (MSB) is output on IO1, while simultaneously the second bit is output
on IO0. Figure 8.3 illustrates the timing sequence.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FRDIO instruction. FRDIO instruction is
terminated by driving CE# high (VIH).
If the FRDIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not affect the current cycle.
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Figure 8.3 Fast Read Dual I/O Sequence (with command decode cycles)
CE #
Mode 3
0
1
2
3
4
5
7
6
8
9
10
...
18
19
20
21
SCK
Mode 0
Mode Bits
3-byte Address
IO0
Instruction = BBh
22
20
18
...
2
0
6
4
23
21
19
...
3
1
7
5
34
35
36
37
38
High Impedance
IO1
CE #
22
23
24
25
26
27
29
28
30
31
32
33
SCK
tV
IO0
2
0
6
4
2
0
6
Data Out 1
IO1
3
1
7
5
3
4
2
0
6
Data Out 2
1
7
5
3
4
2
0
...
...
...
1
...
...
...
Data Out 3
1
7
5
3
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). Anything but
AXh in the mode byte cycle will keep the same sequence.
2. To avoid I/O contention, X should be Hi-Z.
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Figure 8.4 Fast Read Dual I/O Sequence (without command decode cycles)
CE #
Mode 3
0
1
2
3
...
11
12
13
14
15
16
17
18
19
20
22
21
SCK
Mode 0
Mode Bits
3-byte Address
tV
Data Out 2
Data Out 1
IO0
22
20
18
...
2
0
6
4
2
0
6
4
2
0
6
4
...
IO1
23
21
19
...
3
1
7
5
3
1
7
5
3
1
7
5
...
Notes:
1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When
the mode bits are different from AXh, the device exits the AX read operation.
2. To avoid I/O contention, X should be Hi-Z.
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8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3BH)
The FRDO instruction is used to read memory data on two output pins each at up to a 104MHZ clock.
The FRDO instruction code is followed by three address bytes (A23 – A0) and a dummy byte (8 clocks),
transmitted via the IO0 line, with each bit latched-in during the rising edge of SCK. Then the first data byte
addressed is shifted out on the IO1 and IO0 lines, with each pair of bits shifted out at a maximum frequency fCT,
during the falling edge of SCK. The first bit (MSB) is output on IO1. Simultaneously the second bit is output on
IO0.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FRDO instruction. FRDO instruction is
terminated by driving CE# high (VIH).
If a FRDO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not have any effects on the current cycle.
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Figure 8.5 Fast Read Dual-Output Sequence
CE #
Mode 3
0
1
2
3
4
5
7
6
8
9
10
11
28
29
30
31
SCK
Mode 0
3-byte Address
IO0
Instruction = 3Bh
23
22
41
42
21
...
3
2
1
0
44
45
46
47
48
High Impedance
IO1
CE #
32
33
34
35
36
37
38
39
40
43
SCK
tV
IO0
6
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0
6
Data Out 1
8 Dummy Cycles
IO1
4
7
5
3
4
2
0
...
1
...
Data Out 2
1
7
5
3
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IS25LQ032B/016B/080B
8.6 FAST READ QUAD OUTPUT (FRQO, 6BH)
The FRQO instruction is used to read memory data on four output pins each at up to a 104 MHz clock.
The FRQO instruction code is followed by three address bytes (A23 – A0) and a dummy byte (8 clocks),
transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte addressed
is shifted out on the IO3, IO2, IO1 and IO0 lines, with each group of four bits shifted out at a maximum frequency
fCT, during the falling edge of SCK. The first bit (MSB) is output on IO3, while simultaneously the second bit is
output on IO2, the third bit is output on IO1, etc.
The first byte addressed can be at any memory location. The address is automatically incremented after each byte
of data is shifted out. W hen the highest address is reached, the address counter will roll over to the 000000h
address, allowing the entire memory to be read with a single FRQO instruction. FRQO instruction is terminated by
driving CE# high (VIH).
If a FRQO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not have any effects on the current cycle.
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Figure 8.6 Fast Read Quad-Output Sequence
CE #
Mode 3
0
1
2
3
4
5
7
6
8
9
10
11
28
29
30
31
SCK
Mode 0
3-byte Address
IO0
Instruction = 6Bh
23
22
21
...
3
2
1
0
44
45
46
47
48
High Impedance
IO1
High Impedance
IO2
High Impedance
IO3
CE #
32
33
34
35
36
37
38
39
40
41
42
43
SCK
tV
IO0
4
8 Dummy Cycles
0
4
0
4
0
4
0
...
Data Out 1 Data Out 2 Data Out 3 Data Out 4
IO1
5
1
5
1
5
1
5
1
...
IO2
6
2
6
2
6
2
6
2
...
IO3
7
3
7
3
7
3
7
3
...
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8.7 FAST READ QUAD I/O OPERATION (FRQIO, EBH)
The FRQIO instruction allows the address bits to be input four bits at a time. This may allow for code to be
executed directly from the SPI in some applications.
The FRQIO instruction code is followed by three address bytes (A23 – A0), a mode byte, and 4 dummy cycles,
transmitted via the IO3, IO2, IO0 and IO1 lines, with each group of four bits latched-in during the rising edge of
SCK. The address of MSB inputs on IO3, the next bit on IO2, the next bit on IO1, the next bit on IO0, and continue
to shift in alternating on the four. The mode byte contains the value AXh (where X is don’t care). After four dummy
clocks, the first data byte addressed is shifted out on the IO3, IO2, IO1 and IO0 lines, with each group of four bits
shifted out at a maximum frequency f CT, during the falling edge of SCK. The first bit (MSB) is output on IO3, while
simultaneously the second bit is output on IO2, the third bit is output on IO1, etc. Figure 8.7.1 illustrates the timing
sequence.
If the mode byte is AXh, the AX read mode is enabled. In the mode, the device expects that the next operation
will be another FRQIO and subsequent FRQIO execution skips command code. It saves command cycles as
described in Figure 8.7.2. The device will remain in this mode until the mode byte is different from AXh.
The first byte addressed can be at any memory location. The address is automatically incremented after each
byte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h
address, allowing the entire memory to be read with a single FRQIO instruction. FRQIO instruction is terminated
by driving CE# high (VIH).
If a FRQIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not have any effects on the current cycle.
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Figure 8.7.1 Fast Read Quad I/O Sequence (with command decode cycles)
CE #
Mode 3
0
1
2
3
4
5
7
6
8
9
10
11
12
13
14
15
SCK
Mode 0
3-byte Address
IO0
Mode Bits
20
16
12
8
4
0
4
0
21
17
13
9
5
1
5
1
IO2
22
18
14
10
6
2
6
2
IO3
23
19
15
11
7
3
7
3
28
29
30
31
32
Instruction = EBh
High Impedance
IO1
CE #
16
17
18
19
20
21
23
22
24
25
26
27
SCK
4 Dummy Cycles
tV Data Out 1 Data Out 2 Data Out 3 Data Out 4 Data Out 5 Data Out 6
IO0
4
0
4
0
4
0
4
0
4
0
4
0
...
IO1
5
1
5
1
5
1
5
1
5
1
5
1
...
6
2
6
2
6
2
6
2
6
2
6
2
...
7
3
7
3
7
3
7
3
7
3
7
3
...
IO2
IO3
Note: If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). Anything
but AXh in the mode byte cycle will exit the AX read mode.
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Figure 8.7.2 Fast Read Quad I/O AX Sequence (without command decode cycles)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
...
SCK
Mode 0
6 Dummy Cycles
3-byte Address
tV
Data Out 1 Data Out 2
IO0
20
16
12
8
4
0
4
0
4
0
4
0
...
IO1
21
17
13
9
5
1
5
1
5
1
5
1
...
IO2
22
18
14
10
6
2
6
2
6
2
6
2
...
IO3
23
19
15
11
7
3
7
3
7
3
7
3
...
Mode Bits
Notes:
1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When
the mode bits are different from AXh, the device exits the AX read operation.
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8.8 PAGE PROGRAM OPERATION (PP, 02H)
The Page Program (PP) instruction allows up to 256 bytes data to be programmed into memory in a single
operation. The destination of the memory to be programmed must be outside the protected memory area set by
the Block Protection (BP3, BP2, BP1, BP0) bits. A PP instruction which attempts to program into a page that is
write-protected will be ignored. Before the execution of PP instruction, the Write Enable Latch (WEL) must be
enabled through a Write Enable (WREN) instruction.
The PP instruction code, three address bytes and program data (1 to 256 bytes) are input via the SI line. Program
operation will start immediately after the CE# is brought high, otherwise the PP instruction will not be executed.
The internal control logic automatically handles the programming voltages and timing. During a program operation,
all instructions will be ignored except the RDSR instruction. The progress or completion of the program operation
can be determined by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the
program operation is still in progress. If WIP bit is “0”, the program operation has completed.
If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the
previously latched data are discarded, and the last 256 bytes are kept to be programmed into the page. The
starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap around
to the beginning of the same page. If the data to be programmed are less than a full page, the data of all other
bytes on the same page will remain unchanged.
Note: A program operation can alter “1”s into “0”s. The same byte location or page may be programmed more than
once, to incrementally change “1”s to “0”s. An erase operation is required to change “0”s to “1”s.
Figure 8.8 Page Program Sequence
0
1
...
7
8
9
...
31
32
33
...
39
...
...
2079
Mode 3
2072
CE #
SCK
Mode 0
SI
SO
3-byte Address
Instruction = 02h
23
22
...
Data In 1
0
7
6
...
Data In 256
0
...
7
...
0
High Impedance
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8.9 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32H/38H)
The Quad Input Page Program instruction allows up to 256 bytes data to be programmed into memory in a single
operation with four pins (IO0, IO1, IO2 and IO3). The destination of the memory to be programmed must be
outside the protected memory area set by the Block Protection (BP3, BP2, BP1, BP0) bits. A Quad Input Page
Program instruction which attempts to program into a page that is write-protected will be ignored. Before the
execution of Quad Input Page Program instruction, the QE bit in the Status Register must be set to “1” and the
Write Enable Latch (WEL) must be enabled through a Write Enable (WREN) instruction.
The Quad Input Page Program instruction code, three address bytes and program data (1 to 256 bytes) are input
via the four pins (IO0, IO1, IO2 and IO3). Program operation will start immediately after the CE# is brought high,
otherwise the Quad Input Page Program instruction will not be executed. The internal control logic automatically
handles the programming voltages and timing. During a program operation, all instructions will be ignored except
the RDSR instruction. The progress or completion of the program operation can be determined by reading the
WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the program operation is still in progress. If
WIP bit is “0”, the program operation has completed.
If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the
previously latched data are discarded, and the last 256 bytes data are kept to be programmed into the page. The
starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap around
to the beginning of the same page. If the data to be programmed are less than a full page, the data of all other
bytes on the same page will remain unchanged.
Note: A program operation can alter “1”s into “0”s. The same byte location or page may be programmed more than
once, to incrementally change “1”s to “0”s. An erase operation is required to change “0”s to “1”s.
Figure 8.9 Quad Input Page Program operation
CE #
Mode 3
0
1
2
3
4
5
6
7
8
9
...
31
32
33
34
35
SCK
Mode 0
3-byte Address
Data In 1
Data In 2
4
0
4
0
...
5
1
5
1
...
IO2
6
2
6
2
...
IO3
7
3
7
3
...
IO0
IO1
Instruction = 32h/38h
High Impedance
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22
...
0
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8.10 ERASE OPERATION
The Erase command sets all bits in the addressed sector or block to “1”s.
The memory array is organized into uniform 4 Kbyte sectors or 32/64 Kbyte uniform blocks (a block consists of
eight/sixteen adjacent sectors respectively).
Before a byte is reprogrammed, the sector or block that contains the byte must be erased (erasing sets bits to
“1”). In order to erase the device, there are three erase instructions available: Sector Erase (SER), Block Erase
(BER) and Chip Erase (CER). A sector erase operation allows any individual sector to be erased without affecting
the data in other sectors. A block erase operation erases any individual block. A chip erase operation erases the
whole memory array of a device. A sector erase, block erase or chip erase operation can be executed prior to any
programming operation.
8.11 SECTOR ERASE OPERATION (SER, D7H/20H)
A Sector Erase (SER) instruction erases a 4 Kbyte sector before the execution of a SER instruction, the Write
Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is reset automatically after
the completion of Sector Erase operation.
A SER instruction is entered, after CE# is pulled low to select the device and stays low during the entire instruction
sequence The SER instruction code, and three address bytes are input via SI. Erase operation will start
immediately after CE# is pulled high. The internal control logic automatically handles the erase voltage and timing.
During an erase operation, all instruction will be ignored except the Read Status Register (RDSR) instruction. The
progress or completion of the erase operation can be determined by reading the WIP bit in the Status Register
using a RDSR instruction. If the WIP bit is “1”, the erase operation is still in progress. If the WIP bit is “0”, the erase
operation has been completed.
Figure 8.10 Sector Erase Sequence
CE #
Mode 3
0
1
2
3
4
5
6
7
8
9
10
...
28
29
30
31
1
0
SCK
Mode 0
3-byte Address
SI
SO
Instruction = D7h/20h
23
22
21
...
3
2
High Impedance
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8.12 BLOCK ERASE OPERATION (BER32K:52H, BER64K:D8H)
A Block Erase (BER) instruction erases a 32/64 Kbyte block. Before the execution of a BER instruction, the Write
Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically after the
completion of a block erase operation.
The BER instruction code and three address bytes are input via SI. Erase operation will start immediately after
the CE# is pulled high, otherwise the BER instruction will not be executed. The internal control logic automatically
handles the erase voltage and timing.
Figure 8.11 Block Erase (64KB) Sequence
CE #
Mode 3
0
1
2
3
4
5
6
7
8
9
10
...
28
29
30
31
SCK
Mode 0
3-byte Address
SI
Instruction = D8h
23
22
21
...
3
2
1
0
8
9
10
...
28
29
30
31
1
0
High Impedance
SO
Figure 8.12 Block Erase (32KB) Sequence
CE #
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
SI
SO
3-byte Address
Instruction = 52h
23
22
21
...
3
2
High Impedance
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8.13 CHIP ERASE OPERATION (CER, C7H/60H)
A Chip Erase (CER) instruction erases the entire memory array. Before the execution of CER instruction, the Write
Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically after
completion of a chip erase operation.
The CER instruction code is input via the SI. Erase operation will start immediately after CE# is pulled high,
otherwise the CER instruction will not be executed. The internal control logic automatically handles the erase
voltage and timing.
Figure 8.13 Chip Erase Sequence
CE#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
SI
SO
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Instruction = C7h/60h
High Impedance
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8.14 WRITE ENABLE OPERATION (WREN, 06H)
The Write Enable (WREN) instruction is used to set the Write Enable Latch (WEL) bit. The WEL is reset to the
write-protected state after power-up. The WEL bit must be write enabled before any write operation, including
Sector Erase, Block Erase, Chip Erase, Page Program, Write Status Register, and Write Function Register
operations. The WEL bit will be reset to the write-protected state automatically upon completion of a write
operation. The WREN instruction is required before any above operation is executed.
Figure 8.14 Write Enable Sequence
CE#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Address
Instruction = 06h
SI
High Impedance
SO
8.15 WRITE DISABLE OPERATION (WRDI, 04H)
The Write Disable (WRDI) instruction resets the WEL bit and disables all write instructions. The WRDI instruction
is not required after the execution of a write instruction, since the WEL bit is automatically reset.
Figure 8.15 Write Disable Sequence
CE#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
SI
SO
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Instruction = 04h
High Impedance
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8.16 READ STATUS REGISTER OPERATION (RDSR, 05H)
The Read Status Register (RDSR) instruction provides access to the Status Register. During the execution of a
program, erase or Write Status Register operation, all other instructions will be ignored except the RDSR
instruction, which can be used to check the progress or completion of an operation by reading the WIP bit of
Status Register.
Figure 8.16 Read Status Register Sequence
CE #
Mode 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Mode 0
SI
Instruction = 05h
tV
Data Out
SO
7
6
5
2
3
4
1
0
8.17 WRITE STATUS REGISTER OPERATION (WRSR, 01H)
The Write Status Register (WRSR) instruction allows the user to enable or disable the block protection and Status
Register write protection features by writing “0”s or “1”s into the non-volatile BP3, BP2, BP1, BP0, and SRWD
bits. Also WRSR instruction allows the user to disable or enable quad operation by writing “0” or “1” into the nonvolatile QE bit.
Figure 8.17 Write Status Register Sequence
CE #
Mode 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2
1
0
SCK
Mode 0
Data In
SI
SO
Instruction = 01h
7
6
5
4
3
High Impedence
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8.18 READ FUNCTION REGISTER OPERATION (RDFR, 48H)
The Read Function Register (RDFR) instruction provides access to the Function Register. Refer to Table 6.6
Function Register Bit Definition for more detail.
Figure 8.18 Read Function Register Sequence
CE #
Mode 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Mode 0
SI
Instruction = 48h
tV
Data Out
SO
7
6
5
2
3
4
1
0
8.19 WRITE FUNCTION REGISTER OPERATION (WRFR, 42H)
The Write Function Register (WRFR) instruction allows the user to lock the Information Row by bit 0. (IR Lock)
Figure 8.19 Write Function Register Sequence
CE #
Mode 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2
1
0
SCK
Mode 0
Data In
SI
SO
Instruction = 42h
7
6
5
4
3
High Impedence
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8.20 PROGRAM/ERASE SUSPEND & RESUME
The device allows the interruption of Sector-Erase, Block-Erase or Page-Program operations to conduct other
operations. 75h/B0h command for suspend and 7Ah/30h for resume will be used. Function Register bit2 (PSUS)
and bit3 (ESUS) are used to check whether or not the device is in suspend mode.
Suspend to read ready timing: 100µs
Resume to another suspend timing: 1.5ms
PROGRAM/ERASE SUSPEND DURING SECTOR-ERASE OR BLOCK-ERASE (PERSUS 75h/B0h)
The Program/Erase Suspend allows the interruption of Sector Erase and Block Erase operations. After the
Program/Erase Suspend, WEL bit will be disabled, therefore only read related, resume and reset commands can
be accepted. Refer to Table 8.3 for more detail.
To execute the Program/Erase Suspend operation, the host drives CE# low, sends the Program/Erase Suspend
command cycle (75h/B0h), then drives CE# high. The Function Register indicates that the erase has been
suspended by changing the ESUS bit from “0” to “1”, but the device will not accept another command until it is
ready. To determine when the device will accept a new command, poll the WIP bit in the Status Register or wait
the specified time tSUS. When ESUS bit is issued, the Write Enable Latch (WEL) bit will be reset.
PROGRAM/ERASE SUSPEND DURING PAGE PROGRAMMING (PERSUS 75h/B0h)
The Program/Erase Suspend allows the interruption of all array program operations. After the Program/Erase
Suspend command, WEL bit will be disabled, therefore only read related, resume and reset commands can be
accepted. Refer to Table 8.3 for more detail.
To execute the Program/Erase Suspend operation, the host drives CE# low, sends the Program/Erase Suspend
command cycle (75h/B0h), then drives CE# high. The Function Register indicates that the programming has been
suspended by changing the PSUS bit from “0” to “1”, but the device will not accept another command until it is
ready. To determine when the device will accept a new command, poll the WIP bit in the Status Register or wait
the specified time tSUS.
PROGRAM/ERASE RESUME (PERRSM 7Ah/30h)
The Program/Erase Resume restarts a Program or Erase command that was suspended, and changes the
suspend status bit in the Function Register (ESUS or PSUS bits) back to “0”. To execute the Program/Erase
Resume operation, the host drives CE# low, sends the Program/Erase Resume command cycle (7Ah/30h), then
drives CE# high. A cycle is two nibbles long, most significant nibble first. To determine if the internal, self-timed
Write operation completed, poll the WIP bit in the Status Register, or wait the specified time tSE, tBE or tPP for Sector
Erase, Block Erase, or Page Programming, respectively. The total write time before suspend and after resume
will not exceed the uninterrupted write times tSE, tBE or tPP.
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Table 8.3 Instructions accepted during Suspend
Operation
Suspended
Instruction Allowed
Name
Program or Erase
RD
Program or Erase
Program or Erase
Hex Code
Operation
03h
Read Data Bytes from Memory at Normal Read Mode
FR
0Bh
Read Data Bytes from Memory at Fast Read Mode
FRDIO
BBh
Fast Read Dual I/O
Program or Erase
FRDO
3Bh
Fast Read Dual Output
Program or Erase
FRQIO
EBh
Fast Read Quad I/O
Program or Erase
FRQO
6Bh
Fast Read Quad Output
Program or Erase
RDSR
05h
Read Status Register
Program or Erase
RDFR
48h
Read Function Register
Program or Erase
PERRSM
7Ah/30h
Resume program/erase
Program or Erase
RDID
ABh
Read Manufacturer and Product ID
Program or Erase
RDUID
4Bh
Read Unique ID Number
Program or Erase
RDJDID
9Fh
Read Manufacturer and Product ID by JEDEC ID Command
Program or Erase
RDMDID
90h
Read Manufacturer and Device ID
Program or Erase
RDSFDP
5Ah
SFDP Read
Program or Erase
RSTEN
66h
Software reset enable
Program or Erase
RST
99h
Reset (Only along with 66h)
Program or Erase
IRRD
68h
Read Information Row
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8.21 DEEP POWER DOWN (DP, B9H)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (enter
into Power-Down mode), the standby current is reduced from ISB1 to ISB2. During the Power-down mode, the device
is not active and all Write/Program/Erase instructions are ignored. The instruction is initiated by driving the CE#
pin low and shifting the instruction code into the device. The CE# pin must be driven high after the instruction has
been latched. If this is not done the Power-Down will not be executed. After CE# pin driven high, the power-down
state will be entered within the time duration of tDP. While in the power-down state only the Release from Powerdown/RDID instruction, which restores the device to normal operation, will be recognized. All other instructions
are ignored. This includes the Read Status Register instruction, which is always available during normal operation.
Ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write
protection. It can support in SPI and Multi-I/O mode.
Figure 8.20 Enter Deep Power Down Mode Operation (SPI)
tDP
CE #
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
SI
Instruction = B9h
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8.22 RELEASE DEEP POWER DOWN (RDPD, ABH)
The Release from Power-down/Read Device ID instruction is a multi-purpose instruction. To release the device
from the deep power-down mode, the instruction is issued by driving the CE# pin low, shifting the instruction code
“ABh” and driving CE# high.
Release from power-down will take the time duration of tRES1 before the device will resume normal operation and
other instructions are accepted. The CE# pin must remain high during the t RES1 time duration.
If the Release from Power-down/RDID instruction is issued while an Erase, Program or Write cycle is in process
(when WIP equals 1) the instruction is ignored and will not have any effects on the current cycle.
Figure 8.21 Release Power Down Sequence (SPI)
tRES1
CE #
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
SI
Instruction = ABh
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8.23 READ PRODUCT IDENTIFICATION (RDID, ABH)
The Release from Power-down/Read Device ID instruction is a multi-purpose instruction. It can support both SPI
and Multi-I/O mode. The Read Product Identification (RDID) instruction is for reading out the old style of 8-bit
Electronic Signature, whose values are shown as table of Product Identification.
The RDID instruction code is followed by three dummy bytes, each bit being latched-in on SI during the rising
SCK edge. Then the Device ID is shifted out on SO with the MSB first, each bit been shifted out during the falling
edge of SCK. The RDID instruction is ended by CE# going high. The Device ID (ID7-ID0) outputs repeatedly if
additional clock cycles are continuously sent on SCK while CE# is at low.
Table 8.4 Product Identification
Manufacturer ID
(MF7-MF0)
ISSI Serial Flash
9Dh
Instruction
ABh
90h
9Fh
Device Density
Device ID (ID7-ID0)
Memory Type + Capacity
(ID15-ID0)
32Mb
15h
4016h
16Mb
14h
4015h
8Mb
13h
4014h
Figure 8.22 Read Product Identification Sequence
CE #
Mode 3 0
1
...
7
8
9
...
31
32
33
...
39
SCK
Mode 0
SI
Instruction = ABh
3 Dummy Bytes
tV
SO
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Data Out
Device ID
(ID7-ID0)
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8.24 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9FH)
The JEDEC ID READ instruction allows the user to read the manufacturer and product ID of devices. Refer to
Table 8.4 Product Identification for Manufacturer ID and Device ID. After the JEDEC ID READ command (9Fh) is
input, the Manufacturer ID is shifted out on SO with the MSB first, followed by the Memory Type and Capacity
ID15-ID0. Each bit is shifted out during the falling edge of SCK. If CE# stays low after the last bit of the Device ID
is shifted out, the Manufacturer ID and Device (Type/Capacity) IDs will loop until CE# is pulled high.
Figure 8.23 Read Product Identification by JEDEC ID Read Sequence
CE #
Mode 3
0
1
...
7
8
9
...
15
16
17
...
23
24
25
...
31
SCK
Mode 0
SI
Instruction = 9Fh
Data Out
tV
SO
Manufacturer ID
(MF7-MF0)
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Memory Type
(ID15-ID8)
Capacity
(ID7-ID0)
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8.25 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90H)
The Read Device Manufacturer and Device ID (RDMDID) instruction allows the user to read the Manufacturer and
product ID of the devices. Refer to Table 8.4 Product Identification for Manufacturer ID and Device ID. The
RDMDID instruction code is followed by three byte address (A23~A0), each bit being latched-in on SI during the
rising edge of SCK. If A0 = 0 (A23-A1 bits are don’t care), then the Manufacturer ID is shifted out on SO with the
MSB first, then the Device ID (ID7-ID0). Each bit is shifted out during the falling edge of SCK. If A0 = 1 (A23-A1
bits are don’t care), then device ID1 will be read first, followed Manufacturer ID. The Manufacturer and Device ID
can be read continuously alternating between the two until CE# is driven high.
Figure 8.24 Read Product Identification by RDMDID Sequence
CE #
Mode 3
0
1
...
7
8
9
...
31
32
33
...
39
40
41
...
47
SCK
Mode 0
SI
Instruction = 90h
3 Byte Address
Data Out
tV
SO
Manufacturer ID
(MF7-MF0)
Device ID
(ID7-ID0)
Notes:
1. ADDRESS A0 = 0, will output the 1-byte Manufacture ID (MF7-MF0) 1-byte Device (ID7-ID0)
ADDRESS A0 = 1, will output the 1-byte Device (ID7-ID0) 1-byte Manufacture ID (MF7-MF0)
2. The Manufacturer and Device ID can be read continuously and will alternate from one to the other until CE# pin is
pulled high.
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8.26 READ UNIQUE ID NUMBER (RDUID, 4BH)
The Read Unique ID Number (RDUID) instruction accesses a factory-set read-only 16-byte number that is unique
to the device. The ID number can be used in conjunction with user software methods to help prevent copying or
cloning of a system. The RDUID instruction is instated by driving the CE# pin low and shifting the instruction code
(4Bh) followed by 3 address bytes and a dummy byte. After which, the 16-byte ID is shifted out on the falling edge
of SCK as shown below. As a result, the sequence of RDUID instruction is same as FAST READ.
Note: 16-byte of data will repeat as long as CE# is low and SCK is toggling.
Figure 8.25 RDUID Operation
CE #
Mode 3
0
1
...
7
8
9
...
31
32
33
...
39
40
41
...
47
SCK
Mode 0
SI
Instruction = 4Bh
3 Byte Address
Dummy Byte
tV
SO
Data Out
A[23:16]
A[15:9]
A[8:4]
A[3:0]
XXh
XXh
00h
0h Byte address
XXh
XXh
00h
1h Byte address
XXh
XXh
00h
2h Byte address
XXh
XXh
00h
…
Table 8.5 Unique ID Addressing
XXh
XXh
00h
Fh Byte address
Note: XX means “don’t care”.
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8.27 READ SFDP OPERATION (RDSFDP, 5AH)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the
functional and feature capabilities of serial Flash devices in a standard set of internal parameter tables. These
parameter tables can be interrogated by host system software to enable adjustments needed to accommodate
divergent features from multiple vendors. For more details please refer to the JEDEC Standard JESD216A (Serial
Flash Discoverable Parameters).
The sequence of issuing RDSFDP instruction is same as FAST_READ: CE# goes low Send RDSFDP
instruction (5Ah) Send 3 address bytes on SI pin Send 1 dummy byte on SI pin Read SFDP code on SO
End RDSFDP operation by driving CE# high at any time during data out. Refer to ISSI’s Application note for
SFDP table. The data at the addresses that are not specified in SFDP table are undefined.
The sequence of RDSFDP instruction is same as FAST READ except for the instruction code.
Figure 8.26 RDSFDP (Read SFDP) Operation
CE #
Mode 3
0
1
...
7
8
9
...
31
32
33
...
39
40
41
...
47
SCK
Mode 0
SI
Instruction = 5Ah
3 Byte Address
Dummy Byte
tV
SO
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Data Out
49
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8.28 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66H) AND RESET (RST, 99H)
The Reset operation is used as a system (software) reset that puts the device in normal operating mode. This
operation consists of two commands: Reset-Enable (RSTEN) and Reset (RST). The Reset operation requires the
Reset-Enable command followed by the Reset command. Any command other than the Reset command after the
Reset-Enable command will disable the Reset-Enable.
Execute the CE# pin low sends the Reset-Enable command (66h), and drives CE# high. Next, the host drives
CE# low again, sends the Reset command (99h), and drives CE# high.
The Software Reset during an active Program or Erase operation aborts the operation, which can result in
corrupting or losing the data of the targeted address range. Depending on the prior operation, the reset timing
may vary. Recovery from a Write operation requires more latency time than recovery from other operations.
Note: The Status and Function Registers remain unaffected.
Figure 8.27 Software Reset Enable and Software Reset Operations (RSTEN, 66h + RST, 99h)
CE#
Mode 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Mode 0
SI
Instruction = 66h
Instruction = 99h
High Impedance
SO
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8.29 SECURITY INFORMATION ROW (OTP AREA)
The security Information Row is comprised of an additional 4 x 256 bytes of programmable information. The
security bits can be reprogrammed by the user. Any program security instruction issued while program cycle is in
progress is rejected without having any effect on the cycle that is in progress.
Table 8.6 Information Row Valid Address Range
Address Assignment
IRL0 (Information Row Lock0)
IRL1
IRL2
IRL3
A[23:16]
00h
00h
00h
00h
A[15:8]
00h
10h
20h
30h
A[7:0]
Byte address
Byte address
Byte address
Byte address
Bit 7~4 of the Function Register is used to permanently lock the programmable memory array.
-When Function Register bit IRLx = “0”, the 256 bytes of the programmable memory array can be programmed.
-When Function Register bit IRLx = “1”, the 256 bytes of the programmable memory array function as read only.
8.30 INFORMATION ROW PROGRAM OPERATION (IRP, 62H)
The Information Row Program (IRP) instruction allows up to 256 bytes data to be programmed into the memory
in a single operation. Before the execution of IRP instruction, the Write Enable Latch (WEL) must be enabled
through a Write Enable (WREN) instruction.
The IRP instruction code, three address bytes and program data (1 to 256 bytes) should be sequentially input via
the SI line. Three address bytes has to be input as specified in the Table 8.6 Information Row Valid Address
Range. Program operation will start once the CE# goes high, otherwise the IRP instruction will not be executed.
The internal control logic automatically handles the programming voltages and timing. During a program operation,
all instructions will be ignored except the RDSR instruction. The progress or completion of the program operation
can be determined by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the
program operation is still in progress. If WIP bit is “0”, the program operation has completed.
If more than 256 bytes data are sent to a device, the address counter rolls over within the same page. The
previously latched data are discarded and the last 256 bytes data are kept to be programmed into the page. The
starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap around
to the beginning of the same page. If the data to be programmed are less than a full page, the data of all other
bytes on the same page will remain unchanged.
Note: Information Row is only one time programmable (OTP). Once an Information Row is programmed, the data
cannot be altered.
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Figure 8.28 IRP (Information Row Program) Operation
0
1
...
7
8
9
...
31
32
33
...
39
...
...
2079
Mode 3
2072
CE #
SCK
Mode 0
SI
SO
3-byte Address
Instruction = 62h
23
22
...
Data In 1
0
7
6
...
Data In 256
0
...
7
...
0
High Impedance
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8.31 INFORMATION ROW READ OPERATION (IRRD, 68H)
The IRRD instruction is used to read memory data at up to a 104MHZ clock.
The IRRD instruction code is followed by three address bytes (A23 - A0) and a dummy byte (8 clocks), transmitted
via the SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte addressed is shifted
out on the SO line, with each bit shifted out at a maximum frequency fCT, during the falling edge of SCK.
The address is automatically incremented by one after each byte of data is shifted out. Once the address reaches
the last address of each 256 byte Information Row, the next address will not be valid and the data of the address
will be garbage data. It is recommended to repeat four times IRRD operation that reads 256 byte with a valid
starting address of each Information Row in order to read all data in the 4 x 256 byte Information Row array. The
IRRD instruction is terminated by driving CE# high (VIH).
If an IRRD instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not have any effects on the current cycle.
The sequence of IRRD instruction is same as FAST READ except for the instruction code.
Figure 8.29 IRRD (Information Row Read) Operation
CE #
Mode 3
0
1
...
7
8
9
...
31
32
33
...
39
40
41
...
47
SCK
Mode 0
SI
Instruction = 68h
3 Byte Address
Dummy Byte
tV
SO
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8.32 SECTOR LOCK/UNLOCK FUNCTIONS
SECTOR UNLOCK OPERATION (SECUNLOCK, 26h)
The Sector Unlock command allows the user to select a specific sector to allow program and erase operations.
This instruction is effective when the blocks are designated as write-protected through the BP0, BP1, BP2, and
BP3 bits in the Status Register. Only one sector can be enabled at any time. If many SECUNLOCK commands
are input, only the last sector designated by the last SECUNLOCK command will be unlocked. The instruction
code is followed by a 24-bit address specifying the target sector, but A0 through A11 are not decoded. The
remaining sectors within the same block remain as read-only.
Figure 8.30 Sector Unlock Sequence
CE #
Mode 3
0
1
2
3
4
5
6
7
8
9
10
...
28
29
30
31
1
0
SCK
Mode 0
3-byte Address
SI
SO
Instruction = 26h
23
22
21
...
3
2
High Impedance
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SECTOR LOCK OPERATION (SECLOCK, 24h)
The Sector Lock command relocks a sector that was previously unlocked by the Sector Unlock command. The
instruction code does not require an address to be specified, as only one sector can be enabled at a time. The
remaining sectors within the same block remain in read-only mode.
Figure 8.31 Sector Lock Sequence
CE #
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
SI
SO
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9. ELECTRICAL CHARACTERISTICS
9.1 ABSOLUTE MAXIMUM RATINGS (1)
Storage Temperature
-65°C to +150°C
Surface Mount Lead Soldering Temperature
Standard Package
240°C 3 Seconds
Lead-free Package
260°C 3 Seconds
Input Voltage with Respect to Ground on All Pins
-0.5V to VCC + 0.5V
All Output Voltage with Respect to Ground
-0.5V to VCC + 0.5V
VCC
Electrostatic Discharge Voltage (Human Body
-0.5V to +6.0V
Model)(2)
-2000V to +2000V
Notes:
1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. ANSI/ESDA/JEDEC JS-001
9.2 OPERATING RANGE
Part Number
IS25LQ032B/016B/080B
Operating Temperature (Extended Grade E)
-40°C to 105°C
Operating Temperature (Automotive Grade A3)
-40°C to 125°C
Vcc Power Supply
2.3V (VMIN) – 3.6V (VMAX); 3.0V (Typ)
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9.3 DC CHARACTERISTICS
(Under operating range)
Symbo
l
Parameter
VCC Active Read current(3)
ICC1
Typ(2)
Max
NORD at 33MHz
5
11
FRD Single at 104MHz
7
12
FRD Dual at 104MHz
7
13
Condition
Min
9
FRD Quad at 104MHz
VCC Program Current
ICC3
VCC WRSR Current
VCC Erase Current
(SER/BER32K/BER64K)
ICC4
ICC5
VCC Erase Current (CE)
VCC Standby Current
CMOS
ISB1
Deep power down
current
ISB2
105°C
CE# = VCC
17
25
85°C
20(4)
17
25
85°C
20(4)
17
25
85°C
20(4)
VCC = VMAX, CE# = VCC
17
VCC = VMAX, CE# = VCC
23(4)
125°C
25
85°C
20 (4)
105°C
8
30 (4)
125°C
60
85°C
7 (4)
105°C
5
125°C
9 (4)
ILI
Input Leakage Current
VIN = 0V to VCC
ILO
Output Leakage Current
VIN = 0V to VCC
±1
VIL
VIH
(1)
Input Low Voltage
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
VMIN < VCC < VMAX
-0.5
0.3VCC
0.7VCC
VCC + 0.3
IOL = 100 µA
IOH = -100 µA
µA
10
±1
(1)
mA
23(4)
125°C
105°C
CE# = VCC
23(4)
125°C
105°C
CE# = VCC
23(4)
125°C
105°C
CE# = VCC
15
20(4)
85°C
ICC2
Units
0.2
V
VCC - 0.2
Notes:
1. Maximum DC voltage on input or I/O pins is VCC + 0.5V. During voltage transitions, input or I/O pins may overshoot
VCC by +2.0V for a period of time not to exceed 20ns. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, input or I/O pins may undershoot GND by -2.0V for a period of time not to exceed 20ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC
= VCC (Typ), TA=25°C.
3. Outputs are unconnected during reading data so that output switching current is not included.
4. These parameters are characterized and are not 100% tested.
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9.4 AC MEASUREMENT CONDITIONS
Symbol
Parameter
Min
Max
Units
CL
Load Capacitance
30
pF
TR,TF
Input Rise and Fall Times
5
ns
VIN
Input Pulse Voltages
0.2VCC to 0.8VCC
V
VREFI
Input Timing Reference Voltages
0.3VCC to 0.7VCC
V
VREFO
Output Timing Reference Voltages
0.5VCC
V
Figure9.1 Output test load & AC measurement I/O Waveform
0.8VCC
Input
AC
Measurement
Level
VCC/2
1.8k
0.2VCC
OUTPUT PIN
1.2k
30pf
9.5 PIN CAPACITANCE (TA = 25°C, VCC=3V , 1MHZ)
Symbol
CIN
CIN/OUT
Parameter
Input Capacitance
(CE#, SCK)
Input/Output Capacitance
(other pins)
Test Condition
Min
Typ
Max
Units
VIN = 0V
-
-
6
pF
VIN/OUT = 0V
-
-
8
pF
Note:
1. These parameters are characterized and are not 100% tested.
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9.6 AC CHARACTERISTICS
(Under operating range, refer to section 9.4 for AC measurement conditions)
Symbol
Parameter
fCT
Clock Frequency for fast read mode
fC
Clock Frequency for read mode
tRI
Input Rise Time
tFI
Input Fall Time
tCKH
SCK High Time
4
ns
tCKL
SCK Low Time
4
ns
tCEH
CE# High Time
7
ns
tCS
CE# Setup Time
10
ns
tCH
CE# Hold Time
5
ns
tDS
Data In Setup Time
2
ns
tDH
Data in Hold Time
2
ns
tV
Output Valid
tOH
Output Hold Time
tDIS
Output Disable Time
tHLCH
HOLD Active Setup Time relative to SCK
5
ns
tCHHH
HOLD Active Hold Time relative to SCK
5
ns
tHHCH
HOLD Not Active Setup Time relative to SCK
5
ns
tCHHL
HOLD Not Active Hold Time relative to SCK
5
ns
tLZ
HOLD to Output Low Z
tHZ
HOLD to Output High Z
tEC
Min
Typ
Max
Units
0
104
MHz
0
33
MHz
8
ns
8
ns
8
2
ns
ns
100
12
ns
ns
12
ns
Sector Erase Time (4Kbyte)
70
300
ms
Block Erase Time (32Kbyte)
130
500
ms
Block Erase time (64Kbyte)
200
1000
ms
8Mb
3
9
16Mb
5
15
32Mb
10
30
Extended and Extended+ (E and E1)
0.5
1
Automotive grades (A1, A2, A3)
0.5
2
Chip Erase Time
s
tPP
Page Program Time
tres1
Release deep power down
3
µs
tDP
Deep power down
3
µs
tW
Write Status Register time
100
ms
tSUS
Suspend to read ready
100
µs
tSRST
Software Reset cover time
100
µs
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9.7 SERIAL INPUT/OUTPUT TIMING
Figure 9.2 SERIAL INPUT/OUTPUT TIMING (1)
tCEH
CE#
tCS
tCH
tCKH
SCK
tDS
SI
tCKL
tDH
VALID IN
VALID IN
tV
SO
HI-Z
tOH
VALID OUTPUT
tDIS
HI-Z
Note1. For SPI Mode 0 (0,0)
Figure 9.3 HOLD TIMING
CE#
tHLCH
tCHHL
tHHCH
SCK
tCHHH
tHZ
tLZ
SO
SI
HOLD#
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9.8 POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must be NOT SELECTED until Vcc reaches at the right level. (Adding
a simple pull-up resistor on CE# is recommended.)
Power up timing
VCC
VCC(max)
All Write Commands are Rejected
Chip Selection Not Allowed
VCC(min)
Reset State
tVCE
Read Access Allowed
V(write inhibit)
Device fully
accessible
tPUW
Symbol
Parameter
Min.
tVCE(1)
Vcc(min) to CE# Low
1
tPUW (1)
Power-up time delay to write instruction
1
VWI
(1)
Write Inhibit Voltage
Max
Unit
ms
10
ms
2.1
V
Note: These parameters are characterized and are not 100% tested.
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9.9 PROGRAM/ERASE PERFORMANCE
Typ
Max
Unit
Sector Erase Time (4KB)
70
300
ms
Block Erase Time (32KB)
130
500
ms
Block Erase Time (64KB)
200
1000
ms
8Mb
3
9
16Mb
5
15
32Mb
Extended and
Extended+ (E and E1)
Automotive grades
(A1, A2, A3)
10
30
0.5
1
0.5
2
8
25
Parameter
Chip Erase Time
Page Programming
Time
Byte Program
Remarks
From writing erase command to erase
completion
s
ms
From writing program command to
program completion
µs
Note: These parameters are characterized and are not 100% tested.
9.10 RELIABILITY CHARACTERISTICS
Parameter
Min
Max
Unit
Test Method
Endurance
100,000
-
Cycles
JEDEC Standard A117
Data Retention
20
-
Years
JEDEC Standard A117
Latch-Up
-100
+100
mA
JEDEC Standard 78
Note: These parameters are characterized and are not 100% tested.
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10. PACKAGE TYPE INFORMATION
10.1 16-PIN JEDEC 300MIL SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) PACKAGE (M)
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10.2 8-PIN JEDEC 208MIL BROAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) PACKAGE (B)
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10.3 8-PIN JEDEC 150MIL BROAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) PACKAGE (N)
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10.4 8-PIN 208MIL VSOP PACKAGE (F)
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10.5 8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD (WSON) PACKAGE 6X5MM (K)
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10.6 8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD (WSON) PACKAGE 8X6MM (L)
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10.7 24-BALL THIN PROFILE FINE PITCH BGA 6X8MM 4X6 ARRAY (G)
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10.8 8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD (USON) PACKAGE 4X3MM (T)
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10.9 24-BALL THIN PROFILE FINE PITCH BGA 6X8MM 5X5 ARRAY (H)
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11. ORDERING INFORMATION - Valid Part Numbers
IS25LQ 032 B
-
J B L E
TEMPERATURE RANGE
E = Extended (-40°C to +105°C)
A3 = Automotive Grade (-40°C to +125°C)
PACKAGING CONTENT
L = RoHS compliant
PACKAGE Type(1),(2)
M = 16-pin SOIC 300mil
B = 8-pin SOIC 208mil
N = 8-pin SOIC 150mil
F = 8-pin VSOP 208mil
K = 8-contact WSON 6x5mm
L = 8-contact WSON 8x6mm
T = 8-contact USON 4x3mm
G = 24-ball TFBGA 6x8mm 4x6 array (Call Factory)
H = 24-ball TFBGA 6x8mm 5x5 array (Call Factory)
W = KGD (Call Factory)
Option
J = Standard
Q = QE bit set to 1(Default)
Die Revision
B = B Revision
Density
032 = 32 Megabit
016 = 16 Megabit
080 = 8 Megabit
BASE PART NUMBER
IS = Integrated Silicon Solution Inc.
25LQ = FLASH, 2.3V ~ 3.6V, Quad SPI
Note:
1. IS25LQ080B (not available in JM, JL, JG, JH)
2. Call Factory for other package options available
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Density
32Mb
16Mb
Frequency (MHz)
104
104
Order Part Number(1)
Package
IS25LQ032B-JMLE
16-pin SOIC 300mil (Call Factory)
IS25LQ032B-JBLE
8-pin SOIC 208mil
IS25LQ032B-JNLE
8-pin SOIC 150mil
IS25LQ032B-JFLE
8-pin VSOP 208mil
IS25LQ032B-JKLE
8-contact WSON 6x5mm
IS25LQ032B-JLLE
8-contact WSON 8x6mm
IS25LQ032B-JTLE
8-contact USON 4x3mm
IS25LQ032B-JGLE
24-Ball TFBGA 6x8mm 4x6 array (Call Factory)
IS25LQ032B-JHLE
24-Ball TFBGA 6x8mm 5x5 array
IS25LQ032B-JMLA3
16-pin SOIC 300mil
IS25LQ032B-JBLA3
8-pin SOIC 208mil (Call Factory)
IS25LQ032B-JNLA3
8-pin SOIC 150mil
IS25LQ032B-JFLA3
8-pin VSOP 208mil
IS25LQ032B-JKLA3
8-contact WSON 6x5mm
IS25LQ032B-JLLA3
8-contact WSON 8x6mm (Call Factory)
IS25LQ032B-JTLA3
8-contact USON 4x3mm
IS25LQ032B-JGLA3
24-Ball TFBGA 6x8mm 4x6 array (Call Factory)
IS25LQ032B-JHLA3
24-Ball TFBGA 6x8mm 5x5 array
IS25LQ032B-JWLE
KGD (Call Factory)
IS25LQ032B-QWLE
KGD (Call Factory)
IS25LQ016B-JMLE
16-pin SOIC 300mil (Call Factory)
IS25LQ016B-JBLE
8-pin SOIC 208mil
IS25LQ016B-JNLE
8-pin SOIC 150mil
IS25LQ016B-JFLE
8-pin VSOP 208mil
IS25LQ016B-JKLE
8-contact WSON 6x5mm
IS25LQ016B-JLLE
8-contact WSON 8x6mm
IS25LQ016B-JTLE
8-contact USON 4x3mm
IS25LQ016B-JGLE
24-Ball TFBGA 6x8mm 4x6 array (Call Factory)
IS25LQ016B-JHLE
24-Ball TFBGA 6x8mm 5x5 array
IS25LQ016B-JMLA3
16-pin SOIC 300mil
IS25LQ016B-JBLA3
8-pin SOIC 208mil (Call Factory)
IS25LQ016B-JNLA3
8-pin SOIC 150mil
IS25LQ016B-JFLA3
8-pin VSOP 208mil
IS25LQ016B-JKLA3
8-contact WSON 6x5mm
IS25LQ016B-JLLA3
8-contact WSON 8x6mm
IS25LQ016B-JTLA3
8-contact USON 4x3mm
IS25LQ016B-JGLA3
24-Ball TFBGA 6x8mm 4x6 array (Call Factory)
IS25LQ016B-JHLA3
24-Ball TFBGA 6x8mm 5x5 array
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Density
8Mb
Frequency
(MHz)
104
Order Part Number(1)
Package
IS25LQ080B-JBLE
8-pin SOIC 208mil (Call Factory)
IS25LQ080B-JNLE
8-pin SOIC 150mil (Call Factory)
IS25LQ080B-JFLE
8-pin VSOP 208mil (Call Factory)
IS25LQ080B-JKLE
8-contact WSON 6x5mm (Call Factory)
IS25LQ080B-JTLE
8-contact USON 4x3mm (Call Factory)
IS25LQ080B-JBLA3
8-pin SOIC 208mil (Call Factory)
IS25LQ080B-JNLA3
8-pin SOIC 150mil (Call Factory)
IS25LQ080B-JFLA3
8-pin VSOP 208mil (Call Factory)
IS25LQ080B-JKLA3
8-contact WSON 6x5mm (Call Factory)
IS25LQ080B-JTLA3
8-contact USON 4x3mm (Call Factory)
Note:
1. A3 meets AEC-Q100 requirements with PPAP.
Temp Grades: E= -40 to 105°C, A3= -40 to 125°C.
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