IS25WP016
IS25WP080
IS25WP040
IS25WP020
16/8/4/2MBIT
1.8V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI &
QUAD I/O QPI DTR INTERFACE
PRELIMINARY DATA SHEET
IS25WP016/080/040/020
16/8/4/2MBIT
1.8V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI &
QUAD I/O QPI DTR INTERFACE
PRELIMINARY INFORMATION
FEATURES
Industry Standard Serial Interface
- IS25WP016: 16Mbit/2Mbyte
- IS25WP080: 8Mbit/1Mbyte
- IS25WP040: 4Mbit/512Kbyte
- IS25WP020: 2Mbit/256Kbyte
- 256 bytes per Programmable Page
- Supports standard SPI, Fast, Dual, Dual
I/O, Quad, Quad I/O, SPI DTR, Dual I/O
DTR, Quad I/O DTR, and QPI
- Supports Serial Flash Discoverable
Parameters (SFDP)
High Performance Serial Flash (SPI)
- 50MHz Normal and 133Mhz Fast Read
- 532 MHz equivalent QPI
- DTR (Dual Transfer Rate) up to 66MHz
- Selectable Dummy Cycles
- Configurable Drive Strength
- Supports SPI Modes 0 and 3
- More than 100,000 Erase/Program cycles
- More than 20-year Data Retention
Flexible & Efficient Memory Architecture
- Chip Erase with Uniform: Sector/Block
Erase (4/32/64 Kbyte)
- Program 1 to 256 Bytes per Page
- Program/Erase Suspend & Resume
Efficient Read and Program modes
- Low Instruction Overhead Operations
- Continuous Read 8/16/32/64-Byte Burst
Wrap
- Selectable Burst Length
- QPI for Reduced Instruction Overhead
- AutoBoot Operation
Integrated Silicon Solution, Inc.- www.issi.com
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Low Power with Wide Temp. Ranges
- Single 1.65V to 1.95V Voltage Supply
- 10 mA Active Read Current (typ.)
- 8 µA Standby Current (typ.)
- 1 µA Deep Power Down(typ.)
- Temp Grades:
Extended: -40°C to +105°C
Extended+: -40°C to +125°C
Auto Grade: up to +125°C
Note: Extended+ should not be used for Automotive.
Advanced Security Protection
- Software and Hardware Write Protection
- Power Supply Lock Protection
- 4x256-Byte Dedicated Security Area
with OTP User-lockable Bits
- 128 bit Unique ID for Each Device
(Call Factory)
Industry Standard Pin-out & Packages(1),(2)
- M =16-pin SOIC 300mil(3)
- B = 8-pin SOIC 208mil
- N = 8-pin SOIC 150mil
- D = 8-pin TSSOP
- V = 8-pin VVSOP 150mil
- F = 8-pin VSOP 208mil
- K = 8-contact WSON 6x5mm
- T = 8-contact USON 4x3mm
- U = 8-contact USON 2x3mm
- G = 24-ball TFBGA 6x8mm(3)
- KGD (Call Factory)
Notes:
1. IS25WP016 (not available in D) and
IS25WP080/040 (not available in M, D, G) and
IS25WP020 (not available in M, F, T, G)
2. Call Factory for WLCSP or other package options
available
3. For the dedicated RESET# pin option, see the Ordering
Information
2
IS25WP016/080/040/020
GENERAL DESCRIPTION
The IS25WP016/080/040/020 Serial Flash memory offers a versatile storage solution with high flexibility and
performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash is for systems
that require limited space, a low pin count, and low power consumption. The device is accessed through a 4wire SPI Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip
Enable (CE#) pins, which can also be configured to serve as multi-I/O (see pin descriptions).
The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock
frequencies of up to 133MHz allow for equivalent clock rates of up to 532MHz (133MHz x 4) which equates to
66Mbytes/s of data throughput. The IS25xP series of Flash adds support for DTR (Double Transfer Rate)
commands that transfer addresses and read data on both edges of the clock. These transfer rates can
outperform 16-bit Parallel Flash memories allowing for efficient memory access to support XIP (execute in
place) operation.
The memory array is organized into programmable pages of 256-bytes. This family supports page program
mode where 1 to 256 bytes of data are programmed in a single command. QPI (Quad Peripheral Interface)
supports 2-cycle instruction further reducing instruction times. Pages can be erased in groups of 4Kbyte
sectors, 32Kbyte blocks, 64Kbyte blocks, and/or the entire chip. The uniform sector and block architecture
allows for a high degree of flexibility so that the device can be utilized for a broad variety of applications
requiring solid data retention.
GLOSSARY
Standard SPI
In this operation, a 4-wire SPI Interface is utilized, consisting of Serial Data Input (SI), Serial Data Output (SO),
Serial Clock (SCK), and Chip Enable (CE#) pins. Instructions are sent via the SI pin to encode instructions,
addresses, or input data to the device on the rising edge of SCK. The SO pin is used to read data or to check
the status of the device. This device supports SPI bus operation modes (0,0) and (1,1).
Mutil I/O SPI
Multi-I/O operation utilizes an enhanced SPI protocol to allow the device to function with Dual Output, Dual Input
and Output, Quad Output, and Quad Input and Output capability. Executing these instructions through SPI
mode will achieve double or quadruple the transfer bandwidth for READ and PROGRAM operations.
QPI
The device supports Quad Peripheral Interface (QPI) operations only when the device is switched from
Standard/Dual/Quad SPI mode to QPI mode using the enter QPI (35h) instruction. The typical SPI protocol
requires that the byte-long instruction code being shifted into the device only via SI pin in eight serial clocks. The
QPI mode utilizes all four I/O pins to input the instruction code thus requiring only two serial clocks. This can
significantly reduce the SPI instruction overhead and improve system performance. Only QPI mode or
SPI/Dual/Quad mode can be active at any given time. Enter QPI (35h) and Exit QPI (F5h) instructions are used
to switch between these two modes, regardless of the non-volatile Quad Enable (QE) bit status in the Status
Register. Power Reset or Hardware/Software Reset will return the device into the standard SPI mode. SI and
SO pins become bidirectional I/O0 and I/O1, and WP# and HOLD# pins become I/O2 and I/O3 respectively
during QPI mode.
DTR
In addition to SPI and QPI features, the device also supports Fast READ DTR operation. DTR operation allows
high data throughput while running at lower clock frequencies. Fast READ DTR operation uses both rising and
falling edges of the clock for address inputs, and data outputs, resulting in reducing input and output cycles by
half.
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IS25WP016/080/040/020
TABLE OF CONTENTS
FEATURES .......................................................................................................................................................... 2
GENERAL DESCRIPTION .................................................................................................................................. 3
TABLE OF CONTENTS ....................................................................................................................................... 4
1.
PIN CONFIGURATION ................................................................................................................................. 7
2.
PIN DESCRIPTIONS .................................................................................................................................... 8
3.
BLOCK DIAGRAM ...................................................................................................................................... 10
4.
SPI MODES DESCRIPTION ...................................................................................................................... 11
5.
SYSTEM CONFIGURATION ...................................................................................................................... 13
5.1 BLOCK/SECTOR ADDRESSES .......................................................................................................... 13
6.
REGISTERS ............................................................................................................................................... 14
6.1 STATUS REGISTER ............................................................................................................................ 14
6.2 FUNCTION REGISTER ........................................................................................................................ 17
6.3 READ REGISTER AND EXTENDED REGISTER ................................................................................ 18
6.4 AUTOBOOT REGISTER ...................................................................................................................... 21
7.
PROTECTION MODE................................................................................................................................. 22
7.1 HARDWARE WRITE PROTECTION.................................................................................................... 22
7.2 SOFTWARE WRITE PROTECTION .................................................................................................... 22
8.
DEVICE OPERATION ................................................................................................................................ 23
8.1 NORMAL READ OPERATION (NORD, 03h) ....................................................................................... 26
8.2 FAST READ OPERATION (FRD, 0Bh) ................................................................................................ 28
8.3 HOLD OPERATION .............................................................................................................................. 30
8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBh) ........................................................................... 30
8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh) ................................................................... 33
8.6 FAST READ QUAD OUTPUT OPERATION (FRQO, 6Bh).................................................................. 34
8.7 FAST READ QUAD I/O OPERATION (FRQIO, EBh) .......................................................................... 36
8.8 PAGE PROGRAM OPERATION (PP, 02h) .......................................................................................... 40
8.9 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h/38h) ........................................................ 42
8.10 ERASE OPERATION ......................................................................................................................... 43
8.11 SECTOR ERASE OPERATION (SER, D7h/20h) ............................................................................... 44
8.12 BLOCK ERASE OPERATION (BER32K:52h, BER64K:D8h) ............................................................ 45
8.13 CHIP ERASE OPERATION (CER, C7h/60h) ..................................................................................... 47
8.14 WRITE ENABLE OPERATION (WREN, 06h) .................................................................................... 48
8.15 WRITE DISABLE OPERATION (WRDI, 04h) ..................................................................................... 49
8.16 READ STATUS REGISTER OPERATION (RDSR, 05h) ................................................................... 50
8.17 WRITE STATUS REGISTER OPERATION (WRSR, 01h) ................................................................. 51
8.18 READ FUNCTION REGISTER OPERATION (RDFR, 48h) ............................................................... 52
8.19 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h)............................................................. 53
8.20 ENTER QUAD PERIPHERAL INTERFACE (QPI) MODE OPERATION (QPIEN, 35h; QPIDI, F5h) 54
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IS25WP016/080/040/020
8.21 PROGRAM/ERASE SUSPEND & RESUME ...................................................................................... 55
8.22 ENTER DEEP POWER DOWN (DP, B9h) ......................................................................................... 57
8.23 RELEASE DEEP POWER DOWN (RDPD, ABh) ............................................................................... 58
8.24 SET READ PARAMETERS OPERATION (SRPNV: 65h, SRPV: C0h/63h) ...................................... 59
8.25 SET EXTENDED READ PARAMETERS OPERATION (SERPNV: 85h, SERPV: 83h) .................... 61
8.26 READ READ PARAMETERS OPERATION (RDRPNV, 61h) ............................................................ 62
8.27 READ EXTENDED READ PARAMETERS OPERATION (RDRPNV, 81h) ....................................... 63
8.28 READ PRODUCT IDENTIFICATION (RDID, ABh) ............................................................................ 64
8.29 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9Fh; RDJDIDQ, AFh) 66
8.30 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90h) ........................ 67
8.31 READ UNIQUE ID NUMBER (RDUID, 4Bh) ...................................................................................... 68
8.32 READ SFDP OPERATION (RDSFDP, 5Ah) ...................................................................................... 69
8.33 NO OPERATION (NOP, 00h) ............................................................................................................. 69
8.34 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h)) AND HARDWARE
RESET ........................................................................................................................................................ 70
8.35 SECURITY INFORMATION ROW ...................................................................................................... 71
8.36 INFORMATION ROW ERASE OPERATION (IRER, 64h) ................................................................. 72
8.37 INFORMATION ROW PROGRAM OPERATION (IRP, 62h) ............................................................. 73
8.38 INFORMATION ROW READ OPERATION (IRRD, 68h) ................................................................... 74
8.39 FAST READ DTR MODE OPERATION (FRDTR, 0Dh) ..................................................................... 75
8.40 FAST READ DUAL IO DTR MODE OPERATION (FRDDTR, BDh) .................................................. 77
8.41 FAST READ QUAD IO DTR MODE OPERATION (FRQDTR, EDh) ................................................. 80
8.42 SECTOR LOCK/UNLOCK FUNCTIONS ............................................................................................ 84
8.43 AUTOBOOT ........................................................................................................................................ 86
9.
ELECTRICAL CHARACTERISTICS........................................................................................................... 90
9.1 ABSOLUTE MAXIMUM RATINGS
(1)
................................................................................................... 90
9.2 OPERATING RANGE ........................................................................................................................... 90
9.3 DC CHARACTERISTICS ...................................................................................................................... 91
9.4 AC MEASUREMENT CONDITIONS .................................................................................................... 92
9.5 PIN CAPACITANCE (TA = 25°C, VCC=1.8V, 1MHz) .......................................................................... 92
9.6 AC CHARACTERISTICS ...................................................................................................................... 93
9.7 SERIAL INPUT/OUTPUT TIMING ........................................................................................................ 95
9.8 POWER-UP AND POWER-DOWN ...................................................................................................... 97
9.9 PROGRAM/ERASE PERFORMANCE ................................................................................................. 98
9.10 RELIABILITY CHARACTERISTICS ................................................................................................... 98
10.
PACKAGE TYPE INFORMATION ......................................................................................................... 99
10.1 8-Pin JEDEC 208mil Broad Small Outline Integrated Circuit (SOIC) Package (B) ............................ 99
10.2 8-Pin JEDEC 150mil Broad Small Outline Integrated Circuit (SOIC) Package (N) .......................... 100
10.3 8-Pin TSSOP Package (D) ............................................................................................................... 101
10.4 8-Pin 150mil VVSOP Package (V).................................................................................................... 102
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IS25WP016/080/040/020
10.5 8-Contact Ultra-Thin Small Outline No-Lead (WSON) Package 6x5mm (K).................................... 103
10.6 8-Contact Ultra-Thin Small Outline No-Lead (USON) Package 4x3mm (T)..................................... 104
10.7 8-Contact Ultra-Thin Small Outline No-Lead (USON) Package 2x3mm (U) .................................... 105
10.8 8-Pin 208mil VSOP Package (F) ...................................................................................................... 106
10.9 16-lead Plastic Small Outline package (300 mils body width) (M) ................................................... 107
10.10 24-Ball Thin Profile Fine Pitch BGA 6x8mm (G)............................................................................. 108
11.
ORDERING INFORMATION - Valid Part Numbers............................................................................. 109
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IS25WP016/080/040/020
1. PIN CONFIGURATION
CE#
1
8
Vcc
7
HOLD# or
(1)
RESET# (IO3)
8 Vcc
CE# 1
SO (IO1)
WP# (IO2)
GND
2
3
4
SCK
6
HOLD# or
SO (IO1)
2
7 RESET# (IO3)(1)
WP# (IO2)
3
6 SCK
GND
4
5 SI (IO0)
SI (IO0)
5
8-pin SOIC 208mil
8-pin SOIC 150mil
8-pin VSOP 208mil
8-pin TSSOP
8-pin VVSOP 150mil
8-contact WSON 6x5mm
8-contact USON 4x3mm
8-contact USON 2x3mm
Top View, Balls Facing Down
(1,2)
HOLD# or RESET# (IO3)
Vcc
1
16
SCK
A2
A3
NC
RESET#/NC
A4
(3)
2
15
SI (IO0)
RESET#/NC
3
14
NC
NC
4
13
NC
NC
5
12
NC
(3)
NC
6
11
NC
CE#
7
10
GND
SO (IO1)
8
9
16-pin SOIC 300mil
A1
NC
WP# (IO2)
NC
B1
B2
B3
B4
NC
SCK
GND
VCC
C1
C2
C3
C4
NC
CE#
NC
WP#(IO2)
D3
D4
D1
D2
NC
SO(IO1)
(1,2)
SI(IO0) HOLD#(IO3) or
RESET#(IO3)
E1
E2
E3
E4
NC
NC
NC
NC
F1
F2
F3
F4
NC
NC
NC
NC
24-ball TFBGA 6x8mm
Notes:
1. P7 bit setting in Read Register will select HOLD# (P7=0) function or RESET# (P7=1) function when QE=0 for the
standard devices, which do not have dedicated RESET# pin.
2. For the parts with dedicated RESET# pin on pin3 (16-pin SOIC) or ball A3 (24-ball TFBGA), only HOLD# pin is
selected for pin1 (16-pin SOIC) or ball D4 (24-ball TFBGA) regardless of the P7 bit setting.
3. For the dedicated RESET# devices, Function Register Bit0 (RESET# Enable/Disable) was set to “0” from the
factory. The RESET# pin is independent of the P7 bit of Read Register.
The RESET# pin has an internal pull-up resistor and may be left floating if not used. See the Ordering Information
for the additional RESET# pin option.
(1)
(2,3)
16-pin SOIC / 24-ball TFBGA
Standard device
Device with dedicated RESET# pin
Hold#(IO3) or RESET#(IO3) by P7 bit
Pin1 / Ball D4
Hold#(IO3) only regardless of P7 bit setting
setting
Pin3 / Ball A3
NC
RESET#
Part Number Option
J
R or P
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IS25WP016/080/040/020
2. PIN DESCRIPTIONS
For all the standard devices without dedicated RESET# pin
SYMBOL
TYPE
DESCRIPTION
Chip Enable: The Chip Enable (CE#) pin enables and disables the devices
operation. When CE# is high the device is deselected and output pins are in a high
impedance state. When deselected the devices non-critical internal circuitry power
down to allow minimal levels of power consumption while in a standby state.
CE#
INPUT
When CE# is pulled low the device will be selected and brought out of standby
mode. The device is considered active and instructions can be written to, data read,
and written to the device. After power-up, CE# must transition from high to low
before a new instruction will be accepted.
Keeping CE# in a high state deselects the device and switches it into its low power
state. Data will not be accepted when CE# is high.
SI (IO0),
SO (IO1)
INPUT/OUTPUT
Serial Data Input, Serial Output, and IOs (SI, SO, IO0, and IO1):
This device supports standard SPI, Dual SPI, and Quad SPI operation. Standard SPI
instructions use the unidirectional SI (Serial Input) pin to write instructions,
addresses, or data to the device on the rising edge of the Serial Clock (SCK).
Standard SPI also uses the unidirectional SO (Serial Output) to read data or status
from the device on the falling edge of the serial clock (SCK).
In Dual and Quad SPI mode, SI and SO become bidirectional IO pins to write
instructions, addresses or data to the device on the rising edge of the Serial Clock
(SCK) and read data or status from the device on the falling edge of SCK. Quad SPI
instructions use the WP# and HOLD# pins as IO2 and IO3 respectively.
WP# (IO2)
INPUT/OUTPUT
Write Protect/Serial Data IO (IO2): The WP# pin protects the Status Register from
being written in conjunction with the SRWD bit. When the SRWD is set to “1” and the
WP# is pulled low, the Status Register bits (SRWD, QE, BP3, BP2, BP1, BP0) are
write-protected and vice-versa for WP# high. When the SRWD is set to “0”, the
Status Register is not write-protected regardless of WP# state.
When the QE bit is set to “1”, the WP# pin (Write Protect) function is not available
since this pin is used for IO2.
HOLD# or RESET#/Serial Data IO (IO3): When the QE bit of Status Register is set
to “1”, HOLD# pin or RESET# is not available since it becomes IO3.
When QE=0, the pin acts as HOLD# or RESET# and either one can be selected by
the P7 bit setting in Read Register. HOLD# will be selected if P7=0 (Default) and
RESET# will be selected if P7=1.
HOLD# or
RESET# (IO3)
INPUT/OUTPUT
The HOLD# pin allows the device to be paused while it is selected. It pauses serial
communication by the master device without resetting the serial sequence. The
HOLD# pin is active low. When HOLD# is in a low state and CE# is low, the SO pin
will be at high impedance. Device operation can resume when HOLD# pin is brought
to a high state.
RESET# pin is a hardware RESET signal. When RESET# is driven HIGH, the
memory is in the normal operating mode. When RESET# is driven LOW, the
memory enters reset mode and output is High-Z. If RESET# is driven LOW while an
internal WRITE, PROGRAM, or ERASE operation is in progress, data may be lost.
SCK
INPUT
Vcc
POWER
GND
GROUND
NC
Unused
Serial Data Clock: Synchronized Clock for input and output timing operations.
Power: Device Core Power Supply
Ground: Connect to ground when referenced to Vcc
NC: Pins labeled “NC” stand for “No Connect” and should be left unconnected.
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IS25WP016/080/040/020
For the device with dedicated RESET# pin (16-pin SOIC or 24-ball TFBGA)
-
SYMBOL
TYPE
DESCRIPTION
CE#
INPUT
Same as the description in previous page
SI (IO0),
SO (IO1)
INPUT/OUTPUT
Same as the description in previous page
WP# (IO2)
INPUT/OUTPUT
Same as the description in previous page
HOLD#/Serial Data IO (IO3): When the QE bit of Status Register is set to “1”,
HOLD# pin is not available since it becomes IO3.
When QE bit is “0”, the pin acts as HOLD# regardless of the P7 bit of Read Register.
HOLD# (IO3)
INPUT/OUTPUT
The HOLD# pin allows the device to be paused while it is selected. It pauses serial
communication by the master device without resetting the serial sequence. The
HOLD# pin is active low. When HOLD# is in a low state and CE# is low, the SO pin
will be at high impedance. Device operation can resume when HOLD# pin is brought
to a high state.
RESET#: Dedicated RESET# pin with bit 0 of Function Register was set to “0” from
the factory. The RESET# pin has an internal pull-up resistor and may be left floating
if not used
RESET#
INPUT/OUTPUT
SCK
INPUT
Same as the description in previous page
Vcc
POWER
Same as the description in previous page
GND
GROUND
Same as the description in previous page
NC
Unused
Same as the description in previous page
The RESET# pin is a hardware RESET signal. When RESET# is driven HIGH, the
memory is in the normal operating mode. When RESET# is driven LOW, the
memory enters reset mode and output is High-Z. If RESET# is driven LOW while an
internal WRITE, PROGRAM, or ERASE operation is in progress, data may be lost.
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IS25WP016/080/040/020
3. BLOCK DIAGRAM
Control Logic
High Voltage Generator
Status
Register
I/O Buffers and
Data Latches
256 Bytes
Page Buffer
Serial Peripheral Interface
CE#
SCK
WP#
(IO2)
SI
(IO0)
SO
(IO1)
Y-Decoder
(1)
X-Decoder
HOLD# or RESET#
(IO3)
Memory Array
Address Latch &
Counter
Note1: In case of the device with dedicated RESET# pin, IO3 pin can be switched to HOLD# only when QE bit=0
See the Ordering Information for the dedicated RESET# pin option.
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IS25WP016/080/040/020
4. SPI MODES DESCRIPTION
Multiple IS25WP016/080/040/020 devices can be connected on the SPI serial bus and controlled by a SPI
Master, i.e. microcontroller, as shown in Figure 4.1. The devices support either of two SPI modes:
Mode 0 (0, 0)
Mode 3 (1, 1)
The difference between these two modes is the clock polarity. When the SPI master is in stand-by mode, the
serial clock remains at “0” (SCK = 0) for Mode 0 and the clock remains at “1” (SCK = 1) for Mode 3. Please refer
to Figure 4.2 and Figure 4.3 for SPI and QPI mode. In both modes, the input data is latched on the rising edge
of Serial Clock (SCK), and the output data is available from the falling edge of SCK.
Figure 4.1 Connection Diagram among SPI Master and SPI Slaves (Memory Devices)
SDO
SPI interface with
(0,0) or (1,1)
SDI
SCK
SCK SO
SI
SCK SO
SI
SCK SO
SI
SPI Master
(i.e. Microcontroller)
CS3
CS2
SPI
Memory
Device
CS1
SPI
Memory
Device
CE#
SPI
Memory
Device
CE#
WP# HOLD# or
RESET
(1)
CE#
WP# HOLD# or
RESET#
(1)
WP# HOLD# or
RESET#
(1)
Notes:
1. In case of the device with dedicated RESET# pin, IO3 pin can be switched to HOLD# only when QE bit=0 See the
Ordering Information for the dedicated RESET# pin option.
2. SI and SO pins become bidirectional IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3 respectively
during QPI mode.
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IS25WP016/080/040/020
Figure 4.2 SPI Mode Support
SCK
Mode 0 (0,0)
SCK
Mode 3 (1,1)
MSB
SI
SO
MSB
Figure 4.3 QPI Mode Support
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Mode 0
3-byte Address
Mode Bits
Data 1
Data 2
Data 3
IO0
C4
C0
20
16
12
8
4
0
4
0
4
0
4
0
4
0
...
IO1
C5
C1
21
17
13
9
5
1
5
1
5
1
5
1
5
1
...
IO2
C6
C2
22
18
14
10
6
2
6
2
6
2
6
2
6
2
...
IO3
C71
C3
23 1
19
15
11
7
3
71
3
71
3
71
3
71
3
...
Note1: MSB (Most Significant Bit)
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IS25WP016/080/040/020
5. SYSTEM CONFIGURATION
The memory array is divided into uniform 4 Kbyte sectors or uniform 32/64 Kbyte blocks (a block consists of
eight/sixteen adjacent sectors respectively).
Table 5.1 illustrates the memory map of the device. The Status Register controls how the memory is protected.
5.1 BLOCK/SECTOR ADDRESSES
Table 5.1 Block/Sector Addresses of IS25WP016/080/040/020
Block No.
(64Kbyte)
Memory Density
Block No.
(32Kbyte)
Block 0
Block 0
Block 1
Block 2
Block 1
2Mb
Block 3
:
:
4Mb
Block 6
Block 3
8Mb
Block 7
:
:
Block 14
16Mb
Block 7
Block 15
:
:
Block 30
Block 15
Block 31
:
:
Block 60
Block 30
Block 61
Block 62
Block 31
Block 63
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Sector No.
Sector Size
(Kbytes)
Address Range
Sector 0
:
:
Sector 15
Sector 16
:
:
Sector 31
4
:
:
4
4
:
:
4
000000h – 000FFFh
:
:
00F000h - 00FFFFh
010000h – 010FFFh
:
:
01F000h - 01FFFFh
:
:
:
Sector 48
:
:
Sector 63
4
:
:
4
030000h – 030FFFh
:
:
03F000h – 03FFFFh
:
:
:
Sector 112
:
:
Sector 127
4
:
:
4
070000h – 070FFFh
:
:
07F000h – 07FFFFh
:
:
:
Sector 240
:
:
Sector 255
4
:
:
4
0F0000h – 0F0FFFh
:
:
0FF000h – 0FFFFFh
:
:
:
Sector 480
:
:
Sector 495
Sector 496
:
:
Sector 511
4
:
:
4
4
:
:
4
1E0000h – 1E0FFFh
:
:
1EF000h – 1EFFFFh
1F0000h – 1F0FFFh
:
:
1FF000h – 1FFFFFh
13
IS25WP016/080/040/020
6. REGISTERS
The device has four sets of Registers: Status, Function, Read, and Autoboot.
6.1 STATUS REGISTER
Status Register Format and Status Register Bit Definitions are described in Table 6.1 & Table 6.2.
Table 6.1 Status Register Format
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRWD
QE
BP3
BP2
BP1
BP0
WEL
WIP
0
0
0
0
0
0
0
0
Table 6.2 Status Register Bit Definition
Bit
Name
Bit 0
WIP
Bit 1
WEL
Bit 2
BP0
Bit 3
BP1
Bit 4
BP2
Bit 5
BP3
Bit 6
QE
Bit 7
SRWD
Definition
Write In Progress Bit:
"0" indicates the device is ready(default)
"1" indicates a write cycle is in progress and the device is busy
Write Enable Latch:
"0" indicates the device is not write enabled (default)
"1" indicates the device is write enabled
Block Protection Bit: (See Table 6.4 for details)
"0" indicates the specific blocks are not write-protected (default)
"1" indicates the specific blocks are write-protected
Quad Enable bit:
“0” indicates the Quad output function disable (default)
“1” indicates the Quad output function enable
Status Register Write Disable: (See Table 7.1 for details)
"0" indicates the Status Register is not write-protected (default)
"1" indicates the Status Register is write-protected
Read/Write
Type
R
Volatile
R/W
Volatile
R/W
Non-Volatile
R/W
Non-Volatile
R/W
Non-Volatile
Note1: WEL bit can be written by WREN and WRDI commands, but cannot by WRSR command.
The BP0, BP1, BP2, BP3, QE, and SRWD are non-volatile memory cells that can be written by a Write Status
Register (WRSR) instruction. The default value of the BP0, BP1, BP2, BP3, QE, and SRWD bits were set to “0”
at factory. The Status Register can be read by the Read Status Register (RDSR).
The function of Status Register bits are described as follows:
WIP bit: Write In Progress (WIP) bit is read-only, and can be used to detect the progress or completion of a
Program, Erase, or Write/Set Non-Volatile/OTP Register operation. WIP is set to “1” (busy state) when the
device is executing the operation. During this time the device will ignore further instructions except for Read
Status/Function/Extended Read Register and Software/Hardware Reset instructions. In addition to the
instructions, an Erase/Program Suspend instruction also can be executed during a Program or Erase operation.
When an operation has completed, WIP is cleared to “0” (ready state) whether the operation is successful or not
and the device is ready for further instructions.
WEL bit: Write Enable Latch (WEL) indicates the status of the internal write enable latch. When WEL is “0”, the
write enable latch is disabled and the write operations described in Table 6.3 are inhibited. When WEL bit is “1”,
the write operations are allowed. WEL bit is set by a Write Enable (WREN) instruction. Each write register,
program and erase instruction except for Set volatile Read Register and Set volatile Extended Read Register
must be preceded by a WREN instruction. WEL bit can be reset by a Write Disable (WRDI) instruction. It will
automatically reset after the completion of any write operation.
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IS25WP016/080/040/020
Table 6.3 Instructions requiring WREN instruction ahead
Instructions must be preceded by the WREN instruction
Name
PP
Hex Code
Operation
02h
Serial Input Page Program
PPQ
32h/38h
Quad Input Page Program
SER
D7h/20h
Sector Erase 4KB
BER32 (32KB)
52h
Block Erase 32KB
BER64 (64KB)
D8h
Block Erase 64KB
CER
C7h/60h
Chip Erase
WRSR
01h
Write Status Register
WRFR
42h
Write Function Register
SRPNV
65h
Set Read Parameters (Non-Volatile)
SERPNV
85h
Set Extended Read Parameters (Non-Volatile)
IRER
64h
Erase Information Row
IRP
62h
Program Information Row
WRABR
15h
Write AutoBoot Register
BP3, BP2, BP1, BP0 bits: The Block Protection (BP3, BP2, BP1 and BP0) bits are used to define the portion of
the memory area to be protected. Refer to Table 6.4 for the Block Write Protection (BP) bit settings. When a
defined combination of BP3, BP2, BP1 and BP0 bits are set, the corresponding memory area is protected. Any
program or erase operation to that area will be inhibited.
Note: A Chip Erase (CER) instruction will be ignored unless all the Block Protection Bits are “0”s.
SRWD bit: The Status Register Write Disable (SRWD) bit operates in conjunction with the Write Protection
(WP#) signal to provide a Hardware Protection Mode. When the SRWD is set to “0”, the Status Register is not
write-protected. When the SRWD is set to “1” and the WP# is pulled low (VIL), the bits of Status Register
(SRWD, QE, BP3, BP2, BP1, BP0) become read-only, and a WRSR instruction will be ignored. If the SRWD is
set to “1” and WP# is pulled high (VIH), the Status Register can be changed by a WRSR instruction.
QE bit: The Quad Enable (QE) is a non-volatile bit in the Status Register that allows quad operation. When the
QE bit is set to “0”, the pin WP# and HOLD#/RESET# are enabled. When the QE bit is set to “1”, the IO2 and
IO3 pins are enabled.
WARNING: The QE bit must be set to 0 if WP# or HOLD#/RESET# pin is tied directly to the power supply.
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IS25WP016/080/040/020
Table 6.4 Block (64Kbyte) assignment by Block Write Protect (BP) Bits
Status Register Bits
Protected Memory Area
BP3
BP2
BP1
BP0
16 Mbit
8 Mbit
4 Mbit
2 Mbit
0
0
0
0
None
None
None
None
0
0
0
1
1 block : 31
1 block : 15
1 block : 7
1 block : 3
0
0
1
0
2 blocks : 30 - 31
2 blocks : 14 - 15
2 blocks : 6 - 7
2 blocks : 2 - 3
0
0
1
1
4 blocks : 28 - 31
4 blocks : 12 - 15
4 blocks : 4 - 7
0
1
0
0
8 blocks : 24 - 31
8 blocks : 8 - 15
0
1
0
1
16 blocks : 16 - 31
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
16 blocks : 0 - 15
1
0
1
1
8 blocks : 0 - 7
8 blocks : 0 - 7
1
1
0
0
4 blocks : 0 - 3
4 blocks : 0 - 3
4 blocks : 0 - 3
1
1
0
1
2 blocks : 0 - 1
2 blocks : 0 - 1
2 blocks : 0 - 1
2 blocks : 0 - 1
1
1
1
0
1 block : 0
1 block : 0
1 block : 0
1 block : 0
1
1
1
1
None
None
None
None
All Blocks
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All Blocks
16
IS25WP016/080/040/020
6.2 FUNCTION REGISTER
Function Register Format and Bit definition are described in Table 6.5 and Table 6.6.
Table 6.5 Function Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
IRL3
IRL2
IRL1
IRL0
ESUS
PSUS
Reserved
0
0
0
0
0
0
0
Default
Bit 0
RESET#
Enable/Disable
0 or 1
Table 6.6 Function Register Bit Definition
Bit
Name
Bit 0
RESET#
Enable/Disable
Bit 1
Reserved
Bit 2
PSUS
Bit 3
ESUS
Bit 4
IR Lock 0
Bit 5
IR Lock 1
Bit 6
IR Lock 2
Bit 7
IR Lock 3
Definition
RESET# Enable/Disable
“0” indicates Enable dedicated RESET#
“1” indicates Disable dedicated RESET#
Reserved
Program suspend bit:
“0” indicates program is not suspend
“1” indicates program is suspend
Erase suspend bit:
"0" indicates Erase is not suspend
"1" indicates Erase is suspend
Lock the Information Row 0:
“0” indicates the Information Row can be programmed
“1” indicates the Information Row cannot be programmed
Lock the Information Row 1:
“0” indicates the Information Row can be programmed
“1” indicates the Information Row cannot be programmed
Lock the Information Row 2:
“0” indicates the Information Row can be programmed
“1” indicates the Information Row cannot be programmed
Lock the Information Row 3:
“0” indicates the Information Row can be programmed
“1” indicates the Information Row cannot be programmed
Read
/Write
Type
R/W for 0
R for 1
OTP
R
Reserved
R
Volatile
R
Volatile
R/W
OTP
R/W
OTP
R/W
OTP
R/W
OTP
Note: Once OTP bits of Function Register are written to “1”, it cannot be modified to “0” any more.
”.
RESET# Enable/Disable: The default of the bit is dependent on device. The devices with dedicated RESET#
pin in 16-pin SOIC and 24-ball TFBGA packages will default to “0” from factory for enabling dedicated RESET#
pin. All other parts will default to “1”. If the bit defaults to “1” or programmed to “1”, it can’t be programmed to “0”
again.
PSUS bit: The Program Suspend Status bit indicates when a Program operation has been suspended. The
PSUS changes to “1” after a suspend command is issued during the program operation. Once the suspended
Program resumes, the PSUS bit is reset to “0”.
ESUS bit: The Erase Suspend Status bit indicates when an Erase operation has been suspended. The ESUS
bit is “1” after a suspend command is issued during an Erase operation. Once the suspended Erase resumes,
the ESUS bit is reset to “0”.
IR Lock bit 0 ~ 3: The Information Row Lock bits are programmable. If the bit set to “1”, the Information Row
can’t be programmed.
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IS25WP016/080/040/020
6.3 READ REGISTER AND EXTENDED REGISTER
Read Register format and Bit definitions are described below. Read Register and Extended Read Register
consist of a pair of rewritable non-volatile register and volatile register, respectively. During power up sequence,
volatile register will be loaded with the value of non-volatile value.
6.3.1 READ REGISTER
Table 6.7 and Table 6.8 define all bits that control features in SPI/QPI modes. HOLD#/RESET# pin selection
(P7) bit is used to select HOLD# pin or RESET# pin when QE bit is set to “0” in the standard devices. For 16-pin
SOIC or 24-ball TFBGA package devices with dedicated RESET# pin (or ball) will select HOLD# only regardless
of P7 bit setting.
The Dummy Cycle bits (P6, P5, P4, P3) define how many dummy cycles are used during various READ modes.
The wrap selection bits (P2, P1, P0) define burst length with an enable bit.
The SET READ PARAMETERS Operations (SRPNV: 65h, SRPV: C0h or 63h) are used to set all the Read
Register bits, and can thereby define HOLD#/RESET# pin selection, dummy cycles, and burst length with wrap
around. SRPNV is used to set the non-volatile register and SRPV is used to set the volatile register.
Table 6.7 Read Register Parameter Bit Table
Default
P7
HOLD#/
RESET#
0
P6
Dummy
Cycles
0
P5
Dummy
Cycles
0
P4
Dummy
Cycles
0
P3
Dummy
Cycles
0
P2
Wrap
Enable
0
P1
Burst
Length
0
P0
Burst
Length
0
Table 6.8 Read Register Bit Definition
Read/Write
Bit
Name
P0
Burst Length
Burst Length
R/W
P1
Burst Length
Burst Length
R/W
P2
Burst Length
Set Enable
Burst Length Set Enable Bit:
"0" indicates disable (default)
"1" indicates enable
R/W
P3
Dummy Cycles
P4
Dummy Cycles
P5
Dummy Cycles
P6
Dummy Cycles
P7
HOLD#/
RESET#
Definition
Type
Non-Volatile
and Volatile
Non-Volatile
and Volatile
Non-Volatile
and Volatile
Non-Volatile
and Volatile
Non-Volatile
and Volatile
Non-Volatile
and Volatile
Non-Volatile
and Volatile
R/W
Number of Dummy Cycles:
Bits1 to Bit4 can be toggled to select the number of dummy cycles
(1 to 15 cycles)
R/W
R/W
R/W
HOLD#/RESET# pin selection bit when QE bit = “0”:
"0" indicates the HOLD# pin is selected (default)
"1" indicates the RESET# pin is selected
“X” for the device with dedicated RESET# function (selects HOLD#
only)
Non-Volatile
and Volatile
R/W
Table 6.9 Burst Length Data
P1
P0
8 bytes
0
0
16 bytes
0
1
32 bytes
1
0
64 bytes
1
1
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IS25WP016/080/040/020
Table 6.10 Wrap Function
Wrap around boundary
P2
Whole array regardless of P1 and P0 value
0
Burst Length set by P1 and P0
1
Table 6.11 Read Dummy Cycles vs Max Frequency
P[6:3]
Dummy
Cycles2,3
1
Fast Read5 Fast Read5
0Bh
0Bh
Fast Read
Dual
Output
3Bh
Fast Read
Dual IO
BBh
Fast Read
Quad
Output
6Bh
Fast Read
Quad IO
EBh
FRDTR
0Dh
FRDDTR
BDh
FRQDTR
EDh
SPI
QPI
SPI
SPI
SPI
SPI, QPI
SPI/QPI
SPI4
SPI, QPI
133MHz
104MHz
133MHz
115MHz
133MHz
104MHz
66/66MHz
66MHz
66MHz
0
Default
1
1
84MHz
33MHz
84MHz
60MHz
66MHz
33MHz
50/20MHz
33MHz
20MHz
2
2
104MHz
50MHz
104MHz
84MHz
80MHz
50MHz
66/33MHz
50MHz
33MHz
3
3
133MHz
60MHz
115MHz
104MHz
90MHz
60MHz
66/46MHz
66MHz
46MHz
4
4
133MHz
70MHz
128MHz
115MHz
104MHz
70MHz
66/60MHz
66MHz
60MHz
5
5
133MHz
84MHz
133MHz
128MHz
115MHz
84MHz
66/66MHz
66MHz
66MHz
6
6
133MHz
104MHz
133MHz
133MHz
128MHz
104MHz
66/66MHz
66MHz
66MHz
7
7
133MHz
115MHz
133MHz
133MHz
133MHz
115MHz
66/66MHz
66MHz
66MHz
8
8
133MHz
133MHz
133MHz
133MHz
133MHz
128MHz
66/66MHz
66MHz
66MHz
9
9
133MHz
133MHz
133MHz
133MHz
133MHz
133MHz
66/66MHz
66MHz
66MHz
10
10
133MHz
133MHz
133MHz
133MHz
133MHz
133MHz
66/66MHz
66MHz
66MHz
11
11
133MHz
133MHz
133MHz
133MHz
133MHz
133MHz
66/66MHz
66MHz
66MHz
12
12
133MHz
133MHz
133MHz
133MHz
133MHz
133MHz
66/66MHz
66MHz
66MHz
13
13
133MHz
133MHz
133MHz
133MHz
133MHz
133MHz
66/66MHz
66MHz
66MHz
14
14
133MHz
133MHz
133MHz
133MHz
133MHz
133MHz
66/66MHz
66MHz
66MHz
15
15
133MHz
133MHz
133MHz
133MHz
133MHz
133MHz
66/66MHz
66MHz
66MHz
Notes:
1. Default dummy cycles are as follows.
Operation
Command
Dummy Cycles
Normal mode
DTR mode
Normal mode
DTR mode
Fast Read SPI
0Bh
0Dh
8
8
Fast Read QPI
0Bh
0Dh
6
6
Fast Read Dual Output
3Bh
-
8
-
Fast Read Dual IO SPI
BBh
BDh
4
4
Fast Read Quad Output
6Bh
-
8
-
Fast Read Quad IO SPI, QPI
EBh
EDh
6
6
Comment
RDUID, RDSFDP, IRRD instructions
are also applied.
2. Enough number of dummy cycles must be applied to execute properly the AX read operation.
3. Must satisfy bus I/O contention. For instance, if the number of dummy cycles and AX bit cycles are same, then X
must be Hi-Z.
4. QPI is not available for FRDDTR command.
5. RDUID, RDSFDP, IRRD instructions are also applied.
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IS25WP016/080/040/020
6.3.2 EXTENDED READ REGISTER
Table 6.12 and Table 6.13 define all bits that control features in SPI/QPI modes. The ODS2, ODS1, ODS0
(EB7, EB6, EB5) bits provide a method to set and control driver strength. The five bits (EB4, EB3, EB2, EB1,
EB0) remain reserved for future use.
The SET EXTENDED READ PARAMETERS Operations (SERPNV: 85h, SERPV: 83h) are used to set all the
Extended Read Register bits, and can thereby define the output driver strength used during READ modes.
SRPNV is used to set the non-volatile register and SRPV is used to set the volatile register.
Table 6.12 Extended Read Register Bit Table
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
ODS2
ODS1
ODS0
Reserved
Reserved
Reserved
Reserved
Reserved
1
1
1
1
1
1
1
1
Read/Write
Type
Default
Table 6.13 Extended Read Register Bit Definition
Bit
Name
Definition
EB0
Reserved
Reserved
R
Reserved
EB1
Reserved
Reserved
R
Reserved
EB2
Reserved
Reserved
R
Reserved
EB3
Reserved
Reserved
R
Reserved
EB4
Reserved
Reserved
R
Reserved
EB5
ODS0
EB6
ODS1
EB7
ODS2
R/W
Output Driver Strength:
Output Drive Strength can be selected according to Table 6.14
R/W
R/W
Non-Volatile
and Volatile
Non-Volatile
and Volatile
Non-Volatile
and Volatile
Table 6.14 Driver Strength Table
ODS2
ODS1
ODS0
Description
0
0
0
Reserved
0
0
1
12.50%
0
1
0
25%
0
1
1
37.50%
1
0
0
Reserved
1
0
1
75%
1
1
0
100%
1
1
1
50%
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20
IS25WP016/080/040/020
6.4 AUTOBOOT REGISTER
AutoBoot Register Bit (32 bits) Definitions are described in Table 6.15.
Table 6.15 AutoBoot Register Parameter Bit Table
Bits
Symbols
Function
Type
Default
Value
AB[31:24]
ABSA
Reserved
Reserved
00h
AB[23:5]
ABSA
AutoBoot Start
Address
NonVolatile
00000h
AB[4:1]
ABSD
AutoBoot Start
Delay
NonVolatile
0h
AB0
ABE
AutoBoot
Enable
NonVolatile
0
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Description
Reserved for future use
32 byte boundary address for the start of boot
code access
Number of initial delay cycles between CE# going
low and the first bit of boot code being transferred,
and it is the same as dummy cycles of FRD
(QE=0) or FRQIO (QE=1).
Example: The number of initial delay cycles is 8
(QE=0) or 6 (QE=1) when AB[4:1]=00h (Default
setting).
1 = AutoBoot is enabled
0 = AutoBoot is not enabled
21
IS25WP016/080/040/020
7. PROTECTION MODE
The device supports hardware and software write-protection mechanisms.
7.1 HARDWARE WRITE PROTECTION
The Write Protection (WP#) pin provides a hardware write protection method for BP3, BP2, BP1, BP0, SRWD,
and QE in the Status Register. Refer to the section 6.1 STATUS REGISTER.
Write inhibit voltage (VWI) is specified in the section 9.8 POWER-UP AND POWER-DOWN. All write sequence
will be ignored when Vcc drops to VWI.
Table 7.1 Hardware Write Protection on Status Register
SRWD
WP#
Status Register
0
Low
Writable
1
Low
Protected
0
High
Writable
1
High
Writable
Note: Before the execution of any program, erase or write Status Register instruction, the Write Enable Latch (WEL)
bit must be enabled by executing a Write Enable (WREN) instruction. If the WEL bit is not enabled, the
program, erase or write register instruction will be ignored.
7.2 SOFTWARE WRITE PROTECTION
The device also provides a software write protection feature. The Block Protection (BP3, BP2, BP1, BP0) bits
allow part or the whole memory area to be write-protected.
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IS25WP016/080/040/020
8. DEVICE OPERATION
The device utilizes an 8-bit instruction register. Refer to Table 8.1. Instruction Set for details on instructions and
instruction codes. All instructions, addresses, and data are shifted in with the most significant bit (MSB) first on
Serial Data Input (SI) or Serial Data IOs (IO0, IO1, IO2, IO3). The input data on SI or IOs is latched on the rising
edge of Serial Clock (SCK) for normal mode and both of rising and falling edges for DTR mode after Chip
Enable (CE#) is driven low (VIL). Every instruction sequence starts with a one-byte instruction code and is
followed by address bytes, data bytes, or both address bytes and data bytes, depending on the type of
instruction. CE# must be driven high (VIH) after the last bit of the instruction sequence has been shifted in to end
the operation.
Table 8.1 Instruction Set
Instruction
Name
Operation
Mode
Byte0
Byte1
Byte2
Byte3
Byte4
NORD
Normal Read
Mode
SPI
03h
A
A
A
Data out
FRD
Fast Read
Mode
SPI
QPI
0Bh
SPI
BBh
AXh(1),(2)
Dual
Dual
Data out
FRDO
Fast Read
Dual Output
SPI
3Bh
Dummy(1)
Byte
Dual
Data out
FRQIO
Fast Read
Quad I/O
SPI
QPI
EBh
AXh(1), (2)
Quad
Quad
Data out
FRQO
Fast Read
Quad Output
SPI
6Bh
A
A
Dual
A
A
Quad
A
Data out
Fast Read
Dual I/O
A
A
Dual
A
A
Quad
A
Dummy(1)
Byte
FRDIO
A
A
Dual
A
A
Quad
A
Dummy(1)
Byte
Quad
Data out
FRDTR
Fast Read
DTR Mode
SPI
QPI
0Dh
SPI
BDh
AXh(1), (2)
Dual
Dual
Data out
FRQDTR
Fast Read
Quad I/O DTR
SPI
QPI
EDh
A
A
Dual
A
Dual
Data out
Fast Read
Dual I/O DTR
A
A
Dual
A
Dummy(1)
Byte
FRDDTR
A
A
Dual
A
AXh(1), (2)
Quad
Quad
Data out
PP
Input Page
Program
SPI
QPI
02h
A
A
A
PD
(256byte)
PPQ
Quad Input
Page Program
SPI
32h
38h
A
A
A
Quad PD
(256byte)
SER
Sector Erase
SPI
QPI
D7h
20h
A
A
A
BER32
(32KB)
Block Erase
32Kbyte
SPI
QPI
52h
A
A
A
BER64
(64KB)
Block Erase
64Kbyte
SPI
QPI
D8h
A
A
A
CER
Chip Erase
SPI
QPI
C7h
60h
WREN
Write Enable
SPI
QPI
06h
WRDI
Write Disable
SPI
QPI
04h
RDSR
Read Status
Register
SPI
QPI
05h
SR
WRSR
Write Status
Register
SPI
QPI
01h
WSR
Data
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Byte5
Byte6
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IS25WP016/080/040/020
Instruction
Name
Operation
Mode
Byte0
Byte1
RDFR
Read Function
Register
SPI
QPI
48h
Data
out
WRFR
Write Function
Register
SPI
QPI
42h
WFR
Data
QPIEN
Enter
QPI mode
SPI
35h
QPIDI
Exit
QPI mode
QPI
F5h
PERSUS
Suspend during
program/erase
SPI
QPI
75h
B0h
PERRSM
Resume
program/erase
SPI
QPI
7Ah
30h
Deep Power
Down
Read ID /
Release
Power Down
Set Read
Parameters
(Non-Volatile)
Set Read
Parameters
(Volatile)
Set Extended
Read
Parameters
(Non-Volatile)
Set Extended
Read
Parameters
(Volatile)
Read Read
Parameters
(Non-Volatile)
Read
Extended Read
Parameters
(Non-Volatile)
SPI
QPI
B9h
SPI
QPI
ABh
XXh(3)
SPI
QPI
65h
Data in
SPI
QPI
C0h
63h
Data in
SPI
QPI
85h
Data in
SPI
QPI
83h
Data in
SPI
QPI
61h
Data out
SPI
QPI
81h
Data out
DP
RDID,
RDPD
SRPNV
SRPV
SERPNV
SERPV
RDRPNV
RDERPNV
Byte2
Byte3
Byte4
XXh(3)
XXh(3)
ID7-ID0
ID7-ID0
RDJDID
Read JEDEC
ID Command
SPI
9Fh
MF7-MF0
ID15-ID8
RDMDID
Read
Manufacturer
& Device ID
SPI
QPI
90h
XXh(3)
XXh(3)
RDJDIDQ
Read JEDEC ID
QPI mode
QPI
AFh
MF7-MF0
ID15-ID8
ID7-ID0
RDUID
Read
Unique ID
SPI
QPI
4Bh
A(4)
A(4)
RDSFDP
SFDP Read
SPI
QPI
5Ah
A
A
NOP
No Operation
SPI
QPI
00h
RSTEN
Software
Reset
Enable
SPI
QPI
66h
RST
Software Reset
SPI
QPI
99h
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Byte5
00h
MF7-MF0
ID7-ID0
01h
ID7-ID0
MF7-MF0
A(4)
Dummy
Byte
Data out
A
Dummy
Byte
Data out
Byte6
24
IS25WP016/080/040/020
Instruction
Name
IRER
IRP
IRRD
Operation
Erase
Information
Row
Program
Information
Row
Read
Information
Row
Mode
Byte0
Byte1
Byte2
Byte3
SPI
QPI
64h
A
A
A
SPI
QPI
62h
A
A
A
PD
(256byte)
SPI
QPI
68h
A
A
A
Dummy
Byte
A
A
A
Data in 1
Data in 2
Data in 3
SECUNLOCK
Sector Unlock
SPI
QPI
26h
SECLOCK
Sector Lock
SPI
QPI
24h
RDABR
Read AutoBoot
Register
SPI
QPI
14h
WRABR
Write AutoBoot
Register
SPI
QPI
15h
Byte4
Byte5
Byte6
Data out
Data in 4
Notes:
1. The number of dummy cycles depends on the value setting in the Table 6.11 Read Dummy Cycles.
2. AXh has to be counted as a part of dummy cycles. X means “don’t care”.
3. XX means “don’t care”.
4. A are “don’t care” and A are always “0”.
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IS25WP016/080/040/020
8.1 NORMAL READ OPERATION (NORD, 03h)
The NORMAL READ (NORD) instruction is used to read memory contents at a maximum frequency of 50MHz.
The NORD instruction code is transmitted via the SI line, followed by three address bytes (A23 - A0) of the first
memory location to be read. A total of 24 address bits are shifted in, but only AMSB (most significant bit) - A0 are
decoded. The remaining bits (A23 – AMSB+1) are ignored. The first byte addressed can be at any memory
location. Upon completion, any data on the SI will be ignored. Refer to Table 8.2 for the related Address Key.
The first byte data (D7 - D0) is shifted out on the SO line, MSB first. A single byte of data, or up to the whole
memory array, can be read out in one NORMAL READ instruction. The address is automatically incremented by
one after each byte of data is shifted out. The read operation can be terminated at any time by driving CE# high
(VIH) after the data comes out. When the highest address of the device is reached, the address counter will roll
over to the 000000h address, allowing the entire memory to be read in one continuous READ instruction.
If the NORMAL READ instruction is issued while an Erase, Program or Write operation is in process (WIP=1)
the instruction is ignored and will not have any effects on the current operation .
Table 8.2 Address Key
Address
16Mb
8Mb
4Mb
2Mb
AMSB–A0
A20-A0 (A23-A21=X)
A19-A0 (A23-A20=X)
A18-A0 (A23-A19=X)
A17-A0 (A23-A18=X)
Note: X=Don’t Care
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IS25WP016/080/040/020
Figure 8.1 Normal Read Sequence
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
...
28
29
30
31
0
SCK
Mode 0
3-byte Address
SI
Instruction = 03h
23
22
...
21
3
2
1
45
46
47
High Impedance
SO
CE #
32
33
34
35
36
37
39
38
40
41
42
43
44
...
SCK
SI
Data Out 1
SO
tV
7
6
5
4
3
Data Out 2
2
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1
0
7
6
5
4
3
2
1
0
...
27
IS25WP016/080/040/020
8.2 FAST READ OPERATION (FRD, 0Bh)
The FAST READ (FRD) instruction is used to read memory data at up to a 133MHz clock.
The FAST READ instruction code is followed by three address bytes (A23 - A0) and dummy cycles
(configurable, default is 8 clocks), transmitted via the SI line, with each bit latched-in during the rising edge of
SCK. Then the first data byte from the address is shifted out on the SO line, with each bit shifted out at a
maximum frequency fCT, during the falling edge of SCK.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FAST READ instruction. The FAST
READ instruction is terminated by driving CE# high (VIH).
If the FAST READ instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the
instruction is ignored without affecting the current cycle.
Figure 8.2 Fast Read Sequence
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
...
28
29
30
31
SCK
Mode 0
3-byte Address
SI
Instruction = 0Bh
31
30
41
42
29
...
3
2
1
0
44
45
46
47
...
High Impedance
SO
CE #
32
33
34
35
36
37
38
39
40
43
SCK
SI
Dummy Cycles
Data Out
tV
SO
7
6
5
4
3
2
1
0
...
Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.
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IS25WP016/080/040/020
FAST READ QPI OPERATION (FRD QPI, 0Bh)
The FAST READ QPI (FRD QPI) instruction is used to read memory data at up to a 133MHz clock.
The FAST READ QPI instruction code (2 clocks) is followed by three address bytes (A23-A0 — 6 clocks) and
dummy cycles (configurable, default is 6 cycles), transmitted via the IO3, IO2, IO1 and IO0 lines, with each bit
latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out on the IO3, IO2, IO1
and IO0 lines, with each bit shifted out at a maximum frequency f CT, during the falling edge of SCK.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FAST READ QPI instruction. The FAST
READ QPI instruction is terminated by driving CE# high (VIH).
If the FAST READ QPI instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the
instruction is ignored without affecting the current cycle.
The Fast Read QPI sequence is also applied to the commands in the following table 8.3.
Table 8.3 Instructions that Fast Read QPI sequence is applied to
Instruction Name
FRQIO
RDUID
RDSFDP
IRRD
Operation
Hex Code
Fast Read Quad I/O
Read Unique ID
SFDP Read
Read Information Row
EBh
4Bh
5Ah
68h
Figure 8.3 Fast Read QPI Sequence
CE#
Mode 3 0
1
2
3
4
5
6
7
8
9
...
13
14
15
16
17
...
SCK
Mode 0
tV
IO[3:0]
0Bh
Instruction
23:20 19:16 15:12 11:8
3-byte Address
7:4
3:0
7:4
6 Dummy Cycles
3:0
Data 1
7:4
3:0
...
Data 2
Note: Number of dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read
Dummy Cycles.
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IS25WP016/080/040/020
8.3 HOLD OPERATION
HOLD# is used in conjunction with CE# to select the device. When the device is selected and a serial sequence
is underway, HOLD# can be used to pause the serial communication with the master device without resetting
the serial sequence. To pause, HOLD# is brought low while the SCK signal is low. To resume serial
communication, HOLD# is brought high while the SCK signal is low (SCK may still toggle during HOLD). Inputs
to SI will be ignored while SO is in the high impedance state, during HOLD.
Note: HOLD is not supported in DTR mode or with QE=1 or when RESET# is selected for the HOLD# or RESET# pin.
Timing graph can be referenced in AC Parameters Figure 9.4.
8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBh)
The FRDIO allows the address bits to be input two bits at a time. This may allow for code to be executed directly
from the SPI in some applications.
The FRDIO instruction code is followed by three address bytes (A23 – A0) and dummy cycles (configurable,
default is 4 clocks), transmitted via the IO1 and IO0 lines, with each pair of bits latched-in during the rising edge
of SCK. The address MSB is input on IO1, the next bit on IO0, and this shift pattern continues to alternate
between the two lines. Depending on the usage of AX read operation mode, a mode byte may be located after
address input.
The first data byte addressed is shifted out on the IO1 and IO0 lines, with each pair of bits shifted out at a
maximum frequency fCT, during the falling edge of SCK. The MSB is output on IO1, while simultaneously the
second bit is output on IO0. Figure 8.4 illustrates the timing sequence.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FRDIO instruction. FRDIO instruction is
terminated by driving CE# high (VIH).
The device supports the AX read operation by applying mode bits during dummy period. Mode bits consist of 8
bits, such as M7 to M0. Four cycles after address input are reserved for Mode bits in FRDIO execution. M7 to
M4 are important for enabling this mode. M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah), it
enables the AX read operation and subsequent FRDIO execution skips command code. It saves cycles as
described in Figure 8.5. When the code is different from AXh (where X is don’t care), the device exits the AX
read operation. After finishing the read operation, device becomes ready to receive a new command. SPI or QPI
mode configuration retains the prior setting. Mode bit must be applied during dummy cycles. Number of dummy
cycles in Table 6.11 includes number of mode bit cycles. If dummy cycles are configured as 4 cycles, data
output will start right after mode bit is applied.
If the FRDIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not affect the current cycle.
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IS25WP016/080/040/020
Figure 8.4 Fast Read Dual I/O Sequence (with command decode cycles)
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
...
18
19
20
21
SCK
Mode 0
4 Dummy Cycles
3-byte Address
IO0
Instruction = BBh
22
20
18
...
2
0
6
4
23
21
19
...
3
1
7
5
High Impedance
IO1
Mode Bits
CE #
22
23
24
25
26
27
29
28
30
31
32
33
34
35
36
37
...
SCK
tV
IO0
2
0
6
4
2
0
6
Data Out 1
IO1
3
1
7
5
3
4
2
0
6
Data Out 2
1
7
5
3
4
2
0
6
4
...
1
7
5
...
Data Out 3
1
7
5
3
Mode Bits
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bit cycles
are same, then X should be Hi-Z.
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IS25WP016/080/040/020
Figure 8.5 Fast Read Dual I/O AX Read Sequence (without command decode cycles)
CE #
Mode 3 0
1
2
3
...
11
12
13
14
15
16
17
18
19
20
...
21
SCK
Mode 0
4 Dummy Cycles
3-byte Address
tV
Data Out 2
Data Out 1
IO0
22
20
18
...
2
0
6
4
2
0
6
4
2
0
6
4
...
IO1
23
21
19
...
3
1
7
5
3
1
7
5
3
1
7
5
...
Mode Bits
Notes:
1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When
the mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bit cycles
are same, then X should be Hi-Z.
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IS25WP016/080/040/020
8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh)
The FRDO instruction is used to read memory data on two output pins each at up to a 133MHz clock.
The FRDO instruction code is followed by three address bytes (A23 – A0) and dummy cycles (configurable,
default is 8 clocks), transmitted via the IO0 line, with each bit latched-in during the rising edge of SCK. Then the
first data byte addressed is shifted out on the IO1 and IO0 lines, with each pair of bits shifted out at a maximum
frequency fCT, during the falling edge of SCK. The first bit (MSB) is output on IO1. Simultaneously, the second
bit is output on IO0.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FRDO instruction. The FRDO instruction
is terminated by driving CE# high (VIH).
If the FRDO instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction
is ignored and will not have any effects on the current cycle.
Figure 8.6 Fast Read Dual Output Sequence
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
...
28
29
30
31
SCK
Mode 0
3-byte Address
IO0
Instruction = 3Bh
23
22
41
42
21
...
3
2
1
0
44
45
46
47
...
High Impedance
IO1
CE #
32
33
34
35
36
37
38
39
40
43
SCK
tV
IO0
6
2
0
6
Data Out 1
8 Dummy Cycles
IO1
4
7
5
3
4
2
0
...
1
...
Data Out 2
1
7
5
3
Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.
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IS25WP016/080/040/020
8.6 FAST READ QUAD OUTPUT OPERATION (FRQO, 6Bh)
The FRQO instruction is used to read memory data on four output pins each at up to a 133 MHz clock.
The FRQO instruction code is followed by three address bytes (A23 – A0) and dummy cycles (configurable,
default is 8 clocks), transmitted via the IO0 line, with each bit latched-in during the rising edge of SCK. Then
the first data byte addressed is shifted out on the IO3, IO2, IO1 and IO0 lines, with each group of four bits
shifted out at a maximum frequency fCT, during the falling edge of SCK. The fi rst bit (MSB) is output on IO3,
while simultaneously the second bit is output on IO2, the third bit is output on IO1, etc.
The first byte addressed can be at any memory location. The address is automatically incremented after each
byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FRQO instruction. FRQO instruction is
terminated by driving CE# high (VIH).
If a FRQO instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction
is ignored and will not have any effects on the current cycle.
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IS25WP016/080/040/020
Figure 8.7 Fast Read Quad Output Sequence
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
...
28
29
30
31
SCK
Mode 0
3-byte Address
IO0
Instruction = 6Bh
23
22
41
42
21
...
3
2
1
0
44
45
46
47
...
High Impedance
IO1
High Impedance
IO2
High Impedance
IO3
CE #
32
33
34
35
36
37
38
39
40
43
SCK
tV
IO0
4
8 Dummy Cycles
0
4
0
4
0
4
0
...
Data Out 1 Data Out 2 Data Out 3 Data Out 4
IO1
5
1
5
1
5
1
5
1
...
IO2
6
2
6
2
6
2
6
2
...
IO3
7
3
7
3
7
3
7
3
...
Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.
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IS25WP016/080/040/020
8.7 FAST READ QUAD I/O OPERATION (FRQIO, EBh)
The FRQIO instruction allows the address bits to be input four bits at a time. This may allow for code to be
executed directly from the SPI in some applications.
The FRQIO instruction code is followed by three address bytes (A23 – A0) and dummy cycles (configurable,
default is 6 clocks), transmitted via the IO3, IO2, IO1 and IO0 lines, with each group of four bits latched-in during
the rising edge of SCK. The address of MSB inputs on IO3, the next bit on IO2, the next bit on IO1, the next bit
on IO0, and continue to shift in alternating on the four. Depending on the usage of AX read operation mode, a
mode byte may be located after address input.
The first data byte addressed is shifted out on the IO3, IO2, IO1 and IO0 lines, with each group of four bits
shifted out at a maximum frequency f CT, during the falling edge of SCK. The first bit (MSB) is output on IO3,
while simultaneously the second bit is output on IO2, the third bit is output on IO1, etc. Figure 8.8 illustrates the
timing sequence.
The first byte addressed can be at any memory location. The address is automatically incremented after each
byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FRQIO instruction. FRQIO instruction is
terminated by driving CE# high (VIH).
The device supports the AX read operation by applying mode bits during dummy period. Mode bits consist of 8
bits, such as M7 to M0. Two cycles after address input are reserved for Mode bits in FRQIO execution. M7 to
M4 are important for enabling this mode. M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah), it
enables the AX read operation and subsequent FRQIO execution skips command code. It saves cycles as
described in Figure 8.9. When the code is different from AXh (where X is don’t care), the device exits the AX
read operation. After finishing the read operation, device becomes ready to receive a new command. SPI or QPI
mode configuration retains the prior setting. Mode bit must be applied during dummy cycles. Number of dummy
cycles in Table 6.11 includes number of mode bit cycles. If dummy cycles are configured as 6 cycles, data
output will start right after mode bits and 4 additional dummy cycles are applied.
If the FRQIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not have any effects on the current cycle.
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IS25WP016/080/040/020
Figure 8.8 Fast Read Quad I/O Sequence (with command decode cycles)
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
11
12
13
14
15
SCK
Mode 0
3-byte Address
IO0
20
16
12
8
4
0
4
0
21
17
13
9
5
1
5
1
IO2
22
18
14
10
6
2
6
2
IO3
23
19
15
11
7
3
7
3
Instruction = EBh
High Impedance
IO1
Mode Bits
CE #
16
17
18
19
20
21
23
22
24
25
26
27
28
29
30
31
...
SCK
6 Dummy Cycles
tV Data Out 1 Data Out 2 Data Out 3 Data Out 4 Data Out 5 Data Out 6
IO0
4
0
4
0
4
0
4
0
4
0
4
0
...
IO1
5
1
5
1
5
1
5
1
5
1
5
1
...
6
2
6
2
6
2
6
2
6
2
6
2
...
7
3
7
3
7
3
7
3
7
3
7
3
...
IO2
IO3
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bit cycles
are same, then X should be Hi-Z.
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Figure 8.9 Fast Read Quad I/O AX Read Sequence (without command decode cycles)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
...
SCK
Mode 0
6 Dummy Cycles
3-byte Address
tV
Data Out 1 Data Out 2
IO0
20
16
12
8
4
0
4
0
4
0
4
0
...
IO1
21
17
13
9
5
1
5
1
5
1
5
1
...
IO2
22
18
14
10
6
2
6
2
6
2
6
2
...
IO3
23
19
15
11
7
3
7
3
7
3
7
3
...
Mode Bits
Notes:
1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When
the mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bit cycles
are same, then X should be Hi-Z.
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FAST READ QUAD I/O QPI OPERATION (FRQIO QPI, EBh)
The FRQIO QPI instruction is used to read memory data at up to a 133MHz clock.
The FRQIO QPI instruction utilizes all four IO lines to input the instruction code so that only two clocks are
required, while the FRQIO instruction requires that the byte-long instruction code is shifted into the device only
via IO0 line in eight clocks. As a result, 6 command cycles will be reduced by the FRQIO QPI instruction. In
addition, subsequent address and data out are shifted in/out via all four IO lines like the FRQIO instruction. In
fact, except for the command cycle, the FRQIO QPI operation is exactly same as the FRQIO.
The device supports the AX read operation by applying mode bits during dummy period. Mode bits consist of 8
bits, such as M7 to M0. Two cycles after address input are reserved for Mode bits in FRQIO execution. M7 to
M4 are important for enabling this mode. M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah), it
enables the AX read operation and subsequent FRQIO execution skips command code. It saves cycles as
described in Figure 8.9. When the code is different from AXh (where X is don’t care), the device exits the AX
read operation. After finishing the read operation, device becomes ready to receive a new command. SPI or QPI
mode configuration retains the prior setting. Mode bit must be applied during dummy cycles. Number of dummy
cycles in Table 6.11 includes number of mode bit cycles. If dummy cycles are configured as 6 cycles, data
output will start right after mode bits and 4 additional dummy cycles are applied.
If the FRQIO QPI instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the
instruction is ignored and will not have any effects on the current cycle.
Figure 8.10 Fast Read Quad I/O QPI Sequence
CE#
Mode 3 0
1
2
3
4
5
6
7
8
9
...
13
14
15
16
17
...
SCK
Mode 0
Mode Bits
IO[3:0]
EBh
Instruction
23:20 19:16 15:12 11:8
3-byte Address
7:4
3:0
7:4
3:0
6 Dummy Cycles
tV
7:4
3:0
Data 1
7:4
3:0
...
Data 2
Note: Number of dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read
Dummy Cycles.
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8.8 PAGE PROGRAM OPERATION (PP, 02h)
The Page Program (PP) instruction allows up to 256 bytes data to be programmed into memory in a single
operation. The destination of the memory to be programmed must be outside the protected memory area set by
the Block Protection (BP3, BP2, BP1, BP0) bits. A PP instruction which attempts to program into a page that is
write-protected will be ignored. Before the execution of PP instruction, the Write Enable Latch (WEL) must be
enabled through a Write Enable (WREN) instruction.
The PP instruction code, three address bytes and program data (1 to 256 bytes) are input via the Sl line.
Program operation will start immediately after the CE# is brought high, otherwise the PP instruction will not be
executed. The internal control logic automatically handles the programming voltages and timing. During a
program operation, all instructions will be ignored except the RDSR instruction. The progress or completion of
the program operation can be determined by reading the WIP bit in Status Register via a RDSR instruction. If
the WIP bit is “1”, the program operation is still in progress. If WIP bit is “0”, the program operation has
completed.
If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the
previously latched data are discarded, and the last 256 bytes are kept to be programmed into the page. The
starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap
around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all
other bytes on the same page will remain unchanged.
Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s.
A byte cannot be reprogrammed without first erasing the whole sector or block.
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Figure 8.11 Page Program Sequence
1
...
7
8
9
...
31
32
33
...
39
...
...
2079
Mode 3 0
2072
CE #
SCK
Mode 0
SI
3-byte Address
Instruction = 02h
23
Data In 1
Data In 256
22
...
0
7
6
...
0
...
7
...
0
5
6
7
8
9
10
11
12
13
14
15
...
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
7:4
3:0
...
High Impedance
SO
Figure 8.12 Page Program QPI Sequence
CE#
Mode 3 0
1
2
3
4
SCK
Mode 0
IO[3:0]
02h
23:20 19:16 15:12 11:8
3-byte Address
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Data In 1
Data In 2
Data In 3
Data In 4
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8.9 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h/38h)
The Quad Input Page Program instruction allows up to 256 bytes data to be programmed into memory in a
single operation with four pins (IO0, IO1, IO2 and IO3). The destination of the memory to be programmed must
be outside the protected memory area set by the Block Protection (BP3, BP2, BP1, BP0) bits. A Quad Input
Page Program instruction which attempts to program into a page that is write-protected will be ignored. Before
the execution of Quad Input Page Program instruction, the QE bit in the Status Register must be set to “1” and
the Write Enable Latch (WEL) must be enabled through a Write Enable (WREN) instruction.
The Quad Input Page Program instruction code, three address bytes and program data (1 to 256 bytes) are
input via the four pins (IO0, IO1, IO2 and IO3). Program operation will start immediately after the CE# is brought
high, otherwise the Quad Input Page Program instruction will not be executed. The internal control logic
automatically handles the programming voltages and timing. During a program operation, all instructions will be
ignored except the RDSR instruction. The progress or completion of the program operation can be determined
by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the program operation is
still in progress. If WIP bit is “0”, the program operation has completed.
If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the
previously latched data are discarded, and the last 256 bytes data are kept to be programmed into the page.
The starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap
around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all
other bytes on the same page will remain unchanged.
Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s.
A byte cannot be reprogrammed without first erasing the whole sector or block.
Figure 8.13 Quad Input Page Program Sequence
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
...
31
32
33
34
35
...
SCK
Mode 0
3-byte Address
Data In 1
Data In 2
4
0
4
0
...
5
1
5
1
...
IO2
6
2
6
2
...
IO3
7
3
7
3
...
IO0
IO1
Instruction = 32h/38h
High Impedance
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...
0
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8.10 ERASE OPERATION
The memory array of the device is organized into uniform 4 Kbyte sectors or 32/64 Kbyte uniform blocks (a
block consists of eight/sixteen adjacent sectors respectively).
Before a byte is reprogrammed, the sector or block that contains the byte must be erased (erasing sets bits to
“1”). In order to erase the device, there are three erase instructions available: Sector Erase (SER), Block Erase
(BER) and Chip Erase (CER). A sector erase operation allows any individual sector to be erased without
affecting the data in other sectors. A block erase operation erases any individual block. A chip erase operation
erases the whole memory array of a device. A sector erase, block erase, or chip erase operation can be
executed prior to any programming operation.
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8.11 SECTOR ERASE OPERATION (SER, D7h/20h)
A Sector Erase (SER) instruction erases a 4 Kbyte sector before the execution of a SER instruction, the Write
Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is automatically reset after
the completion of Sector Erase operation.
A SER instruction is entered, after CE# is pulled low to select the device and stays low during the entire
instruction sequence The SER instruction code, and three address bytes are input via SI. Erase operation will
start immediately after CE# is pulled high. The internal control logic automatically handles the erase voltage and
timing.
During an erase operation, all instruction will be ignored except the Read Status Register (RDSR) instruction.
The progress or completion of the erase operation can be determined by reading the WIP bit in the Status
Register using a RDSR instruction.
If the WIP bit is “1”, the erase operation is still in progress. If the WIP bit is “0”, the erase operation has been
completed.
Figure 8.14 Sector Erase Sequence
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
...
28
29
30
31
1
0
SCK
Mode 0
3-byte Address
SI
SO
Instruction = D7h/20h
23
22
21
...
4
5
6
7
7:4
3:0
3
2
High Impedance
Figure 8.15 Sector Erase QPI Sequence
CE#
Mode 3 0
1
2
3
SCK
Mode 0
IO[3:0]
3-byte Address
D7h/20h
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8.12 BLOCK ERASE OPERATION (BER32K:52h, BER64K:D8h)
A Block Erase (BER) instruction erases a 32/64Kbyte block. Before the execution of a BER instruction, the Write
Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically after
the completion of a block erase operation.
The BER instruction code and three address bytes are input via SI. Erase operation will start immediately after
the CE# is pulled high, otherwise the BER instruction will not be executed. The internal control logic
automatically handles the erase voltage and timing.
Figure 8.16 Block Erase (64K) Sequence
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
...
28
29
30
31
2
1
0
SCK
Mode 0
3-byte Address
SI
SO
Instruction = D8h
23
22
21
...
4
5
6
7
7:4
3:0
3
High Impedance
Figure 8.17 Block Erase (64K) QPI Sequence
CE#
Mode 3 0
1
2
3
SCK
Mode 0
IO[3:0]
3-byte Address
D8h
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Figure 8.18 Block Erase (32K) Sequence
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
...
28
29
30
31
2
1
0
SCK
Mode 0
3-byte Address
SI
SO
Instruction = 52h
23
22
21
...
4
5
6
7
7:4
3:0
3
High Impedance
Figure 8.19 Block Erase (32K) QPI Sequence
CE#
Mode 3 0
1
2
3
SCK
Mode 0
IO[3:0]
3-byte Address
52h
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8.13 CHIP ERASE OPERATION (CER, C7h/60h)
A Chip Erase (CER) instruction erases the entire memory array. Before the execution of CER instruction, the
Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is automatically reset
after completion of a chip erase operation.
The CER instruction code is input via the SI. Erase operation will start immediately after CE# is pulled high,
otherwise the CER instruction will not be executed. The internal control logic automatically handles the erase
voltage and timing.
Figure 8.20 Chip Erase Sequence
CE#
0
Mode 3
1
2
3
4
5
6
7
SCK
Mode 0
SI
Instruction = C7h/60h
SO
High Impedance
Figure 8.21 Chip Erase QPI Sequence
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
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8.14 WRITE ENABLE OPERATION (WREN, 06h)
The Write Enable (WREN) instruction is used to set the Write Enable Latch (WEL) bit. The WEL bit is reset to
the write-protected state after power-up. The WEL bit must be write enabled before any write operation,
including Sector Erase, Block Erase, Chip Erase, Page Program, Program Information Row, Write Status
Register, Write Function Register, Set non-volatile Read Register, Set non-volatile Extended Read Register,
and Write Autoboot Register operations except for Set volatile Read Register and Set volatile Extended Read
Register. The WEL bit will be reset to the write-protected state automatically upon completion of a write
operation. The WREN instruction is required before any above operation is executed.
Figure 8.22 Write Enable Sequence
CE#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Instruction = 06h
SI
High Impedance
SO
Figure 8.23 Write Enable QPI Sequence
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
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8.15 WRITE DISABLE OPERATION (WRDI, 04h)
The Write Disable (WRDI) instruction resets the WEL bit and disables all write instructions. The WRDI
instruction is not required after the execution of a write instruction, since the WEL bit is automatically reset.
Figure 8.24 Write Disable Sequence
CE#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Instruction = 04h
SI
High Impedance
SO
Figure 8.25 Write Disable QPI Sequence
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
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8.16 READ STATUS REGISTER OPERATION (RDSR, 05h)
The Read Status Register (RDSR) instruction provides access to the Status Register. During the execution of a
program, erase or write Status Register operation, all other instructions will be ignored except the RDSR
instruction, which can be used to check the progress or completion of an operation by reading the WIP bit of
Status Register.
Figure 8.26 Read Status Register Sequence
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
11
12
13
14
15
SCK
Mode 0
SI
Instruction = 05h
tV
SO
Data Out
7
6
5
4
3
2
1
0
Figure 8.27 Read Status Register QPI Sequence
CE#
Mode 3 0
1
2
3
SCK
Mode 0
tV
IO[3:0]
05h
7:4
3:0
Data Out
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8.17 WRITE STATUS REGISTER OPERATION (WRSR, 01h)
The Write Status Register (WRSR) instruction allows the user to enable or disable the block protection and
Status Register write protection features by writing “0”s or “1”s into the non-volatile BP3, BP2, BP1, BP0, and
SRWD bits. Also WRSR instruction allows the user to disable or enable quad operation by writing “0” or “1” into
the non-volatile QE bit.
Figure 8.28 Write Status Register Sequence
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
11
12
13
14
15
2
1
0
SCK
Mode 0
Data In
SI
SO
Instruction = 01h
7
6
5
4
3
High Impedence
Figure 8.29 Write Status Register QPI Sequence
CE#
Mode 3 0
1
2
3
7:4
3:0
SCK
Mode 0
IO[3:0]
01h
Data In
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8.18 READ FUNCTION REGISTER OPERATION (RDFR, 48h)
The Read Function Register (RDFR) instruction provides access to the Function Register. Refer to Table 6.6
Function Register Bit Definition for more detail.
Figure 8.30 Read Function Register Sequence
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
11
12
13
14
15
SCK
Mode 0
SI
Instruction = 48h
tV
SO
Data Out
7
6
5
4
3
2
1
0
Figure 8.31 Read Function Register QPI Sequence
CE#
Mode 3 0
1
2
3
SCK
Mode 0
tV
IO[3:0]
48h
7:4
3:0
Data Out
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8.19 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h)
The Write Function Register (WRFR) instruction allows the user to disable dedicated RESET# pin on 16-pin
SOIC and 24-ball TFBGA packages by setting RESET# Enable/Disable bit to “1” in the case that the default
value of the bit is “0”
Also Information Row Lock bits (IRL3~IRL0) can be set to “1” individually by WRFR instruction in order to lock
Information Row. Since RESER# Enable/Disable bit and IRL bits are OTP, once it is set to “1”, it cannot be set
back to “0” again.
Figure 8.32 Write Function Register Sequence
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
11
12
13
14
15
2
1
0
SCK
Mode 0
Data In
SI
SO
Instruction = 42h
7
6
5
4
3
High Impedence
Figure 8.33 Write Function Register QPI Sequence
CE#
Mode 3 0
1
2
3
7:4
3:0
SCK
Mode 0
IO[3:0]
42h
Data In
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8.20 ENTER QUAD PERIPHERAL INTERFACE (QPI) MODE OPERATION (QPIEN, 35h; QPIDI, F5h)
The Enter Quad Peripheral Interface (QPIEN) instruction, 35h, enables the Flash device for QPI mode operation.
Upon completion of the instruction, all instructions thereafter will be 4-bit multiplexed input/output until a power
cycle or an Exit Quad Peripheral Interface (QPIDI) instruction is sent to device.
The Exit Quad Peripheral Interface (QPIDI) instruction, F5h, resets the device to 1-bit SPI protocol operation. To
execute a QPIDI instruction, the host drives CE# low, sends the QPIDI command cycle, then drives CE# high.
The device just accepts QPI (2 clocks) command cycles.
Figure 8.34 Enter Quad Peripheral Interface (QPI) Mode Sequence
CE#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Instruction = 35h
SI
High Impedance
SO
Figure 8.35 Exit Quad Peripheral Interface (QPI) Mode Sequence
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
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8.21 PROGRAM/ERASE SUSPEND & RESUME
The device allows the interruption of Sector Erase, Block Erase, or Page Program operations to conduct other
operations. 75h/B0h command for suspend and 7Ah/30h for resume will be used. (SPI/QPI all acceptable)
Function Register bit2 (PSUS) and bit3 (ESUS) are used to check whether or not the device is in suspend mode.
Suspend to read ready timing: 100µs
Resume to another suspend timing: 400µs
PROGRAM/ERASE SUSPEND DURING SECTOR-ERASE OR BLOCK-ERASE (PERSUS 75h/B0h)
The Program/Erase Suspend allows the interruption of Sector Erase and Block Erase operations. After the
Program/Erase Suspend, WEL bit will be disabled, therefore only read related, resume and reset commands
can be accepted. Refer to Table 8.4 for more detail.
To execute the Program/Erase Suspend operation, the host drives CE# low, sends the Program/Erase Suspend
command cycle (75h/B0h), then drives CE# high. The Function Register indicates that the erase has been
suspended by changing the ESUS bit from “0” to “1”, but the device will not accept another command until it is
ready. To determine when the device will accept a new command, poll the WIP bit in the Status Register or wait
the specified time tSUS. When ESUS bit is issued, the Write Enable Latch (WEL) bit will be reset.
PROGRAM/ERASE SUSPEND DURING PAGE PROGRAMMING (PERSUS 75h/B0h)
The Program/Erase Suspend allows the interruption of an array program operation. After the Program/Erase
Suspend command, WEL bit will be disabled, therefore only read related, resume and reset command can be
accepted. Refer to Table 8.4 for more detail.
To execute the Program/Erase Suspend operation, the host drives CE# low, sends the Program/Erase Suspend
command cycle (75h/B0h), then drives CE# high. The Function Register indicates that the programming has
been suspended by changing the PSUS bit from “0” to “1”, but the device will not accept another command until
it is ready. To determine when the device will accept a new command, poll the WIP bit in the Status Register or
wait the specified time tSUS.
PROGRAM/ERASE RESUME (PERRSM 7Ah/30h)
The Program/Erase Resume restarts the Program or Erase command that was suspended, and changes the
suspend status bit in the Function Register (ESUS or PSUS bits) back to “0”. To execute the Program/Erase
Resume operation, the host drives CE# low, sends the Program/Erase Resume command cycle (7Ah/30h), then
drives CE# high. A cycle is two nibbles long, most significant nibble first. To determine if the internal, self-timed
Write operation completed, poll the WIP bit in the Status Register, or wait the specified time tSE, tBE or tPP for
Sector Erase, Block Erase, or Page Programming, respectively. The total write time before suspend and after
resume will not exceed the uninterrupted write times tSE, tBE or tPP.
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Table 8.4 Instructions accepted during Suspend
Instruction Allowed
Operation
Suspended
Name
Program or Erase
NORD
03h
Read Data Bytes from Memory at Normal Read Mode
Program or Erase
FRD
0Bh
Read Data Bytes from Memory at Fast Read Mode
Program or Erase
FRDIO
BBh
Fast Read Dual I/O
Program or Erase
FRDO
3Bh
Fast Read Dual Output
Program or Erase
FRQIO
EBh
Fast Read Quad I/O
Program or Erase
FRQO
6Bh
Fast Read Quad Output
Program or Erase
FRDTR
0Dh
Fast Read DTR Mode
Program or Erase
FRDDTR
BDh
Fast Read Dual I/O DTR
Program or Erase
FRQDTR
EDh
Fast Read Quad I/O DTR
Program or Erase
RDSR
05h
Read Status Register
Program or Erase
RDFR
48h
Read Function Register
Program or Erase
PERRSM
7Ah/30h
Resume program/erase
Program or Erase
RDID
ABh
Program or Erase
SRPV
C0/63h
Program or Erase
SERPV
83h
Set Extended Read Parameters (Volatile)
Program or Erase
RDRPNV
61h
Read Read Parameters (Non-Volatile)
Program or Erase
RDERPNV
81h
Read Extended Read Parameters (Non-Volatile)
Program or Erase
RDJDID
9Fh
Read Manufacturer and Product ID by JEDEC ID Command
Program or Erase
RDMDID
90h
Read Manufacturer and Device ID
Program or Erase
RDJDIDQ
AFh
Read JEDEC ID QPI mode
Program or Erase
RDUID
4Bh
Read Unique ID Number
Program or Erase
RDSFDP
5Ah
SFDP Read
Program or Erase
NOP
00h
No Operation
Program or Erase
RSTEN
66h
Software reset enable
Program or Erase
RST
99h
Reset (Only along with 66h)
Program or Erase
IRRD
68h
Read Information Row
Program or Erase
RDABR
14h
Read AutoBoot Register
Hex Code
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Set Read Parameters (Volatile)
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8.22 ENTER DEEP POWER DOWN (DP, B9h)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (enter
into Power-down mode). During this mode, standby current is reduced from Isb1 to Isb2. While in the Power-down
mode, the device is not active and all Write/Program/Erase instructions are ignored. The instruction is initiated
by driving the CE# pin low and shifting the instruction code into the device. The CE# pin must be driven high
after the instruction has been latched, or Power-down mode will not engage. Once CE# pin driven high, the
Power-down mode will be entered within the time duration of tDP. While in the Power-down mode only the
Release from Power-down/RDID instruction, which restores the device to normal operation, will be recognized.
All other instructions are ignored, including the Read Status Register instruction which is always available during
normal operation. Ignoring all but one instruction makes the Power Down state a useful condition for securing
maximum write protection. It is available in both SPI and QPI mode.
Figure 8.36 Enter Deep Power Down Mode Operation
tDP
CE #
Mode 3 0
1
2
3
4
5
6
7
SCK
Mode 0
SI
SO
Instruction = B9h
High Impedance
Figure 8.37 Enter Deep Power Down Mode QPI Operation
tDP
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
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8.23 RELEASE DEEP POWER DOWN (RDPD, ABh)
The Release Deep Power-down/Read Device ID instruction is a multi-purpose command. To release the device
from the Power-down mode, the instruction is issued by driving the CE# pin low, shifting the instruction code
“ABh” and driving CE# high.
Releasing the device from Power-down mode will take the time duration of tRES1 before normal operation is
restored and other instructions are accepted. The CE# pin must remain high during the t RES1 time duration. If
the Release Deep Power-down/RDID instruction is issued while an Erase, Program or Write cycle is in progress
(WIP=1) the instruction is ignored and will not have any effects on the current cycle.
Figure 8.38 Release Deep Power Down Mode Operation
tRES1
CE #
Mode 3 0
1
2
3
4
5
6
7
SCK
Mode 0
SI
SO
Instruction = ABh
High Impedance
Figure 8.39 Release Deep Power Down Mode QPI Operation
tRES1
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
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8.24 SET READ PARAMETERS OPERATION (SRPNV: 65h, SRPV: C0h/63h)
Set Read Parameter Bits
This device supports configurable burst length and dummy cycles in both SPI and QPI mode by setting three
bits (P2, P1, P0) and four bits (P6, P5, P4, P3) within the Read Register, respectively. To set those bits the
SRPNV and SRPV operation instruction are used. Details regarding burst length and dummy cycles can be
found in Table 6.9, Table 6.10, and Table 6.11. HOLD#/RESET# pin selection (P7) bit in the Read Register can
be set with the SRPNV and SRPV operation as well, in order to select RESET# pin instead of HOLD# pin. For
16-pin SOIC or 24-ball TFBGA packages, dedicated RESET# pin (or ball) can be added as a separate pin (or
ball) and it is independent of the P7 bit setting in Read Register.
SRPNV is used to set the non-volatile Read register, while SRPV is used to set the volatile Read register.
Note: When SRPNV is executed, the volatile Read Register is set as well as the non-volatile Read Register.
Figure 8.40 Set Read Parameters Operation
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2
1
0
SCK
Mode 0
Data In
SI
SO
Instruction = 65h or C0h/63h
7
6
5
4
3
High Impedence
Figure 8.41 Set Read Parameters QPI Operation
CE#
Mode 3 0
1
2
3
7:4
3:0
SCK
Mode 0
IO[3:0]
65h or
C0h/63h
Data In
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Read with “8/16/32/64-Byte Wrap Around”
The device is capable of burst read with wrap around in both SPI and QPI mode. The size of burst length is
configurable by using P0, P1, and P2 bits in Read Register. P2 bit (Wrap enable) enables the burst mode
feature. P0 and P1 define the size of burst. Burst lengths of 8, 16, 32, and 64 bytes are supported. By default,
address increases by one up through the entire array. By setting the burst length, the data being accessed can
be limited to the length of burst boundary within a 256 byte page. The first output will be the data at the initial
address which is specified in the instruction. Following data will come out from the next address within the burst
boundary. Once the address reaches the end of boundary, it will automatically move to the first address of the
boundary. CE# high will terminate the command.
For example, if burst length of 8 and initial address being applied is 0h, following byte output will be from
address 00h and continue to 01h,..,07h, 00h, 01h… until CE# terminates the operation. If burst length of 8 and
initial address being applied is FEh(254d), following byte output will be from address FEh and continue to FFh,
F8h, F9h, FAh, FBh, FCh, FDh, and repeat from FEh until CE# terminates the operation.
The commands, “SRPV (65h) or SRPNV (C0h or 63h)”, are used to configure the burst length. If the following
data input is one of “00h”,”01h”,”02h”, and ”03h”, the device will be in default operation mode. It will be
continuous burst read of the whole array. If the following data input is one of “04h”,”05h”,”06h”, and ”07h”, the
device will set the burst length as 8,16,32 and 64, respectively.
To exit the burst mode, another “C0h or 63h” command is necessary to set P2 to 0. Otherwise, the burst mode
will be retained until either power down or reset operation. To change burst length, another “C0h or 63h”
command should be executed to set P0 and P1 (Detailed information in Table 6.9 Burst Length Data). All read
commands will operate in burst mode once the Read Register is set to enable burst mode.
Refer to Figure 8.40 and Figure 8.41 for instruction sequence.
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8.25 SET EXTENDED READ PARAMETERS OPERATION (SERPNV: 85h, SERPV: 83h)
Set Read Operational Driver Strength
This device supports configurable Operational Driver Strength in both SPI and QPI modes by setting three bits
(ODS0, ODS1, ODS2) within the Extended Read Register. To set the ODS bits the SERPNV and SERPV
operation instructions are required. The device’s driver strength can be reduced as low as 12.50% of full drive
strength. Details regarding the driver strength can be found in Table 6.14.
SERPNV is used to set the non-volatile Extended Read register, while SERPV is used to set the volatile
Extended Read register.
Notes:
1. The default driver strength is set to 50%.
2. When SERPNV is executed, the volatile Read Extended Register is set as well as the non-volatile Read Extended
Register.
Figure 8.42 Set Extended Read Parameters Sequence
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2
1
0
SCK
Mode 0
Data In
SI
SO
Instruction = 85h/83h
7
6
5
4
3
High Impedence
Figure 8.43 Set Extended Read Parameters QPI Sequence
CE#
Mode 3 0
1
2
3
7:4
3:0
SCK
Mode 0
IO[3:0]
85h/83h
Data In
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8.26 READ READ PARAMETERS OPERATION (RDRPNV, 61h)
Prior to, or after setting Read Register, the data of the Read Register can be confirmed by the RDRPNV
command. The instruction is only applicable for non-volatile Read Register, not for volatile Read Register.
Figure 8.44 Read Read Parameters Sequence
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
11
12
13
14
15
SCK
Mode 0
SI
Instruction = 61h
tV
SO
Data Out
7
6
5
4
3
2
1
0
Figure 8.45 Read Read Parameters QPI Sequence
CE#
Mode 3 0
1
2
3
SCK
Mode 0
tV
IO[3:0]
61h
7:4
3:0
Data Out
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8.27 READ EXTENDED READ PARAMETERS OPERATION (RDRPNV, 81h)
Prior to, or after setting Extended Read Register, the data of the Extended Read Register can be confirmed by
the RDRPNV command. The instruction is only applicable for non-volatile Extended Read Register, not for
volatile Extended Read Register.
Figure 8.46 Read Extended Read Parameters Sequence
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
11
12
13
14
15
SCK
Mode 0
SI
Instruction = 81h
tV
Data Out
SO
7
6
5
4
3
2
1
0
Figure 8.47 Read Extended Read Parameters QPI Sequence
CE#
Mode 3 0
1
2
3
SCK
Mode 0
tV
IO[3:0]
81h
7:4
3:0
Data Out
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8.28 READ PRODUCT IDENTIFICATION (RDID, ABh)
The Release from Power-down/Read Device ID instruction is a multi-purpose instruction. It can support both SPI
and QPI modes. The Read Product Identification (RDID) instruction is for reading out the old style of 8-bit
Electronic Signature, whose values are shown as table of Product Identification.
The RDID instruction code is followed by three dummy bytes, each bit being latched-in on SI during the rising
SCK edge. Then the Device ID is shifted out on SO with the MSB first, each bit been shifted out during the
falling edge of SCK. The RDID instruction is ended by driving CE# high. The Device ID (ID7-ID0) outputs
repeatedly if additional clock cycles are continuously sent to SCK while CE# is at low.
Table 8.5 Product Identification
Manufacturer ID
(MF7-MF0)
ISSI Serial Flash
9Dh
Instruction
ABh
90h
Device Density
Device ID (ID7-ID0)
9Fh
Memory Type + Capacity
(ID15-ID0)
16Mb
14h
7015h
8Mb
13h
7014h
4Mb
12h
7013h
2Mb
11h
7012h
Figure 8.48 Read Product Identification Sequence
CE #
Mode 3 0
1
...
7
8
9
...
31
32
33
...
39
SCK
Mode 0
SI
Instruction = ABh
3 Dummy Bytes
tV
SO
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Data Out
Device ID
(ID7-ID0)
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Figure 8.49 Read Product Identification QPI Sequence
CE#
Mode 3 0
1
2
3
4
5
6
7
8
9
SCK
Mode 0
tV
IO[3:0]
ABh
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Device ID
(ID7-ID0)
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8.29 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9Fh; RDJDIDQ, AFh)
The JEDEC ID READ instruction allows the user to read the manufacturer and product ID of devices. Refer to
Table 8.5 Product Identification for Manufacturer ID and Device ID. After the JEDEC ID READ command (9Fh in
SPI mode, AFh in QPI mode) is input, the Manufacturer ID is shifted out MSB first followed by the 2-byte
electronic ID (ID15-ID0) that indicates Memory Type and Capacity, one bit at a time. Each bit is shifted out
during the falling edge of SCK. If CE# stays low after the last bit of the 2-byte electronic ID, the Manufacturer ID
and 2-byte electronic ID will loop until CE# is pulled high.
Figure 8.50 Read Product Identification by JEDEC ID Read Sequence in SPI mode
CE #
Mode 3 0
1
...
7
8
9
...
15
16
17
...
23
24
25
...
31
SCK
Mode 0
SI
Instruction = 9Fh
tV
Manufacturer ID
(MF7-MF0)
SO
Capacity
(ID7-ID0)
Memory Type
(ID15-ID8)
Figure 8.51 RDJDIDQ (Read JEDEC ID in QPI Mode) Sequence
CE#
Mode 3 0
1
2
3
4
5
6
7
SCK
Mode 0
IO[3:0]
tV
AFh
7:4
3:0
MF7-MF0
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3:0
ID15-ID8
7:4
3:0
ID7-ID0
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8.30 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90h)
The Read Device Manufacturer and Device ID (RDMDID) instruction allows the user to read the Manufacturer
and product ID of devices. Refer to Table 8.5 Product Identification for Manufacturer ID and Device ID. The
RDMDID instruction code is followed by two dummy bytes and one byte address (A7~A0), each bit being
latched-in on SI during the rising edge of SCK. If one byte address is initially set as A0 = 0, then the
Manufacturer ID is shifted out on SO with the MSB first followed by the Device ID (ID7- ID0). Each bit is shifted
out during the falling edge of SCK. If one byte address is initially set as A0 = 1, then Device ID will be read first
followed by the Manufacturer ID. The Manufacturer and Device ID can be read continuously alternating between
the two until CE# is driven high.
Figure 8.52 Read Product Identification by RDMDID Sequence
CE #
Mode 3 0
1
...
7
8
9
...
31
32
33
...
39
40
41
...
47
SCK
Mode 0
SI
Instruction = 90h
3-byte Address
tV
Device ID
(ID7-ID0)
Manufacturer ID
(MF7-MF0)
SO
Notes:
1. ADDRESS A0 = 0, will output the 1-byte Manufacturer ID (MF7-MF0) 1-byte Device ID (ID7-ID0)
ADDRESS A0 = 1, will output the 1-byte Device ID (ID7-ID0) 1-byte Manufacturer ID (MF7-MF0)
2. The Manufacturer and Device ID can be read continuously and will alternate from one to the other until CE# pin
is pulled high.
Figure 8.53 Read Product Identification by RDMDID QPI Sequence
CE#
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
SCK
Mode 0
tV
IO[3:0]
90h
23:20 19:16 15:12 11:8
Instruction
3-byte Address
7:4
3:0
7:4
3:0
7:4
3:0
Manufacturer Device ID
ID (MF7-MF0) (ID7-ID0)
Notes:
1. ADDRESS A0 = 0, will output the 1-byte Manufacturer ID (MF7-MF0) 1-byte Device ID (ID7-ID0)
ADDRESS A0 = 1, will output the 1-byte Device ID (ID7-ID0) 1-byte Manufacturer ID (MF7-MF0)
2. The Manufacturer and Device ID can be read continuously and will alternate from one to the other until CE# pin
is pulled high.
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8.31 READ UNIQUE ID NUMBER (RDUID, 4Bh)
The Read Unique ID Number (RDUID) instruction accesses a factory-set read-only 16-byte number that is
unique to the device. The ID number can be used in conjunction with user software methods to help prevent
copying or cloning of a system. The RDUID instruction is instated by driving the CE# pin low and shifting the
instruction code (4Bh) followed by 3 address bytes and dummy cycles (configurable, default is 8 clocks). After
which, the 16-byte ID is shifted out on the falling edge of SCK as shown below. As a result, the sequence of
RDUID instruction is same as FAST READ. RDUID QPI sequence is also same as FAST READ QPI except for
the instruction code. Refer to the FAST READ QPI operation.
Note: 16 bytes of data will repeat as long as CE# is low and SCK is toggling.
Figure 8.54 RDUID Sequence
CE #
Mode 3 0
1
...
7
8
9
...
31
32
33
...
39
40
41
...
47
...
SCK
Mode 0
SI
Instruction = 4Bh
3 Byte Address
Dummy Cycles
tV
SO
Data Out
Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.
A[23:16]
A[15:9]
A[8:4]
A[3:0]
XXh
XXh
00h
0h Byte address
XXh
XXh
00h
1h Byte address
XXh
XXh
00h
2h Byte address
XXh
XXh
00h
…
Table 8.6 Unique ID Addressing
XXh
XXh
00h
Fh Byte address
Note: XX means “don’t care”.
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8.32 READ SFDP OPERATION (RDSFDP, 5Ah)
The Serial Flash Discoverable Parameters (SFDP) standard provides a consistent method of describing the
functions and features of serial Flash devices in a standard set of internal parameter tables. These parameters
can be interrogated by host system software to enable adjustments needed to accommodate divergent features
from multiple vendors. For more details please refer to the JEDEC Standard JESD216A (Serial Flash
Discoverable Parameters).
The sequence of issuing RDSFDP instruction is same as FAST_READ: CE# goes low Send RDSFDP
instruction (5Ah) Send 3 address bytes on SI pin Send dummy cycles (configurable, default is 8 clocks) on
SI pin Read SFDP code on SO End RDSFDP operation by driving CE# high at any time during data out.
Refer to ISSI’s Application note for SFDP table. The data at the addresses that are not specified in SFDP table
are undefined.
The sequence of RDSFDP instruction is same as FAST READ except for the instruction code. RDSFDP QPI
sequence is also same as FAST READ QPI except for the instruction code. Refer to the FAST READ QPI
operation.
Figure 8.55 RDSFDP (Read SFDP) Sequence
CE #
Mode 3 0
1
...
7
8
9
...
31
32
33
...
39
40
41
...
47
...
SCK
Mode 0
SI
Instruction = 5Ah
3 Byte Address
Dummy Cycles
tV
SO
Data Out
Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.
8.33 NO OPERATION (NOP, 00h)
The No Operation command solely cancels a Reset Enable command and has no impact on any other
commands. It is available in both SPI and QPI modes. To execute a NOP, the host drives CE# low, sends the
NOP command cycle (00H), then drives CE# high.
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8.34 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h)) AND HARDWARE RESET
The Software Reset operation is used as a system reset that puts the device in normal operating mode. During
the Reset operation, the value of volatile registers will default back to the value in the corresponding non-volatile
register. This operation consists of two commands: Reset-Enable (RSTEN) and Reset (RST). The operation
requires the Reset-Enable command followed by the Reset command. Any command other than the Reset
command after the Reset-Enable command will disable the Reset-Enable.
Execute the CE# pin low sends the Reset-Enable command (66h), and drives CE# high. Next, the host drives
CE# low again, sends the Reset command (99h), and pulls CE# high.
Only if the RESET# pin (or ball) is enabled, Hardware Reset function is available. For all other packages except
the package with dedicated RESET# option, the RESET# pin will be solely applicable in SPI mode and when
the QE bit is disabled. For the package with dedicated RESET# pin (or ball) which is enabled by the RESET#
Enable/Disable bit setting (“0” indicates Enable) in Function Register, the RESET# pin is always applicable
regardless of the QE bit value in Status Register and HOLD#/RESET# selection bit (P7) in Read Register.
The dedicated RESET# pin (or ball) has an internal pull-up resistor and may be left floating if not used. The
RESET# pin has the highest priority among all the input signals and will reset the device to its initial power-on
state regardless of the state of all other pins (CE#, IOs, SCK, and WP#).
In order to activate Hardware Reset, the RESET# pin must be driven low for a minimum period of t RESET (1µs).
Drive RESET# low for a minimum period of tRESET will interrupt any on-going internal and external operations,
1
release the device from deep power down mode , disable all input signals, force the output pin enter a state of
high impedance, and reset all the read parameters. If the RESET# pulse is driven for a period shorter than 1µs,
it may still reset the device, however the 1µs minimum period is recommended to ensure the reliable operation.
The required wait time after activating a HW Reset before the device will accept another instruction (tHWRST) is
the same as the maximum value of tSUS (100µs).
The Software/Hardware Reset during an active Program or Erase operation aborts the operation, which can
result in corrupting or losing the data of the targeted address range. Depending on the prior operation, the reset
timing may vary. Recovery from a Write operation will require more latency than recovery from other operations.
Note 1: The Status and Function Registers remain unaffected.
Figure 8.56 Software Reset Enable and Software Reset Sequence (RSTEN, 66h + RST, 99h)
CE#
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Mode 0
SI
Instruction = 66h
Instruction = 99h
High Impedance
SO
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Figure 8.57 Software Reset Enable and Software Reset QPI Sequence (RSTEN, 66h + RST, 99h)
CE#
Mode 3 0
1
0
1
SCK
Mode 0
IO[3:0]
99h
66h
8.35 SECURITY INFORMATION ROW
The security Information Row is comprised of an additional 4 x 256 bytes of programmable information. The
security bits can be reprogrammed by the user. Any program security instruction issued while an erase, program
or write cycle is in progress is rejected without having any effect on the cycle that is in progress.
Table 8.7 Information Row Valid Address Range
Address Assignment
IRL0 (Information Row Lock0)
IRL1
IRL2
IRL3
A[23:16]
00h
00h
00h
00h
A[15:8]
00h
10h
20h
30h
A[7:0]
Byte address
Byte address
Byte address
Byte address
Bit 7~4 of the Function Register is used to permanently lock the programmable memory array.
When Function Register bit IRLx = “0”, the 256 bytes of the programmable memory array can be programmed.
When Function Register bit IRLx = “1”, the 256 bytes of the programmable memory array function as read only.
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8.36 INFORMATION ROW ERASE OPERATION (IRER, 64h)
Information Row Erase (IRER) instruction erases the data in the Information Row x (x: 0~3) array. Prior to the
operation, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is
automatically reset after the completion of the operation.
The sequence of IRER operation: Pull CE# low to select the device Send IRER instruction code Send
three address bytes Pull CE# high. CE# should remain low during the entire instruction sequence. Once CE#
is pulled high, Erase operation will begin immediately. The internal control logic automatically handles the erase
voltage and timing.
Figure 8.58 IRER (Information Row Erase) Sequence
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
...
28
29
30
31
1
0
SCK
Mode 0
3-byte Address
SI
SO
Instruction = 64h
23
22
21
...
3
2
High Impedance
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8.37 INFORMATION ROW PROGRAM OPERATION (IRP, 62h)
The Information Row Program (IRP) instruction allows up to 256 bytes data to be programmed into the memory
in a single operation. Before the execution of IRP instruction, the Write Enable Latch (WEL) must be enabled
through a Write Enable (WREN) instruction.
The IRP instruction code, three address bytes and program data (1 to 256 bytes) should be sequentially input.
Three address bytes has to be input as specified in the Table 8.7 Information Row Valid Address Range.
Program operation will start once the CE# goes high, otherwise the IRP instruction will not be executed. The
internal control logic automatically handles the programming voltages and timing. During a program operation,
all instructions will be ignored except the RDSR instruction. The progress or completion of the program
operation can be determined by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is
“1”, the program operation is still in progress. If WIP bit is “0”, the program operation has completed.
If more than 256 bytes data are sent to a device, the address counter rolls over within the same page. The
previously latched data are discarded and the last 256 bytes data are kept to be programmed into the page. The
starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap
around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all
other bytes on the same page will remain unchanged.
Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s.
A byte cannot be reprogrammed without first erasing the corresponding Information Row array which is one
of IR0~3.
Figure 8.59 IRP (Information Row Program) Sequence
1
...
7
8
9
...
31
32
33
...
39
...
...
2079
Mode 3 0
2072
CE #
SCK
Mode 0
SI
SO
3-byte Address
Instruction = 62h
23
22
...
Data In 1
0
7
6
...
Data In 256
0
...
7
...
0
High Impedance
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8.38 INFORMATION ROW READ OPERATION (IRRD, 68h)
The IRRD instruction is used to read memory data at up to a 133MHz clock.
The IRRD instruction code is followed by three address bytes (A23 - A0) and dummy cycles (configurable,
default is 8 clocks), transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the
first data byte addressed is shifted out on the SO line, with each bit shifted out at a maximum frequency f CT,
during the falling edge of SCK.
The address is automatically incremented by one after each byte of data is shifted out. Once the address
reaches the last address of each 256 byte Information Row, the next address will not be valid and the data of
the address will be garbage data. It is recommended to repeat four times IRRD operation that reads 256 byte
with a valid starting address of each Information Row in order to read all data in the 4 x 256 byte Information
Row array. The IRRD instruction is terminated by driving CE# high (VIH).
If an IRRD instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not have any effects on the current cycle.
The sequence of IRRD instruction is same as FAST READ except for the instruction code. IRRD QPI sequence
is also same as FAST READ QPI except for the instruction code. Refer to the FAST READ QPI operation.
Figure 8.60 IRRD (Information Row Read) Sequence
CE #
Mode 3
0
1
...
7
8
9
...
31
32
33
...
39
40
41
...
47
...
SCK
Mode 0
SI
Instruction = 68h
3 Byte Address
Dummy Cycles
tV
SO
Data Out
Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.
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8.39 FAST READ DTR MODE OPERATION (FRDTR, 0Dh)
The FRDTR instruction is for doubling the data in and out. Signals are triggered on both rising and falling edge
of clock. The address is latched on both rising and falling edge of SCK, and data of each bit shifts out on both
rising and falling edge of SCK at a maximum frequency fC2. The 2-bit address can be latched-in at one clock,
and 2-bit data can be read out at one clock, which means one bit at the rising edge of clock, the other bit at the
falling edge of clock.
The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte of data is shifted out, so the whole memory can be read out in a single FRDTR instruction. The
address counter rolls over to 0 when the highest address is reached.
The sequence of issuing FRDTR instruction is: CE# goes low Sending FRDTR instruction code (1bit per
clock) 3-byte address on SI (2-bit per clock) 8 dummy clocks (configurable, default is 8 clocks) on SI
Data out on SO (2-bit per clock) End FRDTR operation via driving CE# high at any time during data out.
While a Program/Erase/Write Status Register cycle is in progress, FRDTR instruction will be rejected without
any effect on the current cycle.
Figure 8.61 FRDTR Sequence
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
...
19
20
21
SCK
Mode 0
3-byte Address
SI
Instruction = 0Dh
23 22 21 20 19 18 17
...
0
High Impedance
SO
CE #
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
...
SCK
SI
8 Dummy Cycles
tV
Data Out 1
SO
Data Out 2
Data Out ...
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 ...
Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.
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FAST READ DTR QPI MODE OPERATION (FRDTR QPI, 0Dh)
The FRDTR QPI instruction utilizes all four IO lines to input the instruction code so that only two clocks are
required, while the FRDTR instruction requires that the byte-long instruction code is shifted into the device only
via IO0 line in eight clocks. In addition, subsequent address and data out are shifted in/out via all four IO lines
unlike the FRDTR instruction. Eventually this operation is same as the FRQDTR QPI, but the only different thing
is that AX mode is not available in the FRDTR QPI operation.
The sequence of issuing FRDTR QPI instruction is: CE# goes low Sending FRDTR QPI instruction (4-bit per
clock) 24-bit address interleave on IO3, IO2, IO1 & IO0 (8-bit per clock) 6 dummy clocks (configurable,
default is 6 clocks) Data out interleave on IO3, IO2, IO1 & IO0 (8-bit per clock) End FRDTR QPI operation
by driving CE# high at any time during data out.
If the FRDTR QPI instruction is issued while a Program/Erase/Write Status Register cycle is in progress
(WIP=1), the instruction will be rejected without any effect on the current cycle.
Figure 8.62 FRDTR QPI Sequence
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
...
SCK
Mode 0
IO0
IO1
IO2
IO3
Instruction
= 0Dh
6 Dummy Cycles
3-byte Address
tV
Data Data
Out Out
4
0
20 16 12 8 4 0
4 0 4 0 ...
5
1
21 17 13 9 5 1
5 1 5 1 ...
6
2
22 18 14 10 6 2
6 2 6 2 ...
7
3
23 19 15 11 7 3
7 3 7 3 ...
Notes:
1. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
2. Sufficient dummy cycles are required to avoid I/O contention.
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8.40 FAST READ DUAL IO DTR MODE OPERATION (FRDDTR, BDh)
The FRDDTR instruction enables Double Transfer Rate throughput on dual I/O of the device in read mode. The
address (interleave on dual I/O pins) is latched on both rising and falling edge of SCK, and the data (interleave
on dual I/O pins) shift out on both rising and falling edge of SCK at a maximum frequency f T2. The 4-bit address
can be latched-in at one clock, and 4-bit data can be read out at one clock, which means two bits at the rising
edge of clock, the other two bits at the falling edge of clock.
The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte of data is shifted out, so the whole memory can be read out with a single FRDDTR instruction.
The address counter rolls over to 0 when the highest address is reached. Once writing FRDDTR instruction, the
following address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing FRDDTR instruction is: CE# goes low Sending FRDDTR instruction (1-bit per clock)
24-bit address interleave on IO1 & IO0 (4-bit per clock) 4 dummy clocks (configurable, default is 4 clocks)
on IO1 & IO0 Data out interleave on IO1 & IO0 (4-bit per clock) End FRDDTR operation via pulling CE#
high at any time during data out (Please refer to Figure 8.63 for 2 x I/O Double Transfer Rate Read Mode
Timing Waveform).
If AXh (where X is don’t care) is input for the mode bits during dummy cycles, the device will enter AX read
operation mode which enables subsequent FRDDTR execution skips command code. It saves cycles as
described in Figure 8.64. When the code is different from AXh, the device exits the AX read operation. After
finishing the read operation, device becomes ready to receive a new command.
If the FRDDTR instruction is issued while a Program/Erase/Write Status Register cycle is in progress (WIP=1),
the instruction will be rejected without any effect on the current cycle.
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Figure 8.63 FRDDTR Sequence (with command decode cycles)
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
...
13
14
SCK
Mode 0
3-byte Address
SI
Instruction = BDh
22 20 18 16 14 12 10
4 Dummy Cycles
...
0 6 4
Mode Bits
High Impedance
SO
23 21 19 17 15 13 11
...
1 7 5
CE #
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
...
SCK
tV
SI
2 0
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 ...
Mode Bits
SO
3 1
7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 ...
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bit cycles
are same, then X should be Hi-Z.
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Figure 8.64 FRDDTR AX Read Sequence (without command decode cycles)
CE #
Mode 3 0
1
2
...
6
7
8
9
10
11
12
13
14
15
16
...
SCK
Mode 0
4 Dummy Cycles
3-byte Address
SI
22 20 18 16 14 12 10
...
0 6 4 2 0
tV
Data Out
Data Out
Data Out
6 4 2 0 6 4 2 0 6 4 2 0 ...
Mode Bits
SO
23 21 19 17 15 13 11
...
1 7 5 3 1
7 5 3 1 7 5 3 1 7 5 3 1 ...
Notes:
1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When
the mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bit cycles
are same, then X should be Hi-Z.
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8.41 FAST READ QUAD IO DTR MODE OPERATION (FRQDTR, EDh)
The FRQDTR instruction enables Double Transfer Rate throughput on quad I/O of the device in read mode. The
address (interleave on 4 I/O pins) is latched on both rising and falling edge of SCK, and data (interleave on 4 I/O
pins) shift out on both rising and falling edge of SCK at a maximum frequency fQ2. The 8-bit address can be
latched-in at one clock, and 8-bit data can be read out at one clock, which means four bits at the rising edge of
clock, the other four bits at the falling edge of clock.
The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte data is shifted out, so the whole memory can be read out with a single FRQDTR instruction. The
address counter rolls over to 0 when the highest address is reached. Once writing FRQDTR instruction, the
following address/dummy/data out will perform as 8-bit instead of previous 1-bit.
The sequence of issuing FRQDTR instruction is: CE# goes low Sending FRQDTR instruction (1-bit per clock)
24-bit address interleave on IO3, IO2, IO1 & IO0 (8-bit per clock) 6 dummy clocks (configurable, default is
6 clocks) Data out interleave on IO3, IO2, IO1 & IO0 (8-bit per clock) End FRQDTR operation by driving
CE# high at any time during data out.
If AXh (where X is don’t care) is input for the mode bits during dummy cycles, the device will enter AX read
operation mode which enables subsequent FRQDTR execution skips command code. It saves cycles as
described in Figure 8.66. When the code is different from AXh, the device exits the AX read operation. After
finishing the read operation, device becomes ready to receive a new command.
If the FRQDTR instruction is issued while a Program/Erase/Write Status Register cycle is in progress (WIP=1),
the instruction will be rejected without any effect on the current cycle.
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Figure 8.65 FRQDTR Sequence (with command decode cycles)
CE #
Mode 3 0
1
2
3
4
5
7
6
8
9
10
11
12
SCK
Mode 0
3-byte Address
IO0
Instruction = EDh
6 Dummy Cycles
20 16 12 8 4 0 4 0
High Impedance
IO1
21 17 13 9 5 1 5 1
IO2
22 18 14 10 6 2 6 2
IO3
23 19 15 11 7 3 7 3
Mode Bits
CE #
13
14
15
16
17
18
19
20
21
22
23
24
25
26
...
SCK
Data Data Data Data Data Data Data Data Data Data
tV Out Out Out Out Out Out Out Out Out Out
IO0
4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 ...
IO1
5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 ...
IO2
6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 ...
IO3
7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 ...
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bit cycles
are same, then X should be Hi-Z.
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Figure 8.66 FRQDTR Sequence (without command decode cycles)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
...
SCK
Mode 0
6 Dummy Cycles
3-byte Address
IO0
IO1
IO2
IO3
Data Data Data Data
tV Out Out Out Out
20 16 12 8 4 0 4 0
4 0 4 0 4 0 4 0 ...
21 17 13 9 5 1 5 1
5 1 5 1 5 1 5 1 ...
22 18 14 10 6 2 6 2
6 2 6 2 6 2 6 2 ...
23 19 15 11 7 3 7 3
7 3 7 3 7 3 7 3 ...
Mode Bits
Notes:
1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When
the mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bit cycles
are same, then X should be Hi-Z.
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FAST READ QUAD IO DTR QPI MODE OPERATION (FRQDTR QPI, EDh)
The FRQDTR QPI instruction utilizes all four IO lines to input the instruction code so that only two clocks are
required, while the FRQDTR instruction requires that the byte-long instruction code is shifted into the device
only via IO0 line in eight clocks. As a result, 6 command cycles will be reduced by the FRQDTR QPI instruction.
In addition, subsequent address and data out are shifted in/out via all four IO lines like the FRQDTR instruction.
In fact, except for the command cycle, the FRQDTR QPI operation is exactly same as the FRQDTR.
The sequence of issuing FRQDTR QPI instruction is: CE# goes low Sending FRQDTR QPI instruction (4-bit
per clock) 24-bit address interleave on IO3, IO2, IO1 & IO0 (8-bit per clock) 6 dummy clocks (configurable,
default is 6 clocks) Data out interleave on IO3, IO2, IO1 & IO0 (8-bit per clock) End FRQDTR QPI
operation by driving CE# high at any time during data out.
If AXh (where X is don’t care) is input for the mode bits during dummy cycles, the device will enter AX read
operation mode which enables subsequent FRQDTR QPI execution skips command code. It saves cycles as
described in Figure 8.66. When the code is different from AXh, the device exits the AX read operation. After
finishing the read operation, device becomes ready to receive a new command.
If the FRQDTR QPI instruction is issued while a Program/Erase/Write Status Register cycle is in progress
(WIP=1), the instruction will be rejected without any effect on the current cycle.
Figure 8.67 FRQDTR QPI Sequence (with command decode cycles)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
...
SCK
Mode 0
IO0
IO1
IO2
IO3
Instruction
= EDh
6 Dummy Cycles
3-byte Address
tV
Data Data
Out Out
4
0
20 16 12 8 4 0 4 0
4 0 4 0 ...
5
1
21 17 13 9 5 1 5 1
5 1 5 1 ...
6
2
22 18 14 10 6 2 6 2
6 2 6 2 ...
7
3
23 19 15 11 7 3 7 3
7 3 7 3 ...
Mode Bits
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bit cycles
are same, then X should be Hi-Z.
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8.42 SECTOR LOCK/UNLOCK FUNCTIONS
SECTOR UNLOCK OPERATION (SECUNLOCK, 26h)
The Sector Unlock command allows the user to select a specific sector to allow program and erase operations.
This instruction is effective when the blocks are designated as write-protected through the BP0, BP1, BP2, and
BP3 bits in the Status Register. Only one sector can be enabled at any time. To enable a different sector, a
previously enabled sector must be disabled by executing a Sector Lock command. The instruction code is
followed by a 24-bit address specifying the target sector, but A0 through A11 are not decoded. The remaining
sectors within the same block remain as read-only.
Figure 8.68 Sector Unlock Sequence
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
...
28
29
30
31
1
0
SCK
Mode 0
3-byte Address
SI
SO
Instruction = 26h
...
23
22
21
4
5
6
7
7:4
3:0
3
2
High Impedance
Figure 8.69 Sector Unlock QPI Sequence
CE#
Mode 3 0
1
2
3
SCK
Mode 0
Instruction
IO[3:0]
26h
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23:20 19:16 15:12 11:8
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SECTOR LOCK OPERATION (SECLOCK, 24h)
The Sector Lock command relocks a sector that was previously unlocked by the Sector Unlock command. The
instruction code does not require an address to be specified, as only one sector can be enabled at a time. The
remaining sectors within the same block remain in read-only mode.
Figure 8.70 Sector Lock Sequence
CE#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Instruction = 24h
SI
High Impedance
SO
Figure 8.71 Sector Lock QPI Sequence
CE#
Mode 3 0
1
SCK
Mode 0
IO[3:0]
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8.43 AUTOBOOT
SPI devices normally require 32 or more cycles of command and address shifting to initiate a read command.
And, in order to read boot code from an SPI device, the host memory controller or processor must supply the
read command from a hardwired state machine or from some host processor internal ROM code.
Parallel NOR devices need only an initial address, supplied in parallel in a single cycle, and initial access time to
start reading boot code.
The AutoBoot feature allows the host memory controller to take boot code from the device immediately after the
end of reset, without having to send a read command. This saves 32 or more cycles and simplifies the logic
needed to initiate the reading of boot code.
As part of the power up reset, hardware reset, or command reset process the AutoBoot feature
automatically starts a read access from a pre-specified address. At the time the reset process is completed,
the device is ready to deliver code from the starting address. The host memory controller only needs to drive
CE# signal from high to low and begin toggling the SCK signal. The device will delay code output for a prespecified number of clock cycles before code streams out.
– The Auto Boot Start Delay (ABSD) field of the AutoBoot register specifies the initial delay if any is needed
by the host.
– The host cannot send commands during this time.
– If QE bit (Bit 6) in the Status Register is set to “1”, Fast Read Quad I/O operation will be selected and
initial delay is the same as dummy cycles of Fast Read Quad I/O Read operation. If it is set to “0”, Fast
Read operation will be applied and initial delay is the same as dummy cycles of Fast Read operation.
Maximum operation frequency will be 133MHz for both operations.
The starting address of the boot code is selected by the value programmed into the AutoBoot Start Address
(ABSA) field of the AutoBoot Register.
– Data will continuously shift out until CE# returns high.
At any point after the first data byte is transferred, when CE# returns high, the SPI device will reset to
standard SPI mode; able to accept normal command operations.
– A minimum of one byte must be transferred.
– AutoBoot mode will not initiate again until another power cycle or a reset occurs.
An AutoBoot Enable bit (ABE) is set to enable the AutoBoot feature.
The AutoBoot register bits are non-volatile and provide:
The starting address set by the AutoBoot Start Address (ABSA).
The number of initial delay cycles, set by the AutoBoot Start Delay (ABSD) 4-bit count value.
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Figure 8.72 AutoBoot Sequence (QE = 0)
CE #
Mode 3
0
1
2
...
n-1
n
n+2
n+1
n+3
n+4
n+5
n+6
n+7
n+8
n+9
...
n+10
SCK
Mode 0
SI
ABSD Delay (n)
tV
SO
7
6
5
3
4
2
1
0
7
...
6
High Impedance
Data Out 1
Data Out 2
...
Figure 8.73 AutoBoot Sequence (QE = 1)
CE #
Mode 3
0
1
2
...
n-1
n+2
n+1
n
n+3
n+4
n+5
n+7
n+6
n+9
n+8
n+10
...
SCK
Mode 0
ABSD Delay (n)
tV
IO0
4
0
4
0
4
0
4
0
4
0
...
IO1
5
1
5
1
5
1
5
1
5
1
...
IO2
6
2
6
2
6
2
6
2
6
2
...
IO3
7
3
7
3
7
3
7
3
7
3
...
High Impedance
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...
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AUTOBOOT REGISTER READ OPERATION (RDABR, 14h)
The AutoBoot Register Read command is shifted in. Then the 32-bit AutoBoot Register is shifted out, least
significant byte first, most significant bit of each byte first. It is possible to read the AutoBoot Register
continuously by providing multiples of 32 bits.
Figure 8.74 RDABR Sequence (QE = 1)
CE #
Mode 3
0
1
2
3
4
5
6
8
7
9
10
11
12
13
14
...
15
SCK
Mode 0
SI
Instruction = 14h
tV
SO
7
6
5
4
3
2
1
0
...
Data Out 1
Figure 8.75 RDABR QPI Sequence (QE = 1)
CE#
Mode 3 0
1
2
...
3
SCK
Mode 0
tV
IO[3:0]
14h
7:4
3:0
...
Data Out
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AUTOBOOT REGISTER WRITE OPERATION (WRABR, 15h)
Before the WRABR command can be accepted, a Write Enable (WREN) command must be issued and
decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write
operations.
The WRABR command is entered by shifting the instruction and the data bytes, least significant byte first, most
significant bit of each byte first. The WRABR data is 32 bits in length.
CE# must be driven high after the 32nd bit of data has been latched. If not, the WRABR command is not
executed. As soon as CE# is driven high, the WRABR operation is initiated. While the WRABR operation is in
progress, Status Register may be read to check the value of the Write-In Progress (WIP) bit. The WIP bit is “1”
during the WRABR operation, and is a 0 when it is completed. When the WRABR cycle is completed, the WEL
is set to “0”.
Figure 8.76 WRABR Sequence (QE = 1)
CE #
Mode 3
0
1
2
3
4
5
7
6
8
9
10
11
12
13
14
15
7
6
5
4
3
2
1
0
...
SCK
Mode 0
SI
Instruction = 15h
...
Data In 1
SO
High Impedance
Figure 8.77 WRABR QPI Sequence (QE = 1)
CE#
Mode 3 0
1
2
3
7:4
3:0
...
SCK
Mode 0
IO[3:0]
15h
...
Data In 1
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9. ELECTRICAL CHARACTERISTICS
9.1 ABSOLUTE MAXIMUM RATINGS
(1)
Storage Temperature
Surface Mount Lead Soldering Temperature
Input Voltage with Respect to Ground on All Pins
All Output Voltage with Respect to Ground
VCC
(2)
Electrostatic Discharge Voltage (Human Body Model)
Standard Package
Lead-free Package
-65°C to +150°C
240°C 3 Seconds
260°C 3 Seconds
-0.5V to VCC + 0.5V
-0.5V to VCC + 0.5V
-0.5V to +2.5V
-2000V to +2000V
Notes:
1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. ANSI/ESDA/JEDEC JS-001
9.2 OPERATING RANGE
Part Number
Operating Temperature (Extended Grade E)
Operating Temperature (Extended+ Grade E1)
Operating Temperature (Automotive Grade A1)
Operating Temperature (Automotive Grade A2)
Operating Temperature (Automotive Grade A3)
VCC Power Supply
Integrated Silicon Solution, Inc.- www.issi.com
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IS25WP016/080/040/020
-40°C to 105°C
-40°C to 125°C
-40°C to 85°C
-40°C to 105°C
-40°C to 125°C
1.65V (VMIN) – 1.95V (VMAX); 1.8V (Typ)
90
IS25WP016/080/040/020
9.3 DC CHARACTERISTICS
(Under operating range)
Symbol
ICC1
Parameter
VCC Active Read current
Condition
(3)
Min
Typ
(2)
NORD at 50MHz,
4
9
FRD Single at 133MHz
6
8
FRD Dual at 133MHz
8
10
FRD Quad at 133MHz
10
13
FRD Quad at 84MHz
8
10
FRD Quad at 104MHz
9
11
FRD Single DDR at 66MHz
6
8
FRD Dual DDR at 66MHz
8
10
FRD Quad DDR at 66MHz
10
13
ICC3
ICC4
ICC5
ISB1
VCC Program Current
VCC WRSR Current
VCC Erase Current (4K/32K/64K)
VCC Erase Current (CE)
VCC Standby Current CMOS
CE# = VCC
CE# = VCC
CE# = VCC
CE# = VCC
CE# = VCC,
CE#, RESET#(4) = VCC
105°C
25
30
85°C
28(6)
105°C
25
Deep power down current
29(6)
mA
125°C
30
85°C
28(6)
105°C
25
29(6)
125°C
30
85°C
28(6)
105°C
25
29(6)
125°C
30
85°C
20(6)
105°C
8
35(6)
µA
50
5(6)
85°C
ISB2
mA
29(6)
125°C
125°C
CE# = VCC,
CE#, RESET#(4) = VCC
Units
28(6)
85°C
ICC2
Max
105°C
1
125°C
10(6)
µA
15
ILI
Input Leakage Current
VIN = 0V to VCC
±1(5)
µA
ILO
Output Leakage Current
VIN = 0V to VCC
±1(5)
µA
(1)
Input Low Voltage
-0.5
0.3VCC
V
(1)
VIH
Input High Voltage
0.7VCC
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 100 µA
0.2
V
VOH
Output High Voltage
IOH = -100 µA
VIL
VCC - 0.2
V
Notes:
1. Maximum DC voltage on input or I/O pins is VCC + 0.5V. During voltage transitions, input or I/O pins may
overshoot VCC by + 2.0V for a period of time not to exceed 20ns. Minimum DC voltage on input or I/O pins is
-0.5V. During voltage transitions, input or I/O pins may undershoot GND by -2.0V for a period of time not to
exceed 20ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at
VCC = VCC (Typ), TA=25°C.
3. Outputs are unconnected during reading data so that output switching current is not included.
4. Only for the dedicated RESET# pin.
5. The Max of ILI and ILO for the dedicated RESET# pin is ±2µA.
6. These parameters are characterized and are not 100% tested.
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9.4 AC MEASUREMENT CONDITIONS
Symbol
Max
Units
Load Capacitance up to 104MHz
30
pF
Load Capacitance up to 133MHz
15
pF
TR,TF
Input Rise and Fall Times
5
ns
VIN
Input Pulse Voltages
0.2VCC to 0.8VCC
V
VREFI
Input Timing Reference Voltages
0.3VCC to 0.7VCC
V
VREFO
Output Timing Reference Voltages
0.5VCC
V
CL
Parameter
Min
Figure 9.1 Output test load & AC measurement I/O Waveform
0.8VCC
Input
AC
Measurement
Level
VCC/2
1.8k
0.2VCC
OUTPUT PIN
1.2k
15/30pf
9.5 PIN CAPACITANCE (TA = 25°C, VCC=1.8V, 1MHZ)
Symbol
CIN
CIN/OUT
Parameter
Input Capacitance
(CE#, SCK)
Input/Output Capacitance
(other pins)
Test Condition
Min
Typ
Max
Units
VIN = 0V
-
-
6
pF
VIN/OUT = 0V
-
-
8
pF
Note:
1. These parameters are characterized and not 100% tested.
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9.6 AC CHARACTERISTICS
(Under operating range, refer to section 9.4 for AC measurement conditions)
Symbol
Min
(1)
tCLCH
SCK Rise Time (peak to peak)
0.1
V/ns
(1)
SCK Fall Time ( peak to peak)
0.1
V/ns
fCT
fC2, fT2, fQ2
fC
tCHCL
For read mode
Typ
(3)
Parameter
Clock Frequency for fast read mode:
SPI, Dual, Dual I/O, Quad I/O, and QPI.
Clock Frequency for fast read DTR:
SPI DTR, Dual DTR, Dual I/O DTR, Quad I/O DTR, and
QPI DTR.
Clock Frequency for read mode SPI
Max
Units
0
133
MHz
0
66
MHz
0
50
MHz
45% fC
tCKH
SCK High Time
tCKL
SCK Low Time
tCEH
CE# High Time
7
ns
tCS
CE# Setup Time
5
ns
tCH
CE# Hold Time
6
ns
tDS
Data In Setup Time
tDH
Data in Hold Time
tV
Output Valid
tOH
Output Hold Time
(1)
tDIS
Output Disable Time
tHLCH
HOLD Active Setup Time relative to SCK
2
ns
tCHHH
HOLD Active Hold Time relative to SCK
2
ns
tHHCH
HOLD Not Active Setup Time relative to SCK
2
ns
tCHHL
HOLD Not Active Hold Time relative to SCK
2
tLZ
For others
For read mode
For others
Normal Mode
DTR Mode
Normal Mode
DTR Mode
ns
45% fCT/C2/T2/Q2
45% fC
ns
45% fCT/C2/T2/Q2
2
ns
1.5
2
ns
1.5
@ 133MHz (CL = 15pF)
7
@ 104MHz (CL = 30pF)
8
2
ns
ns
8
ns
ns
(1)
HOLD to Output Low Z
12
ns
(1)
HOLD to Output High Z
12
ns
70
300
ms
Block Erase Time (32Kbyte)
0.1
0.5
s
Block Erase time (64Kbyte)
0.15
1.0
s
2Mb
0.5
1.7
4Mb
1
3
8Mb
2
6
16Mb
4
12
0.2
0.8
tHZ
Sector Erase Time (4Kbyte)
tEC
Chip Erase Time
tPP
Page Program Time
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93
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Symbol
tRES1
(1)
Parameter
Deep power down
tW
Write Status Register time
(1)
tSRST
(1)
tRESET
(1)
tHWRST
(1)
Typ
Release deep power down
(1)
tDP
tSUS
Min
(3)
Max
Units
5
µs
3
µs
15
ms
Suspend to read ready
100
µs
Software Reset recovery time
100
µs
RESET# pin low pulse width
Hardware Reset recovery time
2
1
(2)
µs
100
µs
Notes:
1. These parameters are characterized and not 100% tested.
2. If the RESET# pulse is driven for a period shorter than 1µs (tRESET minimum), it may still reset the device,
however the 1µs minimum period is recommended to ensure reliable operation.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at
VCC = VCC (Typ), TA=25°C.
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9.7 SERIAL INPUT/OUTPUT TIMING
Figure 9.2 SERIAL INPUT/OUTPUT TIMING (Normal Mode)
(1)
tCEH
CE#
tCS
tCH
tCKH
SCK
tDS
SI
tCKL
tDH
VALID IN
VALID IN
tV
SO
HI-Z
tOH
tDIS
HI-Z
VALID OUTPUT
Note1: For SPI Mode 0 (0,0)
Figure 9.3 SERIAL INPUT/OUTPUT TIMING (DTR Mode)
(1)
tCEH
CE#
tCS
tCH
tCKH
SCK
tDS
SI
tCKL
tDH
VALID IN
VALID IN
VALID IN
tV
SO
HI-Z
tV
Output
tOH
Output
tDIS
HI-Z
Note1: For SPI Mode 0 (0,0)
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Figure 9.4 HOLD TIMING
CE#
tHLCH
tCHHL
tHHCH
SCK
tCHHH
tHZ
tLZ
SO
SI
HOLD#
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9.8 POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must be NOT SELECTED until Vcc reaches at the right level. (Adding
a simple pull-up resistor on CE# is recommended.)
Power up timing
VCC
VCC(max)
All Write Commands are Rejected
Chip Selection Not Allowed
VCC(min)
Reset State
tVCE
Read Access Allowed
V(write inhibit)
Device fully
accessible
tPUW
Symbol
Min.
Vcc(min) to CE# Low
1
(1)
Power-up time delay to write instruction
1
tVCE
tPUW
VWI
Parameter
(1)
(1)
Write Inhibit Voltage
Max
Unit
ms
10
ms
1.4
V
Note: These parameters are characterized and not 100% tested.
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9.9 PROGRAM/ERASE PERFORMANCE
Parameter
Typ
Max
Unit
Sector Erase Time (4Kbyte)
70
300
ms
Block Erase Time (32Kbyte)
0.1
0.5
s
Block Erase Time (64Kbyte)
0.15
1.0
s
2Mb
0.5
1.7
4Mb
1
3
8Mb
2
6
Chip Erase Time
16Mb
s
4
12
Page Programming Time
0.2
0.8
ms
Byte Program
8
40
µs
Note: These parameters are characterized and not 100% tested.
9.10 RELIABILITY CHARACTERISTICS
Parameter
Min
Max
Unit
Test Method
Endurance
100,000
-
Cycles
JEDEC Standard A117
Data Retention
20
-
Years
JEDEC Standard A117
Latch-Up
-100
+100
mA
JEDEC Standard 78
Note: These parameters are characterized and not 100% tested.
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IS25WP016/080/040/020
10. PACKAGE TYPE INFORMATION
10.1 8-PIN JEDEC 208MIL BROAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) PACKAGE (B)
Note: Lead co-planarity is 0.1mm.
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IS25WP016/080/040/020
10.2 8-PIN JEDEC 150MIL BROAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) PACKAGE (N)
Note: Lead co-planarity is 0.08mm.
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10.3 8-PIN TSSOP PACKAGE (D)
Note: Lead co-planarity is 0.08mm.
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10.4 8-PIN 150MIL VVSOP PACKAGE (V)
Note: Lead co-planarity is 0.08mm.
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10.5 8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD (WSON) PACKAGE 6X5MM (K)
Note: Lead co-planarity is 0.08mm.
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10.6 8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD (USON) PACKAGE 4X3MM (T)
Note: Lead co-planarity is 0.08mm.
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10.7 8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD (USON) PACKAGE 2X3MM (U)
Note: Lead co-planarity is 0.08mm.
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IS25WP016/080/040/020
10.8 8-PIN 208MIL VSOP PACKAGE (F)
Note: Lead co-planarity is 0.1mm.
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IS25WP016/080/040/020
10.9 16-LEAD PLASTIC SMALL OUTLINE PACKAGE (300 MILS BODY WIDTH) (M)
Note: Lead co-planarity is 0.08mm.
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IS25WP016/080/040/020
10.10 24-BALL THIN PROFILE FINE PITCH BGA 6X8MM (G)
A1 Corner
Index Area
(TOP VIEW)
A1 Corner
Index Area
(BOTTOM VIEW)
Note: Lead co-planarity is 0.08mm.
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11. ORDERING INFORMATION - Valid Part Numbers
IS25WP016
-
J
B
L
E
TEMPERATURE RANGE
E = Extended (-40°C to +105°C)
E1 = Extended+ (-40°C to +125°C)
A1 = Automotive Grade (-40°C to +85°C)
A2 = Automotive Grade (-40°C to +105°C)
A3 = Automotive Grade (-40°C to +125°C)
PACKAGING CONTENT
L = RoHS compliant
(1),(2)
PACKAGE Type
B = 8-pin SOIC 208mil
N = 8-pin SOIC 150mil
D = 8-pin TSSOP
V = 8-pin VVSOP 150mil
K = 8-contact WSON 6x5mm
T = 8-contact USON 4x3mm
U = 8-contact USON 2x3mm
F = 8-pin VSOP 208mil
M = 16-pin SOIC 300mil
G = 24-ball TFBGA 6x8mm
W = KGD (Call Factory)
Option
J = Standard
R = Dedicated RESET# pin option for 16-pin SOIC and 24ball TFBGA
Die Revision
Blank = First Revision
Density
016 = 16 Megabit
080 = 8 Megabit
040 = 4 Megabit
020 = 2 Megabit
BASE PART NUMBER
IS = Integrated Silicon Solution Inc.
25WP = FLASH, 1.65V ~ 1.95V, QPI
Notes:
1. IS25WP016 (not available in D) and IS25WP080/040 (not available in D, M, G) and
IS25WP020 (not available in T, F, M, G)
2. Call Factory for WLCSP package or other package options available
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IS25WP016/080/040/020
Density
16Mb
8Mb
Frequency (MHz)
133
133
Order Part Number(1)
Package
IS25WP016-JBLE
IS25WP016-JBLE1
8-pin SOIC 208mil
IS25WP016-JNLE
IS25WP016-JNLE1
8-pin SOIC 150mil
IS25WP016-JVLE
IS25WP016-JVLE1
8-pin VVSOP 150mil
IS25WP016-JKLE
IS25WP016-JKLE1
8-contact WSON 6x5mm
IS25WP016-JTLE
IS25WP016-JTLE1
8-contact USON 4x3mm
IS25WP016-JULE
IS25WP016-JULE1
8-contact USON 2x3mm
IS25WP016-JFLE
IS25WP016-JFLE1
8-pin VSOP 208mil
IS25WP016-JMLE
IS25WP016-JMLE1
16-pin SOIC 300mil
IS25WP016-JGLE
IS25WP016-JGLE1
24-ball TFBGA 6x8mm
IS25WP016-RMLE
IS25WP016-RMLE1
16-pin SOIC 300mil(2)
IS25WP016-RGLE
IS25WP016-RGLE1
24-ball TFBGA 6x8mm (2)
IS25WP016-JBLA*
8-pin SOIC 208mil (Call Factory)
IS25WP016-JNLA*
8-pin SOIC 150mil (Call Factory)
IS25WP016-JVLA*
8-pin VVSOP 150mil (Call Factory)
IS25WP016-JKLA*
8-contact WSON 6x5mm (Call Factory)
IS25WP016-JTLA*
8-contact USON 4x3mm (Call Factory)
IS25WP016-JULA*
8-contact USON 2x3mm (Call Factory)
IS25WP016-JFLA*
8-pin VSOP 208mil (Call Factory)
IS25WP016-JMLA*
16-pin SOIC 300mil (Call Factory)
IS25WP016-JGLA*
24-ball TFBGA 6x8mm (Call Factory)
IS25WP016-RMLA*
16-pin SOIC 300mil(2) (Call Factory)
IS25WP016-RGLA*
24-ball TFBGA 6x8mm (2)
IS25WP016-JWLE
KGD (Call Factory)
IS25WP080-JBLE
IS25WP080-JBLE1
8-pin SOIC 208mil
IS25WP080-JNLE
IS25WP080-JNLE1
8-pin SOIC 150mil
IS25WP080-JVLE
IS25WP080-JVLE1
8-pin VVSOP 150mi
IS25WP080-JKLE
IS25WP080-JKLE1
8-contact WSON 6x5mm
IS25WP080-JTLE
IS25WP080-JTLE1
8-contact USON 4x3mm
IS25WP080-JULE
IS25WP080-JULE1
8-contact USON 2x3mm
IS25WP080-JFLE
IS25WP080-JFLE1
8-pin VSOP 208mil
IS25WP080-JBLA*
8-pin SOIC 208mil (Call Factory)
IS25WP080-JNLA*
8-pin SOIC 150mil (Call Factory)
IS25WP080-JVLA*
8-pin VVSOP 150mil (Call Factory)
IS25WP080-JKLA*
8-contact WSON 6x5mm (Call Factory)
IS25WP080-JTLA*
8-contact USON 4x3mm (Call Factory)
IS25WP080-JULA*
8-contact USON 2x3mm (Call Factory)
IS25WP080-JFLA*
8-pin VSOP 208mil (Call Factory)
IS25WP080-JWLE
KGD (Call Factory)
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IS25WP016/080/040/020
Density
4Mb
2Mb
Frequency (MHz)
133
133
Order Part Number(1)
Package
IS25WP040-JBLE
IS25WP040-JBLE1
8-pin SOIC 208mil
IS25WP040-JNLE
IS25WP040-JNLE1
8-pin SOIC 150mil
IS25WP040-JVLE
IS25WP040-JVLE1
8-pin VVSOP 150mi
IS25WP040-JKLE
IS25WP040-JKLE1
8-contact WSON 6x5mm
IS25WP040-JTLE
IS25WP040-JTLE1
8-contact USON 4x3mm
IS25WP040-JULE
IS25WP040-JULE1
8-contact USON 2x3mm
IS25WP040-JFLE
IS25WP040-JFLE1
8-pin VSOP 208mil
IS25WP040-JBLA*
8-pin SOIC 208mil (Call Factory)
IS25WP040-JNLA*
8-pin SOIC 150mil (Call Factory)
IS25WP040-JVLA*
8-pin VVSOP 150mil (Call Factory)
IS25WP040-JKLA*
8-contact WSON 6x5mm (Call Factory)
IS25WP040-JTLA*
8-contact USON 4x3mm (Call Factory)
IS25WP040-JULA*
8-contact USON 2x3mm (Call Factory)
IS25WP040-JFLA*
8-pin VSOP 208mil (Call Factory)
IS25WP040-JWLE
KGD (Call Factory)
IS25WP020-JBLE
IS25WP020-JBLE1
8-pin SOIC 208mil
IS25WP020-JNLE
IS25WP020-JNLE1
8-pin SOIC 150mil
IS25WP020-JDLE
IS25WP020-JDLE1
8-pin TSSOP
IS25WP020-JVLE
IS25WP020-JVLE1
8-pin VVSOP 150mil
IS25WP020-JKLE
IS25WP020-JKLE1
8-contact WSON 6x5mm
IS25WP020-JULE
IS25WP020-JULE1
8-contact USON 2x3mm
IS25WP020-JBLA*
8-pin SOIC 208mil (Call Factory)
IS25WP020-JNLA*
8-pin SOIC 150mil (Call Factory)
IS25WP020-JDLA*
8-pin TSSOP (Call Factory)
IS25WP020-JVLA*
8-pin VVSOP 150mil (Call Factory)
IS25WP020-JKLA*
8-contact WSON 6x5mm (Call Factory)
IS25WP020-JULA*
8-contact USON 2x3mm (Call Factory)
IS25WP020-JWLE
KGD (Call Factory)
Notes:
1. A* = A1, A2, A3: Meets AEC-Q100 requirements with PPAP, E1= Extended+ non-Auto qualified
Temp Grades: E= -40 to 105°C, E1= -40 to 125°C, A1= -40 to 85°C, A2= -40 to 105°C, A3= -40 to 125°C
2. The dedicated parts have additional RESET# pin on pin3.
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