IS25WQ040/020
IS25WQ040
IS25WQ020
4M/2M-BIT
1.8V QUAD SERIAL FLASH
MEMORY WITH
104MHZ MULTI I/O SPI
DATA SHEET
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IS25WQ040/020
4M/2M-BIT 1.8V QUAD SERIAL FLASH MEMORY WITH MULTI-I/O SPI
FEATURES
Industry Standard Serial Interface
- IS25WQ040: 4M-bit/ 512K-byte
- IS25WQ020: 2M-bit/ 256K-byte
- 256-bytes per Programmable Page Standard
- Standard SPI/Dual/Quad Multi-I/O SPI
High Performance Serial Flash (SPI)
-
33MHz SPI Normal Read
104 MHz SPI/Dual/Quad Multi-I/O SPI
416 MHz equivalent Quad SPI
52MB/S Continuous Data Throughput
Supports SPI Modes 0 and 3
- More than 100,000 Erase/Program Cycles(1)
- More than 20-year Data Retention
Efficient Read and Program modes
- Low Instruction Overhead Operations
- Continuous data read
- Allows XIP operations (execute in place)
- Outperforms X16 Parallel Flash
Flexible & Cost Efficient Memory Architecture
- Uniform 4 Kbyte Sectors or 32/64 Kbyte Blocks
- Flexible 4, 32, 64 K-bytes, or Chip Erase
- Standard Page Program 1 to 256 bytes
- Program/Erase Suspend and Resume
Low Power with Wide Temp. Ranges
- Single 1.65V to 1.95V Voltage Supply
- 8 mA Active Read Current (typ)
- 15 µA Standby Current (typ.)
- 2 µA Deep Power Down (typ.)
- Temp Grades:
Extended: -40°C to +105°C
Advanced Security Protection
- Software and Hardware Write Protection
- 256-Byte dedicated security area, One
Time Programmable (OTP) Memory
- 128 bit Unique ID for each device (Call Factory)
Industry Standard Pin-out & Pb-Free Packages2
- JN = 8-pin SOIC 150mil
- JB = 8-pin SOIC 208mil
- JV = 8-pin VVSOP 150mil (Call Factory)
- JK = 8-contact WSON 6x5mm
- JU = 8-contact USON 2x3mm
- KGD (Call Factory)
Note2: Call Factory for other package options available
GENERAL DESCRIPTION
The IS25WQ040/020 (4M/2Mbit) Serial Flash memory offers a storage solution with flexibility and performance in a
simplified pin count package. ISSI’s “Industry Standard Serial Interface” is for systems that have limited space, pins,
and power. The IS25WQ040/020 is accessed through a 4-wire SPI Interface consisting of a Serial Data Input (SI), Serial
Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins, which also serve as multi-function I/O pins in Dual
and Quad modes (see pin descriptions). The IS25xQ series of Flash is ideal for code shadowing to RAM, execute in
place (XIP) operations, and storing non-volatile data.
The memory array is organized into programmable pages of 256-bytes each. The IS25WQ040/020 supports page
program mode where 1 to 256 bytes of data can be programmed into the memory with one command. Pages can be
erased in groups of 4K-byte sectors, 32K-byte blocks, 64K-byte blocks, and/or the entire chip. The uniform sectors and
blocks allow greater flexibility for a variety of applications requiring solid data retention.
The device supports the standard Serial Peripheral Interface (SPI), Dual/Quad output (SPI), and Dual/Quad I/O (SPI).
Clock frequencies of up to 104MHz for all read modes allow for equivalent clock rates of up to 416MHz (104MHz x 4)
allowing up to 52MBytes/S of throughput. These transfer rates can outperform 16-bit Parallel Flash memories allowing
for efficient memory access for a XIP (execute in place) operation. The IS25WQ040/020 is manufactured using industry
leading non-volatile memory technology and offered in industry standard lead-free packages. See Ordering Information
for the density and package combinations available.
Note1: 100,000 Continuous Chip and Block cycling, 100,000 Continuous Sector cycling.
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IS25WQ040/020
TABLE OF CONTENTS
FEATURES .......................................................................................................................................................... 2
GENERAL DESCRIPTION .................................................................................................................................. 2
1.
PIN CONFIGURATION ................................................................................................................................. 5
2.
PIN DESCRIPTIONS .................................................................................................................................... 6
3.
BLOCK DIAGRAM ........................................................................................................................................ 7
4.
SPI MODES DESCRIPTION ........................................................................................................................ 8
5.
SYSTEM CONFIGURATION ...................................................................................................................... 10
5.1 BLOCK/SECTOR ADDRESSES .......................................................................................................... 11
6.
REGISTERS ............................................................................................................................................... 12
6.1. STATUS REGISTER ........................................................................................................................... 12
6.2. FUNCTION REGISTER ....................................................................................................................... 15
7.
PROTECTION MODE................................................................................................................................. 16
7.1 HARDWARE WRITE PROTECTION.................................................................................................... 16
7.2 SOFTWARE WRITE PROTECTION .................................................................................................... 16
8.
DEVICE OPERATION ................................................................................................................................ 17
8.1 READ DATA OPERATION (RD, 03h) .................................................................................................. 18
8.2 FAST READ DATA OPERATION (FR, 0Bh) ........................................................................................ 20
8.3 HOLD OPERATION .............................................................................................................................. 21
8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBh) ........................................................................... 21
8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh) .................................................................. 24
8.6 FAST READ QUAD OUTPUT (FRQO, 6Bh) ........................................................................................ 26
8.7 FAST READ QUAD I/O OPERATION (FRQIO, EBh) .......................................................................... 28
8.8 PAGE PROGRAM OPERATION (PP, 02h) .......................................................................................... 31
8.9 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h) ............................................................... 32
8.10 ERASE OPERATION ......................................................................................................................... 33
8.11 SECTOR ERASE OPERATION (SER, D7h/20h) ............................................................................... 33
8.12 BLOCK ERASE OPERATION (BER32K:52h, BER64K:D8h) ............................................................ 34
8.13 CHIP ERASE OPERATION (CER, C7h/60h) ..................................................................................... 35
8.14 WRITE ENABLE OPERATION (WREN, 06h) .................................................................................... 36
8.15 WRITE DISABLE OPERATION (WRDI, 04h) ..................................................................................... 36
8.16 READ STATUS REGISTER OPERATION (RDSR, 05h) ................................................................... 37
8.17 WRITE STATUS REGISTER OPERATION (WRSR, 01h) ................................................................. 37
8.18 READ FUNCTION REGISTER OPERATION (RDFR, 07h) ............................................................... 38
8.19 PROGRAM/ERASE SUSPEND & RESUME ...................................................................................... 39
8.20 DEEP POWER DOWN (DP, B9h) ...................................................................................................... 41
8.21 RELEASE DEEP POWER DOWN (RDPD, ABh) ............................................................................... 42
8.22 READ PRODUCT IDENTIFICATION (RDID, ABh) ............................................................................ 43
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IS25WQ040/020
8.23 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9Fh) ........................... 44
8.24 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90h) ........................ 45
8.25 READ UNIQUE ID NUMBER (RDUID, A1h) ...................................................................................... 46
8.26 SECURITY INFORMATION ROW (OTP MEMORY) ......................................................................... 47
8.27 INFORMATION ROW PROGRAM OPERATION (IRP, B1h) ............................................................. 48
8.28 INFORMATION ROW READ OPERATION (IRRD, 4Bh) ................................................................... 49
8.29 SECTOR LOCK/UNLOCK FUNCTIONS ............................................................................................ 50
9.
ELECTRICAL CHARACTERISTICS........................................................................................................... 52
9.1 ABSOLUTE MAXIMUM RATINGS (1) ................................................................................................... 52
9.2 OPERATING RANGE ........................................................................................................................... 52
9.3 DC CHARACTERISTICS ...................................................................................................................... 53
9.4 AC MEASUREMENT CONDITIONS .................................................................................................... 54
9.5 PIN CAPACITANCE (TA = 25°C, VCC=1.8V, 1MHz) .......................................................................... 54
9.6 AC CHARACTERISTICS ...................................................................................................................... 55
9.7 SERIAL INPUT/OUTPUT TIMING (1) .................................................................................................... 56
9.8 POWER-UP AND POWER-DOWN ...................................................................................................... 57
9.9 PROGRAM/ERASE PERFORMANCE ................................................................................................. 58
9.10 RELIABILITY CHARACTERISTICS1 .................................................................................................. 58
10.
PACKAGE TYPE INFORMATION ......................................................................................................... 59
10.1 8-Pin JEDEC 150mil Broad Small Outline Integrated Circuit (SOIC) Package (JN) .......................... 59
10.2 8-Pin 150mil VVSOP Package (JV) .................................................................................................... 60
10.3 8-Contact Ultra-Thin Small Outline No-Lead (WSON) 6x5mm Package (JK) .................................... 61
10.4 8-Contact Ultra-Thin Small Outline No-Lead (USON) Package 2x3mm (JU) .................................... 62
10.5 8-Pin JEDEC 208mil Broad Small Outline Integrated Circuit (SOIC) Package (JB) .......................... 63
11.
ORDERING INFORMATION - Valid Part Numbers ............................................................................... 64
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IS25WQ040/020
1. PIN CONFIGURATION
CE#
8
1
SO (IO1)
2
7
Vcc
CE#
1
8 Vcc
SO (IO1)
2
7 HOLD# (IO3)
WP# (IO2)
3
6 SCK
GND
4
5 SI (IO0)
HOLD# (IO3)
WP# (IO2)
3
6
SCK
GND
4
5
SI (IO0)
8-contact WSON 6x5mm (Package: JK)
8-pin SOIC 150mil (Package: JN)
8-pin SOIC 208mil (Package: JB)
8-pin VVSOP 150mil (Package: JV)
CE#
1
8
Vcc
SO (IO1)
2
7
HOLD# (IO3)
WP# (IO2)
3
6
SCK
GND
4
5
SI (IO0)
8-contact USON 2x3mm (Package: JU)
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IS25WQ040/020
2. PIN DESCRIPTIONS
SYMBOL
TYPE
DESCRIPTION
Chip Enable: The Chip Enable (CE#) pin enables and disables the devices
operation. When CE# is high the device is deselected and output pins are in a high
impedance state. When deselected the devices non-critical internal circuitry power
down to allow minimal levels of power consumption while in a standby state.
CE#
INPUT
When CE# is pulled low the device will be selected and brought out of standby mode.
The device is considered active and instructions can be written to, data read, and
written to the device. After power-up, CE# must transition from high to low before a
new instruction will be accepted.
Keeping CE# in a high state deselects the device and switches it into its low power
state. Data will not be accepted when CE# is high.
Serial Data Input, Serial Output, and IOs (SI, SO, IO0, and IO1):
SI (IO0),
SO (IO1)
INPUT/OUTPUT
This device supports standard SPI, Dual SPI, and Quad SPI operation. Standard
SPI instructions use the unidirectional SI (Serial Input) pin to write instructions,
addresses, or data to the device on the rising edge of the Serial Clock (SCK).
Standard SPI also uses the unidirectional SO (Serial Output) to read data or status
from the device on the falling edge of the serial clock (SCK).
In Dual and Quad SPI mode, SI and SO become bidirectional IO pins to write
instructions, addresses or data to the device on the rising edge of the Serial Clock
(SCK) and read data or status from the device on the falling edge of SCK. Quad SPI
instructions use the WP# and HOLD# pins as IO2 and IO3 respectively.
WP# (IO2)
INPUT/OUTPUT
Write Protect/Serial Data IO (IO2): The WP# pin protects the Status Register from
being written in conjunction with the SRWD bit. When the SRWD is set to “1” and
the WP# is pulled low, the Status Register bits (SRWD, QE, BP3, BP2, BP1, BP0)
are write-protected and vice-versa for WP# high. When the SRWD is set to “0”, the
Status Register is not write-protected regardless of WP# state.
When the QE bit is set to “1”, the WP# pin (Write Protect) function is not available
since this pin is used for IO2.
Hold/Serial Data IO (IO3): Pauses serial communication by the master device
without resetting the serial sequence. When the QE bit of Status Register is set to
“1”, HOLD# pin is not available since it becomes IO3.
HOLD# (IO3)
INPUT/OUTPUT
The HOLD# pin allows the device to be paused while it is selected. The HOLD# pin
is active low. When HOLD# is in a low state, and CE# is low, the SO pin will be at
high impedance.
Device operation can resume when HOLD# pin is brought to a high state. When the
QE bit of Status Register is set for Quad I/O, the HOLD# pin function is not available
and becomes IO3 for Multi-I/O SPI mode.
SCK
INPUT
Vcc
POWER
GND
GROUND
NC
Unused
Serial Data Clock: Synchronized Clock for input and output timing operations.
Power: Device Core Power Supply
Ground: Connect to ground when referenced to Vcc
NC: Pins labeled “NC” stand for “No Connect” and should be left uncommitted.
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IS25WQ040/020
3. BLOCK DIAGRAM
Control Logic
High Voltage Generator
Status
Register
I/O Buffers and
Data Latches
256 Bytes
Page Buffer
SCK
WP#
(IO2)
SI
(IO0)
SO
(IO1)
Serial Peripheral Interface
CE#
X-Decoder
HOLD#
(IO3)
Y-Decoder
Memory Array
Address Latch &
Counter
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IS25WQ040/020
4. SPI MODES DESCRIPTION
Multiple IS25WQ040/020 devices can be connected on the SPI serial bus and controlled by a SPI Master, i.e.
microcontroller, as shown in Figure 4.1 the devices support either of two SPI modes:
Mode 0 (0, 0)
Mode 3 (1, 1)
The difference between these two modes is the clock polarity. When the SPI master is in stand-by mode, the
serial clock remains at “0” (SCK = 0) for Mode 0 and the clock remains at “1” (SCK = 1) for Mode 3. Please refer
to Figure 4.2 for SPI mode. In SPI mode, the input data is latched on the rising edge of Serial Clock (SCK), and
the output data is available from the falling edge of SCK.
Figure 4.1 Connection Diagram among SPI Master and SPI Slaves (Memory Devices)
SDO
SPI interface with
(0,0) or (1,1)
SDI
SCK
SCK SO
SI
SCK SO
SI
SCK SO
SI
SPI Master
(i.e. Microcontroller)
CS3
CS2
SPI
Memory
Device
CS1
CE#
SPI
Memory
Device
CE#
WP# HOLD#
SPI
Memory
Device
CE#
WP# HOLD#
WP# HOLD#
Notes:
1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as necessary.
2. SI and SO pins become bidirectional IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3 respectively
during Multi-IO mode.
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IS25WQ040/020
Figure 4.2 SPI Mode Support
SCK
Mode 0 (0,0)
SCK
Mode 3 (1,1)
SI
MSB
SO
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IS25WQ040/020
5. SYSTEM CONFIGURATION
The IS25WQ040/020 is designed to interface directly with the synchronous Serial Peripheral Interface (SPI)
microcontrollers or any SPI interface-equipped system controllers.
The memory array of IS25WQ040/020 is divided into uniform 4 Kbyte sectors or uniform 32/64 Kbyte blocks (a
block consists of eight/sixteen adjacent sectors respectively).
Table 5.1 illustrates the memory map of the device. The Status Register controls how the memory is protected.
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IS25WQ040/020
5.1 BLOCK/SECTOR ADDRESSES
Table 5.1 Block/Sector Addresses of IS25WQ040/020
Memory Density
Block No.
(64Kbyte)
Block No.
(32Kbyte)
Block 0
Block 0
Block 1
Block 2
Block 1
Block 3
2 Mbit
Block 4
Block 2
Block 5
Block 6
Block 3
Block 7
4 Mbit
Block 8
Block 4
Block 9
Block 10
Block 5
Block 11
Block 12
Block 6
Block 13
Block 14
Block 7
Block 15
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Sector 0
Sector
Size
(Kbyte)
4
000000h - 000FFFh
:
:
:
Sector No.
Address Range
:
:
:
Sector 15
4
00F000h - 00FFFFh
Sector 16
4
010000h - 010FFFh
:
:
:
:
:
:
Sector 31
4
01F000h - 01FFFFh
Sector 32
4
020000h - 020FFFh
:
:
:
:
:
:
Sector 47
4
02F000h - 02FFFFh
Sector 48
4
030000h - 030FFFh
:
:
:
:
:
:
Sector 63
4
03F000h - 03FFFFh
Sector 64
4
040000h - 040FFFh
:
:
:
:
:
:
Sector 79
4
04F000h - 04FFFFh
Sector 80
4
050000h - 050FFFh
:
:
:
:
:
:
Sector 95
4
05F000h - 05FFFFh
Sector 96
4
060000h - 060FFFh
:
:
:
:
:
:
Sector 111
4
06F000h - 06FFFFh
Sector 112
4
070000h - 070FFFh
:
:
:
:
:
:
Sector 127
4
07F000h - 07FFFFh
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IS25WQ040/020
6. REGISTERS
The IS25WQ040/020 has two sets of Registers: Status, Function.
6.1. STATUS REGISTER
Status Register Format and Status Register Bit Definitions are described in Tables 6.1 & 6.2.
Table 6.1 Status Register Format
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRWD
QE
BP3
BP2
BP1
BP0
WEL
WIP
0
0
0
0
0
0
0
0
Table 6.2 Status Register Bit Definition
Bit
Name
Bit 0
WIP
Bit 1
WEL
Bit 2
BP0
Bit 3
BP1
Bit 4
BP2
Bit 5
BP3
Bit 6
QE
Bit 7
SRWD
Definition
Write In Progress Bit:
"0" indicates the device is ready(default)
"1" indicates a write cycle is in progress and the device is busy
Write Enable Latch:
"0" indicates the device is not write enabled (default)
"1" indicates the device is write enabled
Block Protection Bit: (See Table 6.4 for details)
"0" indicates the specific blocks are not write-protected (default)
"1" indicates the specific blocks are write-protected
Quad Enable bit:
“0” indicates the Quad output function disable (default)
“1” indicates the Quad output function enable
Status Register Write Disable: (See Table 7.1 for details)
"0" indicates the Status Register is not write-protected (default)
"1" indicates the Status Register is write-protected
Read/Write
Type
R
Volatile
R/W
Volatile
R/W
Non-Volatile
R/W
Non-Volatile
R/W
Non-Volatile
The BP0, BP1, BP2, BP3 and SRWD are non-volatile memory cells that can be written by a Write Status Register
(WRSR) instruction. The default value of the BP3, BP2, BP1, BP0, and SRWD bits were set to “0” at factory. The
Status Register can be read by the Read Status Register (RDSR).
The function of Status Register bits are described as follows:
WIP bit: The Write In Progress (WIP) bit is read-only, and can be used to detect the progress or completion of a
program or erase operation. When the WIP bit is “0”, the device is ready for Write Status Register, program or
erase operation. When the WIP bit is “1”, the device is busy.
WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal write enable latch. When the WEL
is “0”, the write enable latch is disabled and all write operations described in Table 6.3 are inhibited. When the
WEL bit is “1”, write operations are allowed. The WEL bit is set by a Write Enable (WREN) instruction. Each write
register, program and erase instruction must be preceded by a WREN instruction. The WEL bit can be reset by a
Write Disable (WRDI) instruction. It will automatically be reset after the completion of any write operation.
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Table 6.3 Instructions requiring WREN instruction ahead
Instructions must be preceded by the WREN instruction
Name
Hex Code
Operation
PP
02h
Input Page Program
PPQ
32h
Quad Input Page Program
SER
D7h/20h
Sector Erase
BER32 (32Kb)
52h
Block Erase 32K
BER64 (64Kb)
D8h
Block Erase 64K
CER
C7h/60h
Chip Erase
WRSR
01h
Write Status Register
IRP
62h
Program Information Row
BP3, BP2, BP1, BP0 bits: The Block Protection (BP3, BP2, BP1 and BP0) bits are used to define the portion of
the memory area to be protected. Refer to Table 6.4 for the Block Write Protection (BP) bit settings. When a
defined combination of BP3, BP2, BP1 and BP0 bits are set, the corresponding memory area is protected. Any
program or erase operation to that area will be inhibited.
Note: A Chip Erase (CER) instruction will be ignored unless all the Block Protection Bits are “0”s.
SRWD bit: The Status Register Write Disable (SRWD) bit operates in conjunction with the Write Protection (WP#)
signal to provide a Hardware Protection Mode. When the SRWD is set to “0”, the Status Register is not writeprotected. When the SRWD is set to “1” and the WP# is pulled low (VIL), the bits of Status Register (SRWD, BP3,
BP2, BP1, BP0) become read-only, and a WRSR instruction will be ignored. If the SRWD is set to “1” and WP# is
pulled high (VIH), the Status Register can be changed by a WRSR instruction.
QE bit: The Quad Enable (QE) is a non-volatile bit in the Status Register that allows quad operation. When the
QE bit is set to “0”, the pin WP# and HOLD# are enabled. When the QE bit is set to “1”, the IO2 and IO3 pins are
enabled.
WARNING: The QE bit must be set to 0 if WP# or HOLD# pin is tied directly to the power supply.
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IS25WQ040/020
Table 6.4 Block (64Kbyte) assignment by Block Write Protect (BP) Bits.
Status Register Bits
Protected Memory Area
BP3
BP2
BP1
BP0
4 Mbit
2 Mbit
0
0
0
0
None
None
0
0
0
1
1 block : 7
1 block : 3
0
0
1
0
2 blocks : 6 - 7
2 blocks : 2 - 3
0
0
1
1
4 blocks : 4 - 7
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
4 blocks 0 - 3
1
1
0
1
2 blocks : 0 - 1
2 blocks : 0 - 1
1
1
1
0
1 block : 0
1 block : 0
1
1
1
1
None
None
All Blocks
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IS25WQ040/020
6.2. FUNCTION REGISTER
Function Register Format and Bit definition are described in Table 6.5 and Table 6.6
Table 6.5 Function Register Format
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
PSUS
ESUS
Reserved
0
0
0
0
0
0
0
0
Table 6.6 Function Register Bit Definition
Read/Write
R
Reserved
R
Volatile
R
Volatile
R
Reserved
Reserved
R
Reserved
Reserved
Reserved
R
Reserved
Reserved
Reserved
R
Reserved
Reserved
Reserved
R
Reserved
Bit
Name
Definition
Bit 0
Reserved
Bit 1
ESUS
Bit 2
PSUS
Bit 3
Reserved
Reserved
Erase suspend bit:
"0" indicates Erase is not suspend
"1" indicates Erase is suspend
Program suspend bit:
“0” indicates program is not suspend
“1” indicates program is suspend
Reserved
Bit 4
Reserved
Bit 5
Bit 6
Bit 7
Type
ESUS bit: The Erase Suspend Status indicates when an Erase operation has been suspended. The ESUS bit is
‘1’ after a suspend command is issued during an Erase operation. Once the suspended Erase resumes, the ESUS
bit is reset to ‘0’.
PSUS bit: The Program Suspend Status bit indicates when a Program operation has been suspended. The PSUS
changes to ‘1’ after a suspend command is issued during the program operation. Once the suspended Program
resumes, the PSUS bit is reset to ‘0’.
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IS25WQ040/020
7. PROTECTION MODE
The IS25WQ040/020 supports hardware and software write-protection mechanisms.
7.1 HARDWARE WRITE PROTECTION
The Write Protection (WP#) pin provides a hardware write protection method for BP3, BP2, BP1, BP0, SRWD,
and QE in the Status Register. Refer to the section 6.1 STATUS REGISTER.
Write inhibit voltage (VWI) is specified in the section 9.8 POWER-UP AND POWER-DOWN. All write sequence will
be ignored when Vcc drops to VWI.
Table 7.1 Hardware Write Protection on Status Register
SRWD
WP#
Status Register
0
Low
Writable
1
Low
Protected
0
High
Writable
1
High
Writable
Note: Before the execution of any program, erase or Write Status Register instruction, the Write Enable Latch (WEL)
bit must be enabled by executing a Write Enable (WREN) instruction. If the WEL bit is not enabled, the program,
erase or write register instruction will be ignored.
7.2 SOFTWARE WRITE PROTECTION
The device also provides a software write protection feature. The Block Protection (BP3, BP2, BP1, and BP0) bits
allow part or the whole memory area to be write-protected.
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IS25WQ040/020
8. DEVICE OPERATION
The device utilizes an 8-bit instruction register. Refer to Table 8.1. Instruction Set for details on Instructions and
Instruction Codes. All instructions, addresses, and data are shifted in with the most significant bit (MSB) first on
Serial Data Input (SI). The input data on SI is latched on the rising edge of Serial Clock (SCK) after Chip Enable
(CE#) is driven low (VIL). Every instruction sequence starts with a one-byte instruction code and is followed by
address bytes, data bytes, or both address bytes and data bytes, depending on the type of instruction. CE# must
be driven high (VIH) after the last bit of the instruction sequence has been shifted in to end the operation.
Table 8.1 Instruction Set
Instruction Name
Hex Code
Operation
RD
03h
Read Data Bytes from Memory at Normal Read Mode
SPI
Maximum
Frequency
33MHz
FR
0Bh
Read Data Bytes from Memory at Fast Read Mode
SPI
104MHz
FRDIO
BBh
Fast Read Dual I/O
SPI
104MHz
FRDO
3Bh
Fast Read Dual Output
SPI
104MHz
FRQIO
EBh
Fast Read Quad I/O
SPI
104MHz
FRQO
6Bh
Fast Read Quad Output
SPI
104MHz
PP
02h
Page Program Data Bytes Into Memory
SPI
104MHz
PPQ
32h
Page Program Data Bytes Into Memory with Quad interface
SPI
104MHz
SER
D7h/20h
Sector Erase 4K
SPI
104MHz
BER32 (32Kbyte)
52h
Block Erase 32K
SPI
104MHz
BER64 (64Kbyte)
D8h
Block Erase 64K
SPI
104MHz
CER
C7h/60h
Chip Erase
SPI
104MHz
WREN
06h
Write Enable
SPI
104MHz
WRDI
04h
Write Disable
SPI
104MHz
RDSR
05h
Read Status Register
SPI
104MHz
WRSR
01h
Write Status Register
SPI
104MHz
RDFR
07h
Read Function Register
SPI
104MHz
PERSUS
75h/B0h
Suspend during the program/erase
SPI
104MHz
PERRSM
7Ah/30h
Resume program/erase
SPI
104MHz
DP
B9h
Deep power down mode
SPI
104MHz
RDID, RDPD
ABh
Read Manufacturer and Product ID/release Deep power down
SPI
104MHz
RDUID
A1h
Read Unique ID Number
SPI
104MHz
RDJDID
9Fh
Read Manufacturer and Product ID by JEDEC ID Command
SPI
104MHz
RDMDID
90h
Read Manufacturer and Device ID
SPI
80MHz
IRP
B1h
Program Information Row
SPI
104MHz
IRRD
4Bh
Read Information Row
SPI
33MHz
SECUNLOCK
26h
Sector Unlock
SPI
104MHz
SECLOCK
24h
Sector Lock
SPI
104MHz
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8.1 READ DATA OPERATION (RD, 03h)
The Read Data (RD) instruction is used to read memory contents of the device at a maximum frequency of 33MHz.
The RD instruction code is transmitted via the SI line, followed by three address bytes (A23 - A0) of the first memory
location to be read. A total of 24 address bits are shifted in, but only AVMSB (Valid Most Significant Bit) - A0 are decoded.
The remaining bits (A23 – AMSB) are ignored. The first byte address can be at any memory location. Upon completion,
any data on the SI will be ignored. Refer to Table 8.2 for the related Address Key.
The first byte data (D7 - D0) address is shifted out on the SO line, MSB first. A single byte of data, or up to the whole
memory array, can be read out in one READ instruction. The address is automatically incremented after each byte of
data is shifted out. The read operation can be terminated at any time by driving CE# high (VIH) after the data comes
out. When the highest address of the device is reached, the address counter will roll over to the 000000h address,
allowing the entire memory to be read in one continuous READ instruction.
If a Read Data instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not have any effects on the current cycle.
Table 8.2 Address Key
Valid Address
IS25WQ040
IS25WQ020
AVMSB–A0
A23-A0 (A23-A19=X)
A23-A0 (A23-A18=X)
Note: X=Don’t Care
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Figure 8.1 Read Data Sequence
CE #
Mode 3
0
1
2
3
4
5
7
6
8
9
10
...
28
29
30
31
SCK
Mode 0
3-byte Address
SI
Instruction = 03h
23
22
41
42
21
...
3
2
1
0
44
45
46
47
48
High Impedance
SO
CE #
32
33
34
35
36
37
39
38
40
43
SCK
SI
Data Out 1
SO
tV
7
6
5
4
3
Data Out 2
2
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0
7
6
5
4
3
2
1
0
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8.2 FAST READ DATA OPERATION (FR, 0Bh)
The FAST_READ instruction is used to read memory data at up to a 104MHZ clock.
The FAST_READ instruction code is followed by three address bytes (A23 - A0) and a dummy byte (8 clocks),
transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte from the
address is shifted out on the SO line, with each bit shifted out at a maximum frequency f CT, during the falling edge of
SCK.
The first byte addressed can be at any memory location. The address is automatically incremented after each byte
of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h address,
allowing the entire memory to be read with a single FAST_READ instruction. The FAST_READ instruction is
terminated by driving CE# high (VIH).
If a Fast Read Data instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction
is ignored and will not have any effects on the current cycle.
Figure 8.2 Fast Read Data Sequence
CE #
Mode 3
0
1
2
3
4
5
7
6
8
9
10
...
28
29
30
31
SCK
Mode 0
3-byte Address
SI
Instruction = 0Bh
23
22
41
42
21
...
3
2
1
0
44
45
46
47
48
High Impedance
SO
CE #
32
33
34
35
36
37
38
39
40
43
SCK
SI
Dummy Byte
Data Out
tV
SO
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6
5
4
3
2
1
0
...
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IS25WQ040/020
8.3 HOLD OPERATION
HOLD# is used in conjunction with CE# to select the device. When the device is selected and a serial sequence is
underway, HOLD# can be used to pause the serial communication with the master device without resetting the serial
sequence. To pause, HOLD# is brought low while the SCK signal is low. To resume serial communication, HOLD# is
brought high while the SCK signal is low (SCK may still toggle during HOLD). Inputs to SI will be ignored while SO is
in the high impedance state.
Timing graph can be referenced in AC Parameters Figure 9.3
8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBh)
The FRDIO instruction allows the address bits to be input two bits at a time. This may allow for code to be executed
directly from the SPI in some applications.
The FRDIO instruction code is followed by three address bytes (A23 – A0) and a mode byte, transmitted via the IO1
and IO0 lines, with each pair of bits latched-in during the rising edge of SCK. The address MSB is input on IO1, the
next bit on IO0, and continue to shift in alternating on the two lines. If AXh (X: don’t care) is input for the mode byte,
the device will enter AX read mode. In the AX read mode, the next instruction expected from the device will be another
FRDIO instruction and will not need the BBh instruction code so that it saves cycles as described in Figure 8.4. If the
following mode byte is not set to AXh, the device will exit AX read mode. To avoid any I/O contention problem, X
should be Hi-Z.
Once address and mode byte are input the device will read out data at the specified address. The first data byte
addressed is shifted out on the IO1 and IO0 lines, with each pair of bits shifted out at a maximum frequency f CT, during
the falling edge of SCK. The first bit (MSB) is output on IO1, while simultaneously the second bit is output on IO0.
Figure 8.3 illustrates the timing sequence.
The first byte addressed can be at any memory location. The address is automatically incremented by one after each
byte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h
address, allowing the entire memory to be read with a single FRDIO instruction. FRDIO instruction is terminated by
driving CE# high (VIH).
If the FRDIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not affect the current cycle.
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Figure 8.3 Fast Read Dual I/O Sequence (with command decode cycles)
CE #
Mode 3
0
1
2
3
4
5
7
6
8
9
10
...
18
19
20
21
SCK
Mode 0
Mode Bits
3-byte Address
IO0
Instruction = BBh
22
20
18
...
2
0
6
4
23
21
19
...
3
1
7
5
34
35
36
37
38
High Impedance
IO1
CE #
22
23
24
25
26
27
29
28
30
31
32
33
SCK
tV
IO0
2
0
6
4
2
0
6
Data Out 1
IO1
3
1
7
5
3
4
2
0
6
Data Out 2
1
7
5
3
4
2
0
...
...
...
1
...
...
...
Data Out 3
1
7
5
3
Notes:
1. If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). When the mode bits are
different from AXh (X: don’t care), the device exits the AX read operation.
2. To avoid I/O contention, X should be Hi-Z.
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Figure 8.4 Fast Read Dual I/O Sequence (without command decode cycles)
CE #
Mode 3
0
1
2
3
...
11
12
13
14
15
16
17
18
19
20
22
21
SCK
Mode 0
Mode Bits
3-byte Address
tV
Data Out 2
Data Out 1
IO0
22
20
18
...
2
0
6
4
2
0
6
4
2
0
6
4
...
IO1
23
21
19
...
3
1
7
5
3
1
7
5
3
1
7
5
...
Notes:
1. If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). When the mode bits are
different from AXh (X: don’t care), the device exits the AX read operation.
2. To avoid I/O contention, X should be Hi-Z.
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8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh)
The FRDO instruction is used to read memory data on two output pins each at up to a 104MHZ clock.
The FRDO instruction code is followed by three address bytes (A23 – A0) and a dummy byte (8 clocks), transmitted
via the IO0 line, with each bit latched-in during the rising edge of SCK. Then the first data byte addressed is shifted
out on the IO1 and IO0 lines, with each pair of bits shifted out at a maximum frequency fCT, during the falling edge of
SCK. The first bit (MSB) is output on IO1. Simultaneously the second bit is output on IO0.
The first byte addressed can be at any memory location. The address is automatically incremented by one after each
byte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h
address, allowing the entire memory to be read with a single FRDO instruction. FRDO instruction is terminated by
driving CE# high (VIH).
If a FRDO instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is
ignored and will not have any effects on the current cycle.
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IS25WQ040/020
Figure 8.5 Fast Read Dual-Output Sequence
CE #
Mode 3
0
1
2
3
4
5
7
6
8
9
10
11
28
29
30
31
SCK
Mode 0
3-byte Address
IO0
Instruction = 3Bh
23
22
21
...
3
2
1
0
44
45
46
47
48
High Impedance
IO1
CE #
32
33
34
35
36
37
38
39
40
41
42
43
SCK
tV
IO0
6
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2
0
6
Data Out 1
8 Dummy Cycles
IO1
4
7
5
3
4
2
0
...
1
...
Data Out 2
1
7
5
3
25
IS25WQ040/020
8.6 FAST READ QUAD OUTPUT (FRQO, 6Bh)
The FRQO instruction is used to read memory data on four output pins each at up to a 104 MHz clock.
The FRQO instruction code is followed by three address bytes (A23 – A0) and a dummy byte (8 clocks),
transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte addressed
is shifted out on the IO3, IO2, IO1 and IO0 lines, with each group of four bits shifted out at a maximum frequency
fCT, during the falling edge of SCK. The first bit (MSB) is output on IO3, while simultaneously the second bit is
output on IO2, the third bit is output on IO1, etc.
The first byte addressed can be at any memory location. The address is automatically incremented after each byte
of data is shifted out. W hen the highest address is reached, the address counter will roll over to the 000000h
address, allowing the entire memory to be read with a single FRQO instruction. FRQO instruction is terminated by
driving CE# high (VIH).
If a FRQO instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is
ignored and will not have any effects on the current cycle.
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IS25WQ040/020
Figure 8.6 Fast Read Quad-Output Sequence
CE #
Mode 3
0
1
2
3
4
5
7
6
8
9
10
11
28
29
30
31
SCK
Mode 0
3-byte Address
IO0
Instruction = 6Bh
23
22
21
...
3
2
1
0
44
45
46
47
48
High Impedance
IO1
High Impedance
IO2
High Impedance
IO3
CE #
32
33
34
35
36
37
38
39
40
41
42
43
SCK
tV
IO0
4
8 Dummy Cycles
0
4
0
4
0
4
0
...
Data Out 1 Data Out 2 Data Out 3 Data Out 4
IO1
5
1
5
1
5
1
5
1
...
IO2
6
2
6
2
6
2
6
2
...
IO3
7
3
7
3
7
3
7
3
...
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8.7 FAST READ QUAD I/O OPERATION (FRQIO, EBh)
The FRQIO instruction allows the address bits to be input four bits at a time. This may allow for code to be
executed directly from the SPI in some applications.
The FRQIO instruction code is followed by three address bytes (A23 – A0), a mode byte, and 4 dummy cycles,
transmitted via the IO3, IO2, IO0 and IO1 lines, with each group of four bits latched-in during the rising edge of
SCK. The address of MSB inputs on IO3, the next bit on IO2, the next bit on IO1, the next bit on IO0, and continue
to shift in alternating on the four. The mode byte contains the value AXh, where X is a “don’t care” value. After
four dummy clocks, the first data byte addressed is shifted out on the IO3, IO2, IO1 and IO0 lines, with each group
of four bits shifted out at a maximum frequency f CT, during the falling edge of SCK. The first bit (MSB) is output on
IO3, while simultaneously the second bit is output on IO2, the third bit is output on IO1, etc. Figure 8.7.1 illustrates
the timing sequence.
If the mode byte is AXh, the AX read mode is enabled. In the mode, the device expects that the next operation
will be another FRQIO and subsequent FRQIO execution skips command code. It saves command cycles as
described in Figure 8.7.2. The device will remain in this mode until the mode byte is different from AXh.
The first byte addressed can be at any memory location. The address is automatically incremented after each
byte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h
address, allowing the entire memory to be read with a single FRQIO instruction. FRQIO instruction is terminated
by driving CE# high (VIH).
If a FRQIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not have any effects on the current cycle.
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Figure 8.7.1 Fast Read Quad I/O Sequence (with command decode cycles)
CE #
Mode 3
0
1
2
3
4
5
7
6
8
9
10
11
12
13
14
15
SCK
Mode 0
3-byte Address
IO0
Mode Bits
20
16
12
8
4
0
4
0
21
17
13
9
5
1
5
1
IO2
22
18
14
10
6
2
6
2
IO3
23
19
15
11
7
3
7
3
28
29
30
31
32
Instruction = EBh
High Impedance
IO1
CE #
16
17
18
19
20
21
23
22
24
25
26
27
SCK
4 Dummy Cycles
tV Data Out 1 Data Out 2 Data Out 3 Data Out 4 Data Out 5 Data Out 6
IO0
4
0
4
0
4
0
4
0
4
0
4
0
...
IO1
5
1
5
1
5
1
5
1
5
1
5
1
...
6
2
6
2
6
2
6
2
6
2
6
2
...
7
3
7
3
7
3
7
3
7
3
7
3
...
IO2
IO3
Note: If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). Anything but AXh
in the mode byte cycle will exit the AX read mode.
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IS25WQ040/020
Figure 8.7.2 Fast Read Quad I/O AX Sequence (without command decode cycles)
CE #
Mode 3 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
...
SCK
Mode 0
6 Dummy Cycles
3-byte Address
tV
Data Out 1 Data Out 2
IO0
20
16
12
8
4
0
4
0
4
0
4
0
...
IO1
21
17
13
9
5
1
5
1
5
1
5
1
...
IO2
22
18
14
10
6
2
6
2
6
2
6
2
...
IO3
23
19
15
11
7
3
7
3
7
3
7
3
...
Mode Bits
Note: If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). Anything but AXh
in the mode byte cycle will exit the AX read mode.
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8.8 PAGE PROGRAM OPERATION (PP, 02h)
The Page Program (PP) instruction allows up to 256 bytes data to be programmed into memory in a single
operation. The destination of the memory to be programmed must be outside the protected memory area set by
the Block Protection (BP3, BP2, BP1, BP0) bits. A PP instruction which attempts to program into a page that is
write-protected will be ignored. Before the execution of PP instruction, the Write Enable Latch (WEL) must be
enabled through a Write Enable (WREN) instruction.
The PP instruction code, three address bytes and program data (1 to 256 bytes) are input via the SI line. Program
operation will start immediately after the CE# is brought high, otherwise the PP instruction will not be executed.
The internal control logic automatically handles the programming voltages and timing. During a program operation,
all instructions will be ignored except the RDSR instruction. The progress or completion of the program operation
can be determined by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the
program operation is still in progress. If WIP bit is “0”, the program operation has completed.
If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the
previously latched data are discarded, and the last 256 bytes are kept to be programmed into the page. The
starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap around
to the beginning of the same page. If the data to be programmed are less than a full page, the data of all other
bytes on the same page will remain unchanged.
Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s.
A byte cannot be reprogrammed without first erasing the whole sector or block.
Figure 8.8 Page Program Sequence
1
...
7
8
9
31
...
32
33
...
39
...
...
2087
0
2086
Mode 3
2079
CE #
SCK
Mode 0
SI
SO
3-byte Address
Instruction = 02h
23
22
...
Data In 1
0
7
6
...
Data In 256
0
...
7
...
0
High Impedance
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8.9 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h)
The Quad Input Page Program instruction allows up to 256 bytes data to be programmed into memory in a single
operation with four pins (IO0, IO1, IO2 and IO3). The destination of the memory to be programmed must be
outside the protected memory area set by the Block Protection (BP3, BP2, BP1, BP0) bits. A Quad Input Page
Program instruction which attempts to program into a page that is write-protected will be ignored. Before the
execution of Quad Input Page Program instruction, the QE bit in the Status Register must be set to “1” and the
Write Enable Latch (WEL) must be enabled through a Write Enable (WREN) instruction.
The Quad Input Page Program instruction code, three address bytes and program data (1 to 256 bytes) are input
via the four pins (IO0, IO1, IO2 and IO3). Program operation will start immediately after the CE# is brought high,
otherwise the Quad Input Page Program instruction will not be executed. The internal control logic automatically
handles the programming voltages and timing. During a program operation, all instructions will be ignored except
the RDSR instruction. The progress or completion of the program operation can be determined by reading the
WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the program operation is still in progress. If
WIP bit is “0”, the program operation has completed.
If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the
previously latched data are discarded, and the last 256 bytes data are kept to be programmed into the page. The
starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap around
to the beginning of the same page. If the data to be programmed are less than a full page, the data of all other
bytes on the same page will remain unchanged.
Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s.
A byte cannot be reprogrammed without first erasing the whole sector or block.
Figure 8.9 Quad Input Page Program operation
CE #
Mode 3
0
1
2
3
4
5
6
7
8
9
...
31
32
33
34
35
SCK
Mode 0
3-byte Address
Data In 1
Data In 2
4
0
4
0
...
5
1
5
1
...
IO2
6
2
6
2
...
IO3
7
3
7
3
...
IO0
IO1
Instruction = 32h
High Impedance
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22
...
0
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8.10 ERASE OPERATION
The memory array of the device is organized into uniform 4 Kbyte sectors or 32K/64 Kbyte uniform blocks (a block
consists of sixteen adjacent sectors).
Before a byte is reprogrammed, the sector or block that contains the byte must be erased (erasing sets bits to
“1”). In order to erase the device, there are three erase instructions available: Sector Erase (SER), Block Erase
(BER) and Chip Erase (CER). A sector erase operation allows any individual sector to be erased without affecting
the data in other sectors. A block erase operation erases any individual block. A chip erase operation erases the
whole memory array of a device. A sector erase, block erase or chip erase operation can be executed prior to any
programming operation.
8.11 SECTOR ERASE OPERATION (SER, D7h/20h)
A Sector Erase (SER) instruction erases a 4 Kbyte sector before the execution of a SER instruction, the Write
Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is reset automatically after
the completion of sector an erase operation.
A SER instruction is entered, after CE# is pulled low to select the device and stays low during the entire instruction
sequence The SER instruction code, and three address bytes are input via SI. Erase operation will start
immediately after CE# is pulled high. The internal control logic automatically handles the erase voltage and timing.
During an erase operation, all instruction will be ignored except the Read Status Register (RDSR) instruction. The
progress or completion of the erase operation can be determined by reading the WIP bit in the Status Register
using a RDSR instruction. If the WIP bit is “1”, the erase operation is still in progress. If the WIP bit is “0”, the erase
operation has been completed.
Figure 8.10 Sector Erase Sequence
CE #
Mode 3
0
1
2
3
4
5
6
7
8
9
10
...
28
29
30
31
1
0
SCK
Mode 0
3-byte Address
SI
SO
Instruction = D7h/20h
23
22
21
...
3
2
High Impedance
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8.12 BLOCK ERASE OPERATION (BER32K:52h, BER64K:D8h)
A Block Erase (BER) instruction erases a 32/64 Kbyte block of the device. Before the execution of a BER
instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset
automatically after the completion of a block erase operation.
The BER instruction code and three address bytes are input via SI. Erase operation will start immediately after
the CE# is pulled high, otherwise the BER instruction will not be executed. The internal control logic automatically
handles the erase voltage and timing.
Figure 8.11 Block Erase (64k) Sequence
CE #
Mode 3
0
1
2
3
4
5
6
7
8
9
10
...
28
29
30
31
SCK
Mode 0
3-byte Address
SI
Instruction = D8h
23
22
21
...
3
2
1
0
8
9
10
...
28
29
30
31
1
0
High Impedance
SO
Figure 8.12 Block Erase (32K) Sequence
CE #
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
SI
SO
3-byte Address
Instruction = 52h
23
22
21
...
3
2
High Impedance
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8.13 CHIP ERASE OPERATION (CER, C7h/60h)
A Chip Erase (CER) instruction erases the entire memory array of the device. Before the execution of CER
instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset
automatically after completion of a chip erase operation.
The CER instruction code is input via the SI. Erase operation will start immediately after CE# is pulled high,
otherwise the CER instruction will not be executed. The internal control logic automatically handles the erase
voltage and timing.
Figure 8.13 Chip Erase Sequence
CE#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
SI
SO
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8.14 WRITE ENABLE OPERATION (WREN, 06h)
The Write Enable (WREN) instruction is used to set the Write Enable Latch (WEL) bit. The WEL is reset to the
write-protected state after power-up. The WEL bit must be write enabled before any write operation, including
Sector Erase, Block Erase, Chip Erase, Page Program, Write Status Register, and Write Function Register
operations. The WEL bit will be reset to the write-protected state automatically upon completion of a write
operation. The WREN instruction is required before any above operation is executed.
Figure 8.14 Write Enable Sequence
CE#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Address
Instruction = 06h
SIO
High Impedance
SO
8.15 WRITE DISABLE OPERATION (WRDI, 04h)
The Write Disable (WRDI) instruction resets the WEL bit and disables all write instructions. The WRDI instruction
is not required after the execution of a write instruction, since the WEL bit is automatically reset.
Figure 8.15 Write Disable Sequence
CE#
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
SIO
SO
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High Impedance
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8.16 READ STATUS REGISTER OPERATION (RDSR, 05h)
The Read Status Register (RDSR) instruction provides access to the Status Register. During the execution of a
program, erase or Write Status Register operation, all other instructions will be ignored except the RDSR
instruction, which can be used to check the progress or completion of an operation by reading the WIP bit of
Status Register.
Figure 8.16 Read Status Register Sequence
CE #
Mode 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Mode 0
SI
Instruction = 05h
tV
Data Out
SO
7
6
5
2
3
4
1
0
8.17 WRITE STATUS REGISTER OPERATION (WRSR, 01h)
The Write Status Register (WRSR) instruction allows the user to enable or disable the block protection and Status
Register write protection features by writing “0”s or “1”s into the non-volatile BP3, BP2, BP1, BP0, and SRWD
bits. WRSR instruction also allows the user to enable or disable the quad operation by setting QE bit to 0 (disable)
or 1 (enable).
Figure 8.17 Write Status Register Sequence
CE #
Mode 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2
1
0
SCK
Mode 0
Data In
SI
SO
Instruction = 01h
7
6
5
4
3
High Impedence
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8.18 READ FUNCTION REGISTER OPERATION (RDFR, 07h)
The Read Function Register (RDFR) instruction provides access to the Erase/Program suspend register. During
the execution of a program, erase or write Status Register suspend, which can be used to check the suspend
status.
Figure 8.18 Read Function Register Sequence
CE #
Mode 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Mode 0
SI
Instruction = 07h
tV
SO
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7
6
5
4
3
2
1
0
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8.19 PROGRAM/ERASE SUSPEND & RESUME
The device allows the interruption of Sector-Erase, Block-Erase or Page-Program operations to conduct other
operations. 75h/B0h command for suspend and 7Ah/30h for resume will be used. Function Register bit1 (ESUS)
and bit2 (PSUS) are used to check whether or not the device is in suspend mode.
Suspend to read ready timing: 20µs
Resume to another suspend timing: 1.0ms
Note: It needs 500ns delay time from write command to suspend command
PROGRAM/ERASE SUSPEND DURING SECTOR-ERASE OR BLOCK-Erase (PERSUS 75h/B0h)
The Program/Erase Suspend allows the interruption of Sector Erase and Block Erase operations. After the
Program/Erase Suspend, WEL bit will be disabled, therefore only read related, resume and reset commands can
be accepted. Refer to Table 8.3 for more detail.
To execute the Program/Erase Suspend operation, the host drives CE# low, sends the Program/Erase Suspend
command cycle (75h/B0h), then drives CE# high. The Function Register indicates that the erase has been
suspended by changing the ESUS bit from ‘0’ to ‘1’, but the device will not accept another command until it is
ready. To determine when the device will accept a new command, poll the WIP bit in the Status Register or wait
tSUS. When ESUS bit is issued, the Write Enable Latch (WEL) bit will be reset.
PROGRAM/ERASE SUSPEND DURING PAGE PROGRAMMING (PERSUS 75h/B0h)
The Program/Erase Suspend allows the interruption of all program operations. After the Program/Erase Suspend
command, WEL bit will be disabled, therefore only read related, resume and reset commands can be accepted.
Refer to Table 8.3 for more detail.
To execute the Program/Erase Suspend operation, the host drives CE# low, sends the Program/Erase Suspend
command cycle (75h/B0h), then drives CE# high. The Function Register indicates that the programming has been
suspended by changing the PSUS bit from ‘0’ to ‘1’, but the device will not accept another command until it is
ready. To determine when the device will accept a new command, poll the WIP bit in the Status Register or wait
tSUS.
PROGRAM/ERASE RESUME (PERRSM 7A/30h)
The Program/Erase Resume restarts a Program or Erase command that was suspended, and changes the
suspend status bit in the Function Register (ESUS or PSUS bits) back to ‘0’. To execute the Program/Erase
Resume operation, the host drives CE# low, sends the Program/Erase Resume command cycle (7Ah/30h), then
drives CE# high. A cycle is two nibbles long, most significant nibble first. To determine if the internal, self-timed
Write operation completed, poll the WIP bit in the Status Register, or wait the specified time t SE, tBE or tPP for Sector
Erase, Block Erase, or Page Programming, respectively. The total write time before suspend and after resume
will not exceed the uninterrupted write times tSE, tBE or tPP.
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Table 8.3 Instructions accepted during Suspend
Operation
Suspended
Instruction Allowed
Name
Hex Code
Operation
Program or Erase
RD
03h
Read Data Bytes from Memory at Normal Read Mode
Program or Erase
FR
0Bh
Read Data Bytes from Memory at Fast Read Mode
Program or Erase
FRDIO
BBh
Fast Read Dual I/O
Program or Erase
FRDO
3Bh
Fast Read Dual Output
Program or Erase
FRQIO
EBh
Fast Read Quad I/O
Program or Erase
FRQO
6Bh
Fast Read Quad Output
Program or Erase
RDSR
05h
Read Status Register
Program or Erase
RDFR
07h
Read Function Register
Program or Erase
PERRSM
7Ah/30h
Resume program/erase
Program or Erase
RDID
ABh
Read Manufacturer and Product ID
Program or Erase
RDUID
A1h
Read Unique ID Number
Program or Erase
RDJDID
9Fh
Read Manufacturer and Product ID by JEDEC ID Command
Program or Erase
RDMDID
90h
Read Manufacturer and Device ID
Program or Erase
IRRD
4Bh
Read Information Row
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8.20 DEEP POWER DOWN (DP, B9h)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (enter
into Power-Down mode), the standby current is reduced from ISB1 to ISB2. During the Power-down mode, the device
is not active and all Write/Program/Erase instructions are ignored. The instruction is initiated by driving the CE#
pin low and shifting the instruction code “B9h” as show in the figure 8.20. The CE# pin must be driven high after
the instruction has been latched. If this is not done the Power-Down will not be executed. After CE# pin driven
high, the power-down state will be entered within the time duration of tDP. While in the power-down state only the
Release from Power-down / RDID instruction, which restores the device to normal operation, will be recognized.
All other instructions are ignored. This includes the Read Status Register instruction, which is always available
during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition for
securing maximum write protection. It can support in SPI and Multi-I/O mode.
Figure 8.20 Enter Deep Power Down Mode Operation (SPI)
tDP
CE #
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
SI
Instruction = B9h
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8.21 RELEASE DEEP POWER DOWN (RDPD, ABh)
The Release from Power-down / Read Device ID instruction is a multi-purpose instruction. To release the device
from the power-down state mode, the instruction is issued by driving the CE# pin low, shifting the instruction code
“ABh” and driving CE# high as shown in Figure 8.21.
Release from power-down will take the time duration of tRES1 before the device will resume normal operation and
other instructions are accepted. The CE# pin must remain high during the tRES1 time duration. If the Release from
Power-down / RDID instruction is issued while an Erase, Program or Write cycle is in process (when WIP equals
1) the instruction is ignored and will not have any effects on the current cycle.
Figure 8.21 Release Power Down Sequence (SPI)
tRES1
CE #
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
SI
Instruction = ABh
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8.22 READ PRODUCT IDENTIFICATION (RDID, ABh)
The Release from Power-down /read Device ID instruction is a multi-purpose instruction. It can support both SPI
and Multi-I/O mode. The Read Product Identification (RDID) instruction is for reading out the old style of 8-bit
Electronic Signature, whose values are shown as Table 8.4 Product Identification.
The RDID instruction code is followed by three dummy bytes, each bit being latched-in on SI during the rising
SCK edge. Then the Device ID1 is shifted out on SO with the MSB first, each bit been shifted out during the falling
edge of SCK. The RDID instruction is ended by CE# going high. The Device ID1 outputs repeatedly if additional
clock cycles are continuously sent on SCK while CE# is at low.
Table 8.4 Product Identification
Instruction
ABh, 90h, 9Fh
ID1
9Dh
ID2
7Fh
Manufacturer ID
Device Density
Device ID1
Device ID2
4Mb
12h
53h
2Mb
11h
52h
Figure 8.22 Read Product Identification Sequence
CE #
Mode 3 0
1
...
7
8
9
...
31
32
33
...
39
SCK
Mode 0
SI
Instruction = ABh
3 Dummy Bytes
tV
SO
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Device ID1
(ID7-ID0)
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8.23 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9Fh)
The JEDEC ID READ instruction allows the user to read the manufacturer and product ID of devices. Refer to
Table 8.4 Product Identification for Manufacturer ID and Device ID. After the JEDEC ID READ command (9Fh) is
input, the Manufacturer ID1 is shifted out on SO with the MSB first, followed by the Device ID1 and Device ID2,
each bit is shifted out during the falling edge of SCK. If CE# stays low after the last bit of the Device ID2 is shifted
out, the Manufacturer ID1, Device ID1, and Device ID2 will loop until CE# is pulled high.
Figure 8.23 Read Product Identification by JEDEC ID Read Sequence
CE #
Mode 3
0
1
...
7
8
9
...
15
16
17
...
23
24
25
...
31
SCK
Mode 0
SI
Instruction = 9Fh
Data Out
tV
SO
Manufacturer ID1
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Device ID1
Device ID2
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8.24 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90h)
The Read Device Manufacturer and Device ID (RDMDID) instruction allows the user to read the manufacturer and
product ID of the devices. Refer to Table 8.4 Product Identification for manufacturer ID and device ID. The
RDMDID instruction code is followed by two dummy bytes and one byte address (A7~A0), each bit being latchedin on SI during the rising edge of SCK. If one byte address is initially set to A0 = 0, then the Manufacturer ID1 is
shifted out on SO with the MSB first, then the Device ID1 and Manufacturer ID2, with each bit being shifted out
during the falling edge of SCK. If one byte address is initially set to A0 = 1, then device ID1 will be read first,
followed Manufacturer ID1 and Manufacturer ID2. The Manufacturer and Device IDs can be read continuously
alternating between the three until CE# is driven high.
Figure 8.24 Read Product Identification by RDMDID Read Sequence
CE #
Mode 3
0
1
...
7
8
9
...
31
32
...
39
40
...
47
48
...
55
...
SCK
Mode 0
SI
Instruction = 90h
3 Byte Address
(A0=0)
Data Out
tV
SO
Manufacturer
ID1
Device ID1
Manufacturer
ID2
Notes:
1. ADDRESS A0 = 0, will output the Manufacturer ID1 Device ID1 Manufacturer ID2
ADDRESS A0 = 1, will output the Device ID1 Manufacturer ID1 Manufacturer ID2
2. The Manufacture and Device IDs can be read continuously and will alternate from one to the other until CE# pin is
pulled high.
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8.25 READ UNIQUE ID NUMBER (RDUID, A1h)
The Read Unique ID Number (RDUID) instruction accesses a factory-set read-only 16-byte number that is unique
to the device. The ID number can be used in conjunction with user software methods to help prevent copying or
cloning of a system. The RDUID instruction is instated by driving the CE# pin low and shifting the instruction code
(A1h) followed by 3 address bytes and a dummy byte. After which, the 16-byte ID is shifted out on the falling edge
of SCK as shown below.
Note: 16-byte of data will repeat as long as CE# is low and SCK is toggling.
Figure 8.25 RDUID Operation
CE #
Mode 3
0
1
...
7
8
9
...
31
32
33
...
39
40
41
...
47
SCK
Mode 0
SI
Instruction = A1h
3 Byte Address
Dummy Byte
tV
SO
Data Out
A[23:16]
A[15:9]
A[8:4]
A[3:0]
XXh
XXh
00h
0h Byte address
XXh
XXh
00h
1h Byte address
XXh
XXh
00h
2h Byte address
XXh
XXh
00h
…
Table 8.5 Unique ID Addressing
XXh
XXh
00h
Fh Byte address
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8.26 SECURITY INFORMATION ROW (OTP MEMORY)
The Security Information Row is comprised of an additional 256 bytes of programmable information. The security
bits can be reprogrammed by the user. Any program security instruction issued while program cycle is in progress
is rejected without having any effect on the cycle that is in progress.
Table 8.6 Information Row Address
Address Assignment
OTP memory array
OTP control byte (lock bit = bit 0)
A[23:16]
00h
00h
A[15:8]
00h
00h
A[7:0]
Byte address (0h ~ FEh)
FFh
To lock the Security Information Row (OTP memory), the Bit 0 of the OTP control byte (byte 256) is used to
permanently lock the OTP memory array.
- When the bit 0 of byte 256 = ’1’, the 256 bytes of the OTP memory array can be programmed.
- When the bit 0 of byte 256 = ‘0’, the 256 bytes of the OTP memory array are read-only and cannot be
programmed anymore.
Once a bit of the OTP memory has been programmed to ‘0’, it can no longer be set to ‘1’. Therefore, as soon
as bit 0 of byte 256 (control byte) is set to ‘0’, the 256 bytes of the OTP memory array become read-only in a
permanent way.
BIT
Bit1~ Bit7: Don’t care
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8.27 INFORMATION ROW PROGRAM OPERATION (IRP, B1h)
The Information Row Program (IRP) instruction allows up to 256 bytes data to be programmed into the Security
Information Row in a single operation. Before the execution of IRP instruction, the Write Enable Latch (WEL) must
be enabled through a Write Enable (WREN) instruction.
The IRP instruction code, three address bytes and program data (1 to 256 bytes) should be sequentially input via
the SI line. Three address bytes has to be input as specified in the Table 8.6 Information Row Address. Program
operation will start once the CE# goes high, otherwise the IRP instruction will not be executed. The internal control
logic automatically handles the programming voltages and timing. During a program operation, all instructions will
be ignored except the RDSR instruction. The progress or completion of the program operation can be determined
by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the program operation is still
in progress. If WIP bit is “0”, the program operation has completed.
At least one program data should be input. The starting byte can be anywhere within the 256 addresses. The data
to be programmed is not allowed to exceed the last address. If the number of the data to be programmed are less
than the one between starting address and the last address, the data of all remaining addresses will be
unchanged.
After CE# pin is driven HIGH, the self-timed page program cycle (whose duration is tPOTP) is initiated. While the
program cycle is in progress, the status register may be read to check the value of the write in progress (WIP)
bit. The write in progress (WIP) bit is “1” during the self-timed program cycle, and it is “0” when the program
cycle is completed. At some unspecified time before the cycle is complete, the write enable latch (WEL) bit will
be reset.
If an IRP instruction is issued while an erase, program or write cycle is in progress the instruction is ignored
without having any effect on the cycle that is in progress
Note: Information Row is only one time programmable (OTP). Once Information Row is programmed, the data
cannot be altered.
Figure 8.28 IRP (Information Row Program) Operation
1
...
7
8
9
31
...
32
33
...
39
...
...
2087
0
2086
Mode 3
2079
CE #
SCK
Mode 0
SI
SO
3-byte Address
Instruction = B1h
23
22
...
Data In 1
0
7
6
...
Data In n
0
...
7
...
0
High Impedance
Note:
1. The “n” must not exceed the last address. (1 ≤ n ≤ 256)
2. The lock bit of Security Information Row is in the address of 0000FFh.
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8.28 INFORMATION ROW READ OPERATION (IRRD, 4Bh)
The IRRD instruction is used to read Security Information Row at up to a 33MHZ clock.
The IRRD instruction code is followed by three address bytes (A23 - A0), transmitted via the SI line, and with each
bit latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out on the SO line, with
each bit shifted out at a maximum frequency fCT, during the falling edge of SCK.
The address is automatically incremented after each byte of data is shifted out. When the last address is reached,
the address counter will not wrap around to the 000000h address since there is no rollover mechanism in the
IRRD instruction. This means that the IRRD instruction must be sent with a maximum of 256 bytes to read and
the data of the last address keeps being read on the SO pin once the last address is reached. The IRRD instruction
is terminated by driving CE# high (VIH).
If an IRRD instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not have any effects on the current cycle
Figure 8.29 IRRD (Information Row Read) Operation
CE #
Mode 3
0
1
...
7
8
9
...
31
32
33
...
39
40
41
...
47
SCK
Mode 0
SI
Instruction = 4Bh
3 Byte Address
tV
SO
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Data Out ...
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8.29 SECTOR LOCK/UNLOCK FUNCTIONS
SECTOR UNLOCK OPERATION (SECUNLOCK, 26h)
The Sector Unlock command allows the user to select a specific sector to allow program and erase operations.
This instruction is effective when the blocks are designated as write-protected through the BP0, BP1, BP2, and
BP3 bits in the Status Register. Only one sector can be enabled at any time. If many SECUNLOCK commands
are input, only the last sector designated by the last SECUNLOCK command will be unlocked. The instruction
code is followed by a 24-bit address specifying the target sector, but A0 through A11 are not decoded. The
remaining sectors within the same block remain as read-only.
Figure 8.59 Sector Unlock Sequence
CE #
Mode 3
0
1
2
3
4
5
6
7
8
9
10
...
28
29
30
31
1
0
SCK
Mode 0
3-byte Address
SI
SO
Instruction = 26h
23
22
21
...
3
2
High Impedance
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SECTOR LOCK OPERATION (SECLOCK, 24h)
The Sector Lock command relocks a sector that was previously unlocked by the Sector Unlock command. The
instruction code does not require an address to be specified, as only one sector can be enabled at a time. The
remaining sectors within the same block remain in read-only mode.
Figure 8.60 Sector Lock Sequence
CE #
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
SI
SO
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High Impedance
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9. ELECTRICAL CHARACTERISTICS
9.1 ABSOLUTE MAXIMUM RATINGS (1)
Storage Temperature
-65°C to +150°C
Surface Mount Lead Soldering Temperature
Standard Package
240°C 3 Seconds
Lead-free Package
260°C 3 Seconds
Input Voltage with Respect to Ground on All Pins
-0.5V to Vcc + 0.5V
All Output Voltage with Respect to Ground
-0.5V to Vcc + 0.5V
VCC
Electrostatic Discharge Voltage (Human Body
-0.5V to + 4.0V
Model)(2)
-2000V to +2000V
Notes:
1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. ANSI/ESDA/JEDEC JS-001
9.2 OPERATING RANGE
Part Number
IS25WQ040/020
Operating Temperature (Extended Grade E)
-40°C to 105°C
Vcc Power Supply
1.65V (VMIN) – 1.95V (VMAX); 1.8V (Typ)
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9.3 DC CHARACTERISTICS
(Under operating range)
Symbol
ICC1
ICC2
ICC3
ICC4
Typ(2)
Max
NORD at 33MHz,
8
13
FRD Single at 80MHz
10
15
FRD Dual at 80MHz
10
20
FRD Quad at 80MHz
12
24
FRD Single at 104MHz
11
16
FRD Dual at 104MHz
11
21
FRD Quad at 104MHz
13
25
Parameter
VCC Active Read current
Condition
(3)
Min
CE# = VCC
17
105°C
22
20(4)
85°C
VCC WRSR Current
CE# = VCC
17
105°C
22
CE# = VCC
mA
(4)
85°C
VCC Erase Current (4K/32K/64K)
mA
20(4)
85°C
VCC Program Current
Units
20
17
105°C
22
20(4)
85°C
ICC5
VCC Erase Current (CE)
CE# = VCC
ISB1
VCC Standby Current CMOS
CE# = VCC,
CE#, RESET#(4) = VCC
ISB2
Deep power down current
CE# = VCC,
CE#, RESET#(4) = VCC
ILI
Input Leakage Current
VIN = 0V to VCC
±1
µA
ILO
Output Leakage Current
VIN = 0V to VCC
±1
µA
-0.5
0.3VCC
V
0.7VCC
VCC + 0.3
V
0.2
V
(1)
Input Low Voltage
VIH(1)
Input High Voltage
VOL
Output Low Voltage
IOL = 100 µA
VOH
Output High Voltage
IOH = -100 µA
VIL
17
105°C
22
30(4)
85°C
15
105°C
µA
50
6(4)
85°C
2
105°C
µA
10
VCC - 0.2
V
Notes:
1. Maximum DC voltage on input or I/O pins is VCC + 0.5V. During voltage transitions, input or I/O pins may overshoot
VCC by + 2.0V for a period of time not to exceed 20ns. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, input or I/O pins may undershoot GND by -2.0V for a period of time not to exceed 20ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at
VCC = VCC (Typ), TA=25°C.
3. Outputs are unconnected during reading data so that output switching current is not included.
4. These parameters are characterized and not 100% tested.
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9.4 AC MEASUREMENT CONDITIONS
Symbol
Parameter
Min
Max
Units
CL
Load Capacitance up to 104Mhz
30
pF
TR,TF
Input Rise and Fall Times
5
ns
VIN
Input Pulse Voltages
0.2VCC to 0.8VCC
V
VREFI
Input Timing Reference Voltages
0.3VCC to 0.7VCC
V
VREFO
Output Timing Reference Voltage
0.5VCC
V
Figure9.1 Output test load & AC measurement I/O Waveform
0.8VCC
Input
AC
Measurement
Level
VCC/2
1.8k
0.2VCC
OUTPUT PIN
1.2k
30pf
9.5 PIN CAPACITANCE (TA = 25°C, VCC=1.8V, 1MHZ)
Symbol
CIN
CIN/OUT
Parameter
Input Capacitance
(CE#, SCK)
Input/Output Capacitance
(other pins)
Test Condition
Min
Typ
Max
Units
VIN = 0V
-
-
6
pF
VIN/OUT = 0V
-
-
8
pF
Notes:
1. These parameters are characterized and are not 100% tested.
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9.6 AC CHARACTERISTICS
(Under operating range, refer to section 9.4 for AC measurement conditions)
Parameter
fCT
Clock Frequency for fast read mode
fC
Clock Frequency for read mode
tRI(1)
Input Rise Time
0.1
V/ns
Input Fall Time
0.1
V/ns
tCKH
SCK High Time
4
ns
tCKL
SCK Low Time
4
ns
tCEH
CE# High Time
25
ns
tCS
CE# Setup Time
10
ns
tCH
CE# Hold Time
5
ns
tDS
Data In Setup Time
2
ns
tDH
Data in Hold Time
2
ns
tV
Output Valid
tOH
Output Hold Time Normal Mode
0
ns
tHLCH
HOLD Active Setup Time relative to SCK
15
ns
tCHHH
HOLD Active Hold Time relative to SCK
15
ns
tHHCH
HOLD Not Active Setup Time relative to SCK
15
ns
tCHHL
HOLD Not Active Hold Time relative to SCK
15
tDIS(1)
Output Disable Time
100
ns
(1)
HOLD to Output Low Z
200
ns
(1)
HOLD to Output High Z
tFI
(1)
tLZ
tHZ
tEC
Units
0
104
MHz
0
33
MHz
8
ns
200
ns
300
ms
Block Erase Time (32Kbyte)
120
500
ms
Block Erase time (64Kbyte)
250
1000
ms
2Mb
0.75
1.5
4Mb
1.5
3.0
0.5
1
Vcc Set-up Time
(1)
ns
120
Page Program Time
tVCS
tRES1
Max
Sector Erase Time (4Kbyte)
Chip Erase Time
tPP
Min
Typ(2)
Symbol
50
s
ms
us
Release deep power down
5
µs
tDP(1)
Deep power down
10
µs
tW
Write Status Register time
50
ms
tSUS(1)
Suspend to read ready
20
µs
trs(1)
Resume to another suspend
1
ms
tPOTP
Program OTP Time
1
ms
5
0.5
Notes:
1. These parameters are characterized and not 100% tested.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at
VCC = VCC (Typ), TA=25°C.
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9.7 SERIAL INPUT/OUTPUT TIMING (1)
Figure 9.2 SERIAL INPUT/OUTPUT TIMING
tCEH
CE#
VIH
VIL
tCS
SCK
tCH
VIH
tCKH
VIL
tDS
SI
VIH
tCKL
tDH
VALID IN
VIL
tV
SO
VOH
tOH
HI-Z
tDIS
HI-Z
VOL
Note1. For SPI Mode 0 (0,0)
Figure 9.3 HOLD TIMING
CE#
tHLCH
tCHHL
tHHCH
SCK
tCHHH
tHZ
tLZ
SO
SI
HOLD#
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9.8 POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must be NOT SELECTED until Vcc reaches at the right level. (Adding
a simple pull-up resistor on CE# is recommended.)
Power up timing
VCC
VCC(max)
All Write Commands are Rejected
Chip Selection Not Allowed
VCC(min)
Reset State
tVCE
V(write inhibit)
Read Access Allowed
Device fully
accessible
tPUW
Symbol
Parameter
Min.
tVCE(1)
Vcc(min) to CE# Low
10
tPUW (1)
Power-up time delay to write instruction
1
VWI
(1)
Write Inhibit Voltage
Max
Unit
µs
10
ms
1.4
V
Note1. These parameters are characterized and are not 100% tested.
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9.9 PROGRAM/ERASE PERFORMANCE
Typ
Max
Unit
Sector Erase Time (4KB)
Parameter
120
300
ms
Block Erase Time (32KB)
120
500
ms
Block Erase Time (64KB)
250
1000
ms
2Mb
0.75
1.5
4Mb
1.5
3
Page Programming Time
0.5
1
ms
Byte Program (First byte)
8
25
µs
2.5
12
µs
Chip Erase Time
Additional Byte Program (After first byte)
Remarks
From writing erase command to erase
completion
s
From writing program command to program
completion
Note: These parameters are characterized and are not 100% tested.
9.10 RELIABILITY CHARACTERISTICS1
Parameter
Min
Max
Unit
Test Method
Endurance
100,000
-
Cycles
JEDEC Standard A117
Data Retention
20
-
Years
JEDEC Standard A117
Latch-Up
-100
+100
mA
JEDEC Standard 78
Notes:
1. These parameters are characterized and are not 100% tested.
2. 100,000 Continuous Chip and Block cycling, 100,000 Continuous Sector cycling
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10. PACKAGE TYPE INFORMATION
10.1 8-PIN JEDEC 150MIL BROAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) PACKAGE (JN)
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10.2 8-PIN 150MIL VVSOP PACKAGE (JV)
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10.3 8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD (WSON) 6X5MM PACKAGE (JK)
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10.4 8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD (USON) PACKAGE 2X3MM (JU)
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10.5 8-PIN JEDEC 208MIL BROAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) PACKAGE (JB)
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11. ORDERING INFORMATION - Valid Part Numbers
IS25WQ 040
-
JN
L
E
TEMPERATURE RANGE
E = Extended (-40°C to +105°C)
PACKAGING CONTENT
L = RoHS compliant
PACKAGE Type (1)
JN = 8-pin SOIC 150mil
JB = 8-pin SOIC 208mil
JV = 8-pin VVSOP 150mil (Call Factory)
JK = 8-contact WSON 6x5mm
JU = 8-contact USON 2x3mm
JW = KGD (Call Factory)
Die Revision
Blank = A Revision
Density
040 = 4 Mbit
020 = 2 Mbit
BASE PART NUMBER
IS = Integrated Silicon Solution Inc.
25WQ = FLASH, 1.65V ~ 1.95V, Quad SPI
Note:
1. Call Factory for other package options available
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IS25WQ040/020
Density
4Mb
2Mb
Frequency (MHz)
104
104
Order Part Number
Package
IS25WQ040-JNLE
8-pin SOIC 150mil
IS25WQ040-JBLE
8-pin SOIC 208mil (Call Factory)
IS25WQ040-JVLE
8-pin VVSOP 150mil (Call Factory)
IS25WQ040-JKLE
8-contact WSON 6x5mm
IS25WQ040-JULE
8-contact USON 2x3mm
IS25WQ040-JWLE
KGD (Call Factory)
IS25WQ020-JNLE
8-pin SOIC 150mil (Call Factory)
IS25WQ020-JBLE
8-pin SOIC 208mil
IS25WQ020-JVLE
8-pin VVSOP 150mil (Call Factory)
IS25WQ020-JKLE
8-contact WSON 6x5mm (Call Factory)
IS25WQ020-JULE
8-contact USON 2x3mm
IS25WQ020-JWLE
KGD (Call Factory)
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