IS25WQ080-JBLE

IS25WQ080 8 Mbit bit Single Operating Voltage Serial Flash Memory With 104 MHz Dual- or Quad-Output SPI Bus Interface FEATURES • Single Power Supply Operation - Low voltage range: 1.65 V – 1.95 V • Memory Organization - IS25WQ080: 1024K x 8 (8 Mbit) • Cost Effective Sector/Block Architecture - 8Mb : Uniform 4KByte sectors / Sixteen uniform 64KByte blocks • Serial Peripheral Interface (SPI) Compatible - Supports single-, dual- or quad-output - Supports SPI Modes 0 and 3 - Maximum 33 MHz clock rate for normal read - Maximum 104 MHz clock rate for fast read - Maximum 208MHz clock rate equivalent Dual SPI - Maximum 416MHz clock rate equivalent Quad SPI • Byte Program Operation - Typical 8 us/Byte • Page Program (up to 256 Bytes) Operation - Maximum 0.7 ms per page program • Sector, Block or Chip Erase Operation - Sector Erase (4KB)150 ms (Max) - Block Erase (32K/64KB)0.5S (Max) - Chip Erase 6s (8Mb) (Max) •Deep power-down mode 1uA (Typ) PRELIMINARY DATASHEET • Low Power Consumption - Max 15 mA active read current - Max 20 mA program/erase current - Max 50uA standby current • Hardware Write Protection - Protect and unprotect the device from write operation by Write Protect (WP#) Pin • Software Write Protection - The Block Protect (BP3, BP2, BP1, BP0) bits allow partial or entire memory to be configured as read-only • High Product Endurance - Guaranteed 100,000 program/erase cycles per single sector - Minimum 20 years data retention • Industrial Standard Pin-out and Package - 8-pin SOIC 208mil - 8-pin SOIC 150mil - 8-pin VVSOP 150mil - 8-pin WSON (5x6mm) - Lead-free (Pb-free) package Additional 256-byte Security information onetime programmable (OTP) area GENERAL DESCRIPTION The IS25WQ080 are 8Mbit Serial Peripheral Interface (SPI) Flash memories, providing single-, dual or quadoutput. The devices are designed to support a 33 MHz fclock rate in normal read mode, and 104 MHz in fast read, the fastest in the industry. The devices use a single low voltage power supply, ranging from 1.65 Volt to 1.95 Volt, to perform read, erase and program operations. The devices can be programmed in standard EPROM programmers. The IS25WQ080 are accessed through a 4-wire SPI Interface consisting of Serial Data Input (Sl), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. The devices support page program mode, where 1 to 256 bytes data can be programmed into the memory in one program operation. These devices are divided into uniform 4 Kbyte sectors or uniform 64 Kbyte blocks. The IS25WQ080 are manufactured on pFLASH™’s advanced non-volatile technology. Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 1 IS25WQ080 CONNECTION DIAGRAMS CE# 1 8 SO (IO1) 2 7 Vcc HOLD# (IO3) WP# (IO2) 3 6 SCK GND 4 5 SI (IO0) 8-Pin SOIC/VVSOP Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 CE# 1 8 Vcc SO (IO1) 2 7 HOLD# (IO3) WP# (IO2) 3 6 SCK GND 4 5 SI (IO0) 8-pin WSON 2 IS25WQ080 PIN DESCRIPTIONS SYMBOL TYPE DESCRIPTION CE# INPUT SCK SI (IO0) SO (IO1) GND Vcc WP# (IO2) INPUT INPUT/OUTPUT INPUT/OUTPUT HOLD# (IO3) INPUT/OUTPUT Chip Enable: CE# low activates the devices internal circuitries for device operation. CE# high deselects the devices and switches into standby mode to reduce the power consumption. When a device is not selected, data will not be accepted via the serial input pin (Sl), and the serial output pin (SO) will remain in a high impedance state. Serial Data Clock Serial Data Input/Output Serial Data Input/Output Ground Device Power Supply Write Protect/Serial Data Output: A hardware program/erase protection for all or part of a memory array. When the WP# pin is low, memory array write-protection depends on the setting of BP3, BP2, BP1 and BP0 bits in the Status Register. When the WP# is high, the status register are not write-protected. When the QE bit of is set “1”, the /WP pin (Hardware Write Protect) function is not available since this pin is used for IO2 Hold: Pause serial communication by the master device without resetting the serial sequence. When the QE bit of Status Register-2 is set for “1”, the function is Serial Data Input & Output (for 4xI/O read mode) INPUT/OUTPUT Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 3 IS25WQ080 BLOCK DIAGRAM WP# (IO2) SI (IO0) SO (IO1) HOLD# (IO3) Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 4 IS25WQ080 SPI MODES DESCRIPTION Multiple IS25WQ080 devices can be connected on the SPI serial bus and controlled by a SPI Master, i.e. microcontroller, as shown in Figure 1. The devices support either of two SPI modes: Mode 0 (0, 0) Mode 3 (1, 1) The difference between these two modes is the clock polarity when the SPI master is in Stand-by mode: the serial clock remains at “0” (SCK = 0) for Mode 0 and the clock remains at “1” (SCK = 1) for Mode 3. Please refer to Figure 2. For both modes, the input data is latched on the rising edge of Serial Clock (SCK), and the output data is available from the falling edge of SCK. Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices) SDI SPI Interface with (0,0) or (1,1) SDI SCK SCK SPI Master (i.e. Microcontroller) CS3 CS2 SO SI SCK SPI Memory Device CS1 CE# WP# SO SI SCK CE# WP# CE# HOLD# SI SPI Memory Device SPI Memory Device HOLD# SO WP# HOLD# Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as appropriate. Figure 2. SPI Modes Supported SCK Mode 0 (0,0) SCK Mode 3 (1,1) SI MSb Input mode SO Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 MSb 5 IS25WQ080 SYSTEM CONFIGURATION The IS25WQ080 devices are designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of the Motorola MC68HCxx series of microcontrollers or any SPI interface-equipped system controllers. The devices have the superset features that can be enabled through specific software instructions: Configurable sector size: The memory array of IS25WQ080 is divided into uniform 4 Kbyte sectors or uniform 32K/64 Kbyte blocks (a block consists of sixteen adjacent sectors). The below Table 1 illustrates the memory map of the devices. BLOCK/SECTOR ADDRESSES Table 1. Block/Sector Addresses of IS25WQ080 Memory Density Block No.(64KB) Block No.(32KB) Block 0 Block 0 8 Mbit Block 1 Block 2 Block 1 Block 3 16 Mbit : Block 7 Block 8 : : Block 15 Block 16 : : Block 31 : : : : : Block30 Block31 Block32 Block33 : : Block62 Block63 Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 Sector No. Sector 0 : : Sector 15 Sector 16 : : Sector 31 : : Sector 128 : : : Sector 255 Sector 256 : : : : Sector511 Sector Size (Kbytes) 4 : : 4 4 : : 4 : : 4 : : : 4 4 : : : 4 Address Range 000000h – 000FFFh 001000h – 001FFFh : 00F000h – 00FFFFh 010000h – 010FFFh 011000h – 011FFFh : 01F000h – 01FFFFh : 070000h – 07FFFFh 080000h – 08FFFFh : : 0F0000h – 0FFFFFh 100000h – 10FFFFh : : 1F0000h – 1FFFFFh 6 IS25WQ080 REGISTERS (CONTINUED) STATUS REGISTER Refer to Tables 2 and 5 for Status Register Format and BP3, BP2, BP1, BP0 bits: The Block Protection (BP3, Status Register Bit Definitions. BP2, BP1 and BP0) bits are used to define the portion The BP0, BP1, BP2, BP3 and SRWD are non-volatile of the memory area to be protected. Refer to Tables 6 memory cells that can be written by a Write Status and 7 for the Block Write Protection bit settings. When Register (WRSR) instruction. The default value of the a defined combination of BP3, BP2, BP1 and BP0 bits BP2, BP1, BP0, and SRWD bits were set to “0” at are set, the corresponding memory area is protected. factory. The Status Register can be read by the Read Any program or erase operation to that area will be Status Register (RDSR). Refer to Table 10 for inhibited.Note: a Chip Erase (CHIP_ER) instruction is Instruction Set. executed only if all the Block Protection Bits are set as “0”s. The function of Status Register bits are described as follows: SRWD bit: The Status Register Write Disable (SRWD) WIP bit: The Write In Progress (WIP) bit is read-only, bits operates in conjunction with the Write Protection and can be used to detect the progress or completion (WP#) signal to provide a Hardware Protection Mode. of a program or erase operation. When the WIP bit is When the SRWD is set to “0”, the Status Register is “0”, the device is ready for a write status register, not write-protected. When the SRWD is set to “1” and program or erase operation. When the WIP bit is “1”, the WP# is pulled low (VIL), the bits of Status Register the device is busy. (SRWD, BP3, BP2, BP1, BP0) become read-only, and a WRSR instruction will be ignored. If the SRWD is set WEL bit: The Write Enable Latch (WEL) bit indicates to “1” and WP# is pulled high (VIH), the Status Register the status of the internal write enable latch. When the can be changed by a WRSR instruction. WEL is “0”, the write enable latch is disabled, and all QE bit: The Quad Enable (QE) is a non-volatile bit in write operations, including write status register, write configuration register, page program, sector erase, the status register that allows Quad operation. When block and chip erase operations are inhibited. When the QE bit is set to “0”,the pin WP# and HOLD# are the WEL bit is “1”, write operations are allowed. The enable. When the QE bit is set to “1”, the pin IO2 and WEL bit is set by a Write Enable (WREN) instruction. IO3 are enable. Each write register, program and erase instruction must be preceded by a WREN instruction. The WEL bit WARNING: The QE bit should never be set to a 1 can be reset by a Write Disable (WRDI) instruction. It during standard SPI or Dual SPI operation if the will automatically be the reset after the completion of a WP# or HOLD# pins are tied directly to the power write instruction. supply or ground. Table 2. Status Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 SRWD QE BP3 BP2 BP1 BP0 WEL Default (flash bit) 0 0 0 0 0 0 0  The default value of the BP3, BP2, BP1, BP0, and SRWD bits were set to “0” at factory. Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 Bit 0 WIP 0 7 IS25WQ080 REGISTERS (CONTINUED) bit is ‘1’ after the host issues a suspend command during an Erase operation. Once the suspended Erase resumes, the ESUS bit is reset to ‘0.’ Function REGISTER The Function Register can be read by the Read Function Register (RFR). Refer to Table 9 for Instruction Set. PSUS bit: The Program Suspend Status bit indicates when a Program operation has been suspended. The PSUS is ‘1’ after the host issues a suspend command during the Program operation. Once the suspended Program resumes, the PSUS bit is reset to ‘0.’ The function of Function Register bits are described as follows: ESUS bit: The Erase Suspend Status indicates when an Erase operation has been suspended. The ESUS Table 3. Function Register Format Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X 0 X 0 X 0 X 0 X 0 PSUS 0 ESUS 0 X 0 Table 4. Function register bit definition Bit Name Bit 1 ESUS Bit 2 PSUS Definition Erase suspend bit: “0” indicates Erase is not suspend “1” indicates Erase is suspend Program suspend bit: “0” indicates program is not suspend “1” indicates program is suspend Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 Read/Write Non-Volatile bit R No R No 8 IS25WQ080 REGISTERS (CONTINUED) Table 5. Status Register Bit Definition Bit Name Definition Bit 0 WIP Bit 1 WEL Bit 2 Bit 3 Bit 4 Bit 5 BP0 BP1 BP2 BP3 Bit 6 QE Bit 7 SRWD Write In Progress Bit: “0” indicates the device is ready “1” indicates a write cycle is in progress and the device is busy Write Enable Latch: “0” indicates the device is not write enabled (default) “1” indicates the device is write enabled Block Protection Bit: (See Tables 6 and 7 for details) “0” indicates the specific blocks are not write-protected (default) “1” indicates the specific blocks are write-protected Quad Enable bit: “0” indicates the Quad output function disable (default) “1” indicates the Quad output function enable Status Register Write Disable: (See Table 10 for details) “0” indicates the Status Register is not write-protected (default) “1” indicates the Status Register is write-protected Read/Write Non-Volatile bit R No R/W No R/W Yes R/W Yes R/W Yes Table 7. Block Write Protect Bits for IS25WQ080 Status Register Bits Protected Memory Area BP3 BP2 BP1 BP0 8 Mbit 0 0 0 0 None 0 0 0 1 th Upper sixteenth (1 block : 15 ): th th 0 0 1 0 0 0 1 1 Upper quarter (4 blocks :12 to 15 ): 0 1 0 0 Upper half (8 blocks :8 to 15 ): 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 Upper eighth (2 blocks :14 and 15 ): th th th th All blocks (16blocks : 0 to 15): 000000h – 0FFFFFh th th (8blocks :0 to 7 ): th (4 blocks :0 to 3th): th (2blocks :0 to 1th): th (1 blocks :0 ): None 9 IS25WQ080 REGISTERS (CONTINUED) PROTECTION MODE The IS25WQ080 have two types of write-protection mechanisms: hardware and software. These are used to prevent irrelevant operation in a possibly noisy environment and protect the data integrity. HARDWARE WRITE-PROTECTION The devices provide two hardware write-protection features: a. When inputting a program, erase or write status register instruction, the number of clock pulse is checked to determine whether it is a multiple of eight before the executing. Any incomplete instruction command sequence will be ignored. b. Write inhibit is 1.3V, all write sequence will be ignored when Vcc drop to 1.3V and lower. c. The Write Protection (WP#) pin provides a hardware write protection method for BP3, BP2, BP1, BP0 and SRWD in the Status Register. Refer to the STATUS REGISTER description. SOFTWARE WRITE PROTECTION The IS25WQ080 also provides two software write protection features: a. Before the execution of any program, erase or write status register instruction, the Write Enable Latch (WEL) bit must be enabled by executing a Write Enable (WREN) instruction. If the WEL bit is not enabled first, the program, erase or write register instruction will be ignored. b. The Block Protection (BP3, BP2, BP1, BP0) bits allow part or the whole memory area to be writeprotected. Table 8. Hardware Write Protection on Status Register SRWD WP# Status Register 0 Low Writable 1 0 1 Low High High Protected Writable Writable DEVICE OPERATION The IS25WQ080 utilize an 8-bit instruction register. Refer to Table 9 Instruction Set for details of the Instructions and Instruction Codes. All instructions, addresses, and data are shifted in with the most significant bit (MSB) first on Serial Data Input (SI). The input data on SI is latched on the rising edge of Serial Clock (SCK) after Chip Enable (CE#) is driven low (VIL). Every instruction sequence starts with a one-byte Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 instruction code and is followed by address bytes, data bytes, or both address bytes and data bytes, depending on the type of instruction. CE# must be driven high (VIH) after the last bit of the instruction sequence has been shifted in. The timing for each instruction is illustrated in the following operational descriptions. 10 IS25WQ080 Table 9. Instruction Set Instruction Name Hex Code Operation Comman d Cycle Maximum Frequency RDID Abh 4 Bytes 104 MHz JEDEC ID READ RDMDID WREN WRDI RDSR WRSR READ FAST_READ FRDO FRDIO FRQO FRQIO MR PAGE_ PROG 9Fh 90h 06h 04h 05h 01h 03h 0Bh 3Bh BBh 6Bh Ebh FFh 02h Read Manufacturer and Product ID/ release deep power down mode Read Manufacturer and Product ID by JEDEC ID Command Read Manufacturer and Device ID Write Enable Write Disable Read Status Register Write Status Register Read Data Bytes from Memory at Normal Read Mode Read Data Bytes from Memory at Fast Read Mode Fast Read Dual Output Fast Read Dual I/O Fast Read Quad Output Fast Read Quad I/O Mode Reset Page Program Data Bytes Into Memory 104 MHz 104 MHz 104 MHz 104 MHz 104 MHz 104 MHz 33 MHz 104 MHz 104 MHz 104MHz 104 MHz 104MHz 104MHz 104 MHz SECTOR_ER D7h/ 20h 52h D8h C7h/ 60h A2h 32h Sector Erase 1 Byte 4 Bytes 1 Byte 1 Byte 1 Byte 2 Bytes 4 Bytes 5 Bytes 5 Bytes 3 Bytes 5 Bytes 2 Bytes 2 Byte 4 Bytes + 256B 4 Bytes Block Erase Block Erase Chip Erase 4 Bytes 4 Bytes 1 Byte 104 MHz 104 MHz 104 MHz BLOCK_ER (32KB) BLOCK_ER (64KB) CHIP_ER Dual page program Quad page program Page Program Data Bytes Into Memory with Dual interface Page Program Data Bytes Into Memory with Quad interface 4 Bytes + 256B 104 MHz 104MHz 104MHz Power down Program information Raw Read information Raw B9h B1h Program 256 bytes of Security area 4 Bytes 104MHz 104 MHz 4Bh Read 256 bytes of Security area 4 Bytes 33 MHz Program/Erase Suspend Program/Erase Resume RDFR 75h/ B0h 7Ah/ 30h 07h Suspend during the program/erase 1 byte 104MHz Resume program/erase 1 byte 104MHz Read function register 1 byte 104MHz HOLD OPERATION HOLD# is used in conjunction with CE# to select the IS25WQ080. When the devices are selected and a serial sequence is underway, HOLD# can be used to pause the serial communication with the master device without resetting the serial sequence. Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 To pause, HOLD# is brought low while the SCK signal is low. To resume serial communication, HOLD# is brought high while the SCK signal is low (SCK may still toggle during HOLD). Inputs to Sl will be ignored while SO is in the high impedance state. 11 IS25WQ080 DEVICE OPERATION (CONTINUED) RDID COMMAND (READ PRODUCT IDENTIFICATION)/ Release Power-down OPERATION The Release from Power-down or High performance Mode / Device ID instruction is a multi-purpose instruction. The Read Product Identification (RDID) instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table 10 of ID Definitions. This is not same as RDID or JEDEC ID instruction. It’s not recommended to use for new design. For new design, please use RDID or JEDEC ID instruction. The RDES instruction code is followed by three dummy bytes, each bit being latched-in on SI during the rising edge of SCK. Then the Device ID is shifted out on SO with the MSB first, each bit been shifted out during the falling edge of SCK. The RDES instruction is ended by CE# goes high. The Device ID outputs repeatedly if continuously send the additional clock cycles on SCK while CE# is at low. To release the device from the power-down state Mode, the instruction is issued by driving the CE# pin low, shifting the instruction code “Abh” and driving CE# high as shown in figure 3. Release from power-down will take the time duration of tRES1 before the device will resume normal operation and other instructions are accepted. The CE# pin must remain high during the tRES1 time duration. If the Release from Power-down / RDID instruction is issued while an Erase, Program or Write cycle is in process (when WIP equals 1) the instruction is ignored and will not have any effects on the current cycle Table 10. Product Identification Product Identification Manufacturer ID Device ID: IS25WQ080 Data First Byte Second Byte Device ID1 13h 9Dh 7Fh Device ID2 54h Figure 3. Read Product Identification Sequence CE# 0 1 7 8 9 38 31 46 39 47 54 SCK INSTRUCTION SI SO 3 Dummy Bytes 1010 1011b HIGH IMPEDANCE Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 Device ID1 Device ID1 Device ID1 12 IS25WQ080 DEVICE OPERATION (CONTINUED) JEDEC ID READ COMMAND (READ PRODUCT IDENTIFICATION BY JEDEC ID) OPERATION The JEDEC ID READ instruction allows the user to read the manufacturer and product ID of devices. Refer to Table 10 Product Identification for pFlash Manufacturer ID and Device ID. After the JEDEC ID READ command is input, the second Manufacturer ID (7Fh) is shifted out on SO with the MSB first, followed by the first Manufacturer ID (9Dh) and the Device ID2 (54h, in the case of the IS25WQ080), each bit shifted out during the falling edge of SCK. If CE# stays low after the last bit of the Device ID is shifted out, the Manufacturer ID and Device ID will loop until CE# is pulled high. Figure 4. Read Product Identification by JEDEC ID READ Sequence CE# 0 15 16 7 8 23 24 31 SCK INSTRUCTION SI SO 1001 1111b HIGH IMPEDANCE Manufacture ID2 Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 Manufacture ID1 Device ID2 13 IS25WQ080 DEVICE OPERATION (CONTINUED) RDMDID COMMAND (READ DEVICE MANUFACTURER AND DEVICE ID) OPERATION The Read Product Identification (RDID) instruction allows the user to read the manufacturer and product ID of the devices. Refer to Table 10 Product Identification for pFLASH™ manufacturer ID and device ID. The RDID instruction code is followed by two dummy bytes and one byte address (A7~A0), each bit being latched-in on SI during the rising edge of SCK. If one byte address is initially set to A0 = 0, then the first manufacturer ID (9Dh) is shifted out on SO with the MSB first, the device ID1 and the second manufacturer ID (7Fh), each bit been shifted out during the falling edge of SCK. If one byte address is initially set to A0 = 1, then device ID1 will be read first, then followed by the first manufacture ID (9Dh) and then second manufacture ID (7Fh). The manufacture and device ID can be read continuously, alternating from one to the others. The instruction is completed by driving CE# high. Figure 5. Read Product Identification by RDMDID READ Sequence CE# 0 1 2 3 4 5 6 9 8 7 10 11 SCK 28 29 30 31 1 A0 ... 3 - BYTE ADDRESS SIO INSTRUCTION = 1001 0000b 23 22 2 ... 3 21 HIGH IMPEDANCE SO CE# 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK SIO Data Out1 SO 7 6 5 4 3 Data Out2 2 1 Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 0 7 6 5 4 3 2 1 0 14 IS25WQ080 CE# 47 48 49 50 51 52 53 54 55 4 3 2 1 0 56 SCK SIO Data Out3 SO 7 6 5 Note : st nd 1. ADDRESS A0 = 0, will output the 1 manufacture ID (9Dh) first -> device ID1 -> 2 manufacture ID (7Fh) st nd ADDRESS A0 = 1, will output the device ID1 -> 1 manufacture ID (9D) -> 2 manufacture ID (7Fh) Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 15 IS25WQ080 DEVICE OPERATION (CONTINUED) WRITE ENABLE OPERATION The Write Enable (WREN) instruction is used to set the Write Enable Latch (WEL) bit. The WEL bit of the IS25WQ080 is reset to the write –protected state after power-up. The WEL bit must be write enabled before any write operation, including sector, block erase, chip erase, page program and write status register. The WEL bit will be reset to the write-protect state automatically upon completion of a write operation. The WREN instruction is required before any above operation is executed. Figure 6. Write Enable Sequence WRDI COMMAND (WRITE DISABLE) OPERATION The Write Disable (WRDI) instruction resets the WEL bit and disables all write instructions. The WRDI instruction is not required after the execution of a write instruction, since the WEL bit is automatically reset. Figure 7. Write Disable Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 16 IS25WQ080 DEVICE OPERATION (CONTINUED) RDSR COMMAND (READ STATUS REGISTER) OPERATION The Read Status Register (RDSR) instruction provides access to the Status Register. During the execution of a program, erase or write status register operation, all other instructions will be ignored except the RDSR instruction, which can be used to check the progress or completion of an operation by reading the WIP bit of Status Register. Figure 8. Read Status Register Sequence WRSR COMMAND (WRITE STATUS REGISTER) OPERATION The Write Status Register (WRSR) instruction allows the user to enable or disable the block protection and status register write protection features by writing “0”s or “1”s into the non-volatile BP3, BP2, BP1, BP0 and SRWD bits. Figure 9. Write Status Register Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 17 IS25WQ080 DEVICE OPERATION (CONTINUED) READ COMMAND (READ DATA) OPERATION The Read Data (READ) instruction is used to read memory data of a IS25WQ080 under normal mode running up to 33 MHz. The READ instruction code is transmitted via the Sl line, followed by three address bytes (A23 – A0) of the first memory location to be read. A total of 24 address bits are shifted in, but only AMS (most significant address) – A0 are decoded. The remaining bits (A23 – AMS) are ignored. The first byte addressed can be at any memory location. Upon completion, any data on the Sl will be ignored. Refer to Table 11 for the related Address Key. out on the SO line, MSb first. A single byte of data, or up to the whole memory array, can be read out in one READ instruction. The address is automatically incremented after each byte of data is shifted out. The read operation can be terminated at any time by driving CE# high (VIH) after the data comes out. When the highest address of the devices is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read in one continuous READ instruction. If a Read Data instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is ignored and will not have any effects on the current cycle The first byte data (D7 – D0) addressed is then shifted Table 11. Address Key Address IS25WQ080 AN (AMS – A0) A19 – A0 Don’t Care Bits A23 – A20 Figure 10. Read Data Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 18 IS25WQ080 DEVICE OPERATION (CONTINUED) FAST_READ COMMAND (FAST READ DATA) OPERATION The FAST_READ instruction is used to read memory data at up to a 104 MHz clock. The first byte addressed can be at any memory location. The address is automatically incremented after each byte of data is shifted out. When the highest The FAST_READ instruction code is followed by three address is reached, the address counter will roll over to address bytes (A23 – A0) and a dummy byte (8 the 000000h address, allowing the entire memory to be clocks), transmitted via the SI line, with each bit read with a single FAST_READ instruction. The latched-in during the rising edge of SCK. Then the first FAST_READ instruction is terminated by driving CE# data byte addressed is shifted out on the SO line, with high (VIH). If a Fast Read Data instruction is issued while each bit shifted out at a maximum frequency f CT, during an Erase, Program or Write cycle is in process (WIP=1) the instruction is ignored and will not have any effects on the falling edge of SCK. the current cycle Figure 11. Fast Read Data Sequence SIO Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 19 IS25WQ080 DEVICE OPERATION (CONTINUED) FRDO COMMAND (FAST READ DUAL OUTPUT) OPERATION The FRDO instruction is used to read memory data on two output pins each at up to a 104 MHz clock. The first byte addressed can be at any memory location. The address is automatically incremented after each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single FRDO instruction. FRDO instruction is terminated by driving CE# high (VIH). If a FRDO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is ignored and will not have any effects on the current cycle The FRDO instruction code is followed by three address bytes (A23 – A0) and a dummy byte (8 clocks), transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out on the SO and SIO lines, with each pair of bits shifted out at a maximum frequency fCT, during the falling edge of SCK. The first bit (MSb) is output on SO, while simultaneously the second bit is output on SIO. Figure 12. Fast Read Dual-Output Sequence CE# 0 2 1 3 4 5 6 7 8 9 10 11 SCK 30 31 2 1 0 46 47 48 2 0 6 1 7 28 29 ... 3 - BYTE ADDRESS SI INSTRUCTION = 0011 1011b 23 22 21 42 43 ... 3 HIGH IMPEDANCE SO CE# 32 33 34 35 36 37 38 39 40 41 44 45 SCK IO switch from input to output IO0 HIGH IMPEDANCE 6 4 2 0 6 DATA OUT 1 IO1 HIGH IMPEDANCE 7 5 3 4 DATA OUT 2 1 7 5 3 8 dummy clocks Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 20 IS25WQ080 DEVICE OPERATION (CONTINUED) FRDIO COMMAND (FAST READ DUAL I/O) OPERATION The FRDIO instruction is similar to the FRDO instruction, but allows the address bits to be input two bits at a time. This may allow for code to be executed directly from the SPI in some applications. The first byte addressed can be at any memory location. The address is automatically incremented after each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single FRDIO instruction. FRDIO instruction is terminated by driving CE# high (VIH). The FRDIO instruction code is followed by three address bytes (A23 – A0) and a mode byte, transmitted via the IO0 and IO1 lines, with each pair of bits latched-in during the rising edge of SCK. The address MSb is input on IO1, the next bit on IO0, and continues to shift in alternating on the two lines. The mode byte contains the value Ax, where x is a “don’t care” value. Then the first data byte addressed is shifted out on the IO1 and IO0 lines, with each pair of bits shifted out at a maximum frequency fCT, during the falling edge of SCK. The MSb is output on IO1, while simultaneously the second bit is output on IO0. Figure 13 illustrates the timing sequence. The device expects the next operation will be another FRDIO. It remains in this mode until it receives a Mode Reset (FFh) command. In subsequent FRDIO execution, the command code is not input, saving timing cycles as described in Figure 14. If a FRDIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is ignored and will not have any effects on the current cycle Figure 13. Fast Read Dual I/O Sequence (with command decode cycles) CE# 0 2 1 3 4 5 6 8 7 9 10 SCK 11 18 19 20 21 ... 3 - BYTE ADDRESS IO0 INSTRUCTION = 1011 1011b 21 19 ... 2 0 6 23 22 20 ... 3 1 7 22 IO1 MODE BITS 4 5 CE# 22 23 24 25 26 27 28 29 30 31 SCK IO switch from input to output IO0 6 4 2 0 6 DATA OUT 1 IO1 7 5 3 4 2 0 6 1 7 DATA OUT 2 1 7 Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 5 3 21 IS25WQ080 DEVICE OPERATION (CONTINUED) Figure 14. Fast Read Dual I/O Sequence (without command decode cycles) CE# 0 1 2 SCK 11 3 13 14 15 16 17 19 20 21 22 23 24 22 21 19 ... 2 IO switch from input to output MODE BITS 0 6 6 4 23 22 20 ... 3 1 7 5 4 2 0 6 DATA OUT 1 2 dummy clocks IO1 18 … 3 - BYTE ADDRESS IO0 12 7 5 3 4 2 0 DATA OUT 2 1 7 5 3 1 FRQO COMMAND (FAST READ QUAD OUTPUT) OPERATION The FRQO instruction is used to read memory data on four output pins each at up to a 104 MHz clock. simultaneously the second bit is output on IO2, the third bit is output on IO1, etc. The FRQO instruction code is followed by three address bytes (A23 – A0) and a dummy byte (8 clocks), transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out on the IO3, IO2, IO1 and IO0 lines, with each group of four bits shifted out at a maximum frequency fCT, during the falling edge of SCK. The first bit (MSb) is output on IO3, while The first byte addressed can be at any memory location. The address is automatically incremented after each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single FRQO instruction. FRQO instruction is terminated by driving CE# high (VIH). If a FRQO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is ignored and will not have any effects on the current cycle Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 22 IS25WQ080 DEVICE OPERATION (CONTINUED) Figure 15. Fast Read Quad-Output Sequence CE# r 0 1 2 3 4 5 6 9 8 7 10 11 SCK 28 29 30 31 1 0 ... 3 - BYTE ADDRESS SI INSTRUCTION = 0110 1011b 23 ... 3 22 21 2 HIGH IMPEDANCE SO CE# 32 33 34 35 36 37 38 40 39 41 43 42 44 45 46 47 SCK 8 dummy clocks IO0 HIGH IMPEDANCE IO1 HIGH IMPEDANCE IO switch from input to output DATA OUT 1 DATA OUT 2 HIGH IMPEDANCE IO3 Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 DATA OUT n 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 HIGH IMPEDANCE IO2 ... 23 IS25WQ080 DEVICE OPERATION (CONTINUED) FRQIO COMMAND (FAST READ QUAD I/O) OPERATION The FRQIO instruction is similar to the FRQO instruction, but allows the address bits to be input four bits at a time. This may allow for code to be executed directly from the SPI in some applications. third bit is output on IO1, etc. Figure 16 illustrates the timing sequence. The first byte addressed can be at any memory location. The address is automatically incremented The FRQIO instruction code is followed by three after each byte of data is shifted out. When the highest address bytes (A23 – A0) and a mode byte, address is reached, the address counter will roll over to transmitted via the IO3, IO2, IO0 and IO1 lines, with the 000000h address, allowing the entire memory to be each group of four bits latched-in during the rising edge read with a single FRQIO instruction. FRQIO of SCK. The address MSb is input on IO3, the next bit instruction is terminated by driving CE# high (VIH). on IO2, the next bit on IO1, the next bit on IO0, and continue to shift in alternating on the four. The mode The device expects the next operation will be another byte contains the value Ax, where x is a “don’t care” FRQIO. It remains in this mode until it receives a value. After four dummy clocks, the first data byte Mode Reset (FFh) command. In subsequent FRQIO addressed is shifted out on the IO3, IO2, IO1 and IO0 execution, the command code is not input, saving lines, with each group of four bits shifted out at a cycles as described in Figure 17. If a FRQIO instruction maximum frequency fCT, during the falling edge of SCK. is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is ignored and will not The first bit (MSb) is output on IO3, while have any effects on the current cycle simultaneously the second bit is output on IO2, the Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 24 IS25WQ080 Figure 16. Fast Read Quad I/O Sequence (with command decode cycles) CE# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK 3 - BYTE ADDRESS IO0 INSTRUCTION = 1110 1011b 20 16 12 MODE BITS 8 4 0 4 IO1 21 17 13 9 5 1 5 IO2 22 18 14 10 6 2 6 IO3 23 19 15 11 7 3 7 CE# 16 17 18 19 20 21 22 23 24 25 26 27 SCK 4 dummy cycles DATA OUT 1 DATA OUT 2 DATA OUT 3 DATA OUT 4 IO0 4 0 4 0 4 0 4 0 4 IO1 5 1 5 1 5 1 5 1 5 IO2 6 2 6 2 6 2 6 2 6 IO3 7 3 7 3 7 3 7 3 7 IO switch from input to output Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 25 IS25WQ080 DEVICE OPERATION (CONTINUED) Figure 17. Fast Read Quad I/O Sequence (without command decode cycles) CE# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK 3 - BYTE ADDRESS MODE BITS 4 Dummy Clock IO0 DATA OUT 1 DATA OUT 2 20 16 12 8 4 0 4 4 0 4 IO1 21 17 13 9 5 1 5 5 1 5 IO2 22 18 14 10 6 2 6 6 2 6 IO3 23 19 15 11 7 3 7 7 3 7 MR COMMAND (MODE RESET) OPERATION The Mode Reset command is used to conclude subsequent FRDIO and FRQIO operations. It resets the Mode bits to a value that is not Ax. It should be executed after an FRDIO or FRQIO operation, and is recommended also as the first Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 command after a system reset. The timing sequence is different depending whether the MR command is used after an FRDIO or FRQIO, as shown in Figure 18. 26 IS25WQ080 Figure 18, Mode Reset Command Mode Reset for Dual I/O Mode Reset for Quad I/O CE# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK SIO SO INSTRUCTION = 1111 1111b INSTRUCTION = 1111 1111b HIGH IMPEDANCE Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 27 IS25WQ080 DEVICE OPERATION (CONTINUED) PAGE_PROG COMMAND (PAGE PROGRAM) OPERATION The Page Program (PAGE_PROG) instruction allows up to 256 bytes data to be programmed into memory in a single operation. The destination of the memory to be programmed must be outside the protected memory area set by the Block Protection (BP2, BP1, BP0) bits. A PAGE_PROG instruction which attempts to program into a page that is write-protected will be ignored. Before the execution of PAGE_PROG instruction, the Write Enable Latch (WEL) must be enabled through a Write Enable (WREN) instruction. The PAGE_PROG instruction code, three address bytes and program data (1 to 256 bytes) are input via the Sl line. Program operation will start immediately after the CE# is brought high, otherwise the PAGE_PROG instruction will not be executed. The internal control logic automatically handles the programming voltages and timing. During a program operation, all instructions will be ignored except the RDSR instruction. The progress or completion of the program operation can be determined by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the program operation is still in progress. If WIP bit is “0”, the program operation has completed. If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the previously latched data are discarded, and the last 256 bytes data are kept to be programmed into the page. The starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s. A byte cannot be reprogrammed without first erasing the whole sector or block. Figure 19. Page Program Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 28 IS25WQ080 DEVICE OPERATION (CONTINUED) Quad Input Page Program operation The Quad Input Page Program instruction allows up to 256 bytes data to be programmed into memory in a single operation with four pins (IO0, IO1, IO2 and IO3). The destination of the memory to be programmed must be outside the protected memory area set by the Block Protection (BP3, BP2, BP1, BP0) bits. A Quad Input Page Program instruction which attempts to program into a page that is writeprotected will be ignored. Before the execution of Quad Input Page Program instruction, the QE bit in the status register must be set to “1” and the Write Enable Latch (WEL) must be enabled through a Write Enable (WREN) instruction. RDSR instruction. The progress or completion of the program operation can be determined by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the program operation is still in progress. If WIP bit is “0”, the program operation has completed. If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the previously latched data are discarded, and the last 256 bytes data are kept to be programmed into the page. The starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. The Quad Input Page Program instruction code, three address bytes and program data (1 to 256 bytes) are input via the four pins (IO0, IO1, IO2 and IO3). Program operation will start immediately after the CE# is brought high, otherwise the Quad Input Page Program instruction will not be executed. The internal control logic automatically handles the programming voltages and timing. During a program operation, all instructions will be ignored except the Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s. A byte cannot be reprogrammed without first erasing the whole sector or block. Figure 20. Quad Page Program Sequence CE# 0 1 2 3 4 5 6 7 8 9 10 SCK 11 28 29 30 31 32 34 35 ... DATA IN 1 3 - BYTE ADDRESS IO0 33 DATA IN 2 4 0 4 0 5 1 5 1 IO2 6 2 6 2 IO3 7 3 7 3 INSTRUCTION = 0101 0010b 00110010b IO1 Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 23 22 21 ... 3 2 1 0 29 IS25WQ080 DEVICE OPERATION (CONTINUED) Dual Input Page Program operation The Dual Input Page Program instruction allows up to 256 bytes data to be programmed into memory in a single operation with two pins (IO0, IO1). The destination of the memory to be programmed must be outside the protected memory area set by the Block Protection (BP3, BP2, BP1, BP0) bits. A Dual Input Page Program instruction which attempts to program into a page that is write-protected will be ignored. Before the execution of Dual Input Page Program instruction, the Write Enable Latch (WEL) must be enabled through a Write Enable (WREN) instruction. The Dual Input Page Program instruction code, three address bytes and program data (1 to 256 bytes) are input via the two pins (IO0, IO1). Program operation will start immediately after the CE# is brought high, otherwise the Dual Input Page Program instruction will not be executed. The internal control logic automatically handles the programming voltages and timing. During a program operation, all instructions will be ignored except the RDSR instruction. The Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 progress or completion of the program operation can be determined by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the program operation is still in progress. If WIP bit is “0”, the program operation has completed. If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the previously latched data are discarded, and the last 256 bytes data are kept to be programmed into the page. The starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s. A byte cannot be reprogrammed without first erasing the whole sector or block. 30 IS25WQ080 Figure 21. Dual Input Page Program Sequence CE# 0 2 1 3 4 5 6 7 8 9 10 SCK 11 28 29 30 31 1 0 ... 3 - BYTE ADDRESS IO0 INSTRUCTION = 0101 0010b 23 22 21 ... 3 2 IO1 IO2 IO3 CE# 32 33 34 35 36 37 38 39 SCK DATA . . . IN 2 DATA IN 1 IO0 IO1 DATA IN n 6 4 2 0 6 4 2 0 6 7 5 3 1 7 5 3 1 7 IO2 IO3 Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 31 IS25WQ080 DEVICE OPERATION (CONTINUED) ERASE OPERATION operation can be determined by reading the WIP bit in the Status Register using a RDSR instruction. If the The memory array of the IS25WQ080 is organized into WIP bit is “1”, the erase operation is still in progress. If uniform 4 Kbyte sectors or 64 Kbyte uniform blocks (a the WIP bit is “0”, the erase operation has been block consists of sixteen adjacent sectors). completed. Before a byte can be reprogrammed, the sector or block that contains the byte must be erased (erasing sets bits to “1”). In order to erase the devices, there are three erase instructions available: Sector Erase (SECTOR_ER), Block Erase (BLOCK_ER) and Chip Erase (CHIP_ER). A sector erase operation allows any individual sector to be erased without affecting the data in other sectors. A block erase operation erases any individual block. A chip erase operation erases the whole memory array of a device. A sector erase, block erase or chip erase operation can be executed prior to any programming operation. SECTOR_ER COMMAND (SECTOR ERASE) OPERATION BLOCK_ER COMMAND (BLOCK ERASE) OPERATION A Block Erase (BLOCK_ER) instruction erases a 32K/64 Kbyte block of the IS25WQ080. Before the execution of a BLOCK_ER instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically after the completion of a block erase operation. The BLOCK_ER instruction code and three address bytes are input via SI. Erase operation will start immediately after the CE# is pulled high, otherwise the BLOCK_ER instruction will not be executed. The internal control logic automatically handles the erase voltage and timing. Refer to Figure 23 for Block Erase Sequence. A SECTOR_ER instruction erases a 4 Kbyte sector Before the execution of a SECTOR_ER instruction, the Write Enable Latch (WEL) must be set via a Write CHIP_ER COMMAND (CHIP ERASE) OPERATION Enable (WREN) instruction. The WEL bit is reset automatically after the completion of sector an erase A Chip Erase (CHIP_ER) instruction erases the entire operation. memory array of a IS25WQ080. Before the execution of CHIP_ER instruction, the Write Enable Latch (WEL) A SECTOR_ER instruction is entered, after CE# is must be set via a Write Enable (WREN) instruction. pulled low to select the device and stays low during the The WEL is reset automatically after completion of a entire instruction sequence The SECTOR_ER chip erase operation. instruction code, and three address bytes are input via SI. Erase operation will start immediately after CE# is The CHIP_ER instruction code is input via the SI. pulled high. The internal control logic automatically Erase operation will start immediately after CE# is handles the erase voltage and timing. Refer to Figure pulled high, otherwise the CHIP_ER instruction will not 22 for Sector Erase Sequence. be executed. The internal control logic automatically handles the erase voltage and timing. Refer to Figure During an erase operation, all instruction will be 24 for Chip Erase Sequence. ignored except the Read Status Register (RDSR) instruction. The progress or completion of the erase Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 32 IS25WQ080 DEVICE OPERATION (CONTINUED) Figure 22. Sector Erase Sequence Figure 23. Block Erase Sequence Figure 24. Chip Erase Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 33 IS25WQ080 DEVICE OPERATION (CONTINUED) Deep Power Down driven high, the power-down state will entered within the time duration of tDPD. While in the power-down state only the Release from Power-down / RDID instruction, which restores the device to normal operation, will be recognized. All other instructions are ignored. This includes the Read Status Register instruction, which is always available during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write protection. The Power-down (DP) instruction is for setting the device on the minimizing the power consumption (enter into Power-Down mode), the standby current is reduced from Isb1 to Isb2). During the Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. The instruction is initiated by driving the CE# pin low and shifting the instruction code “B9h” as show in the figure 25. The CE# pin must be driven high after the instruction has been latched. If this is not done the Power-Down will not be executed. After CE# pin Figure 25. Power Down Sequence CE# tdp 0 1 2 3 4 5 6 7 ... SCK SI INSTRUCTION = 1011 1001b ... Figure 26. Release Power Down Sequence CE# tRES1 0 1 2 3 4 5 6 ... SCK SI 7 INSTRUCTION = 1010 1011b Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 ... 34 IS25WQ080 DEVICE OPERATION (CONTINUED) Program Security information Row instruction (PSIR) The PSIR instructions can read and programmed (Erase) using three dedicated instructions. The program information Raw instruction is used to program at most 256 bytes to the security memory area (by changing bits from ‘1’ to ‘0’, only). Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL) bit. The program information Row instruction is entered by driving CE# pin Low, followed by the instruction code, three address bytes and at least one data byte on serial data input (SI). CE# pin must be driven High after the eighth bits of the last data byte has been latched in, otherwise the Program information Row instruction is not executed. If more than 256 bytes data are sent to a device, the address counter can not roll over. After CE# pin is driven High, the self-timed page program cycle (whose duration is tpotp) is initiated. While the program OTP cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed program cycle, and it is 0 when it is completed. At some unspecified time before the cycle is complete, the write enable latch (WEL) bit is reset. Figure 27. Program information Raw Sequence CE# 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 2 1 0 ... SCK SI INSTRUCTION = 1011 0001b 23 22 MSB ... 21 24-bit address CE# 32 33 34 35 36 37 38 39 40 41 42 43 ... SCK MSB SI 7 6 5 4 3 2 1 0 Data Byte 1 7 6 5 Data Byte 2 ... Data Byte n Note: 1  n  256 Note: 1. The SIR address is from 000000h to 0000FFh. 2. The SIR protection bit is in the address 000100h Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 35 IS25WQ080 DEVICE OPERATION (CONTINUED) To lock the OTP memory: Bit 0 of the OTP control byte, that is byte256, is used to permanently lock the OTP memory array. When bit 0 of byte 256 = ’1’, the 256 bytes of the OTP memory array can be programmed. When bit 0 of byte 256 = ‘0’, the 256 bytes of the OTP memory array are read-only and cannot be programmed anymore. Once a bit of the OTP memory has been programmed to ‘0’, it can no longer be set to ‘1’. Therefore, as soon as bit 0 of byte 256 (control byte) is set to ‘0’, the 256 bytes of the OTP memory array become read-only in a permanent way. Any program OTP (POTP) instruction issued while an erase, program or write cycle is in progress is rejected without having any effect on the cycle that is in progress Figure 28. OTP area OTP control byte Byte1 Byte2 Byte255Byte256 X X X X X Bit 1~bit 7 do not care Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 X X Bit 0 When bit 0 = 0 the 256 OTP bytes become read only 36 IS25WQ080 DEVICE OPERATION (CONTINUED) Read Security Information Row (RSIR) th maximum of 256 bytes to read, since once the 256 th byte has been read, the same (256 ) byte keeps being read on the SO pin. The RSIR instruction read the security information Row. There is no rollover mechanism with the read OTP (ROTP) instruction. This means that the read OTP (ROTP) instruction must be sent with a Fig 29. Read Security information Row instruction CE# 0 2 1 3 4 5 6 8 7 9 10 11 28 29 30 31 2 1 0 32 33 7 6 34 35 36 37 38 39 4 3 2 1 ... SCK SI INSTRUCTION = 0100 1011b 23 22 MSB 21 ... 24-bit address SO 5 0 Data Out0 CE# 40 41 42 43 44 45 46 47 ... SCK SI MSB SO 7 6 5 4 3 2 1 0 Data outpur 1 Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 7 6 5 Data output 2 ... Data output N 37 IS25WQ080 DEVICE OPERATION (CONTINUED) Program/Erase Suspend Resume The device allow the interruption of Sector-Erase, Block-Erase or Page-Program operations and conduct other operations. To enter the suspend/ resume mode: issuing 75h/B0h for suspend; 7Ah/30h for resume Read function register bit2 (PSUS) and bit1 (ESUS) to check suspend ready information. Suspend to suspend ready timing: 20us. Resume to another suspend timing: 1ms. *Note: It needs 500ns delay time from write command to suspend command Program/Erase Suspend During Sector-Erase or Block-Erase After erase suspend, WEL bit will be clear, only read related, resume and reset command can be accepted. (03h, 0Bh, BBh, Ebh, 05h, Abh, 9Fh, 90h, 4Bh) To execute a Program/Erase Suspend operation, the host drives CE# low, sends the Program/Erase Suspend command cycle (75h/B0H), then drives CE# high. The Function register indicates that the erase has been suspended by changing the ESUS bit from ‘0’ to ‘1,’ but the device will not accept another command until it is ready. To determine when the device will accept a new command, poll the WIP bit in the Status register or wait TWS. When ESUS bit is issued, the Write Enable Latch (WEL) bit will be reset. Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 Program/Erase Suspend During Page Programming Program suspend allows the interruption of all program operations. After program suspend, WEL bit will be cleared, only read related, resume and reset command can be accepted. (03h, 0Bh, BBh, Ebh, 05h, Abh, 9Fh, 90h, 4Bh) To execute a Program/Erase Suspend operation, the host drives CE# low, sends the Program/Erase Suspend command cycle (75h/B0H), then drives CE# high. The Function register indicates that the programming has been suspended by changing the PSUS bit from ‘0’ to ‘1,’ but the device will not accept another command until it is ready. To determine when the device will accept a new command, poll the WIP bit in the Status register or wait TWS. Program/Erase Resume Program/Erase Resume restarts a Program/Erase command that was suspended, and changes the suspend status bit in the (ESUS or PSUS) back to ‘0’. To execute a Program/Erase Resume operation, the host drives CE# low, sends the Program/Erase Resume command cycle (7Ah/30H), then drives CE# high. To determine if the internal, self-timed Write operation completed, poll the WIP bit in the Status register, or wait the specified time T SE, TBE or TPP for Sector- Erase, Block-Erase, or Page-Programming, respectively. The total write time before suspend and after resume will not exceed the uninterrupted write times TSE, TBE or TPP. 38 IS25WQ080 DEVICE OPERATION (CONTINUED) RDFR COMMAND (READ FUNCTION REGISTER) OPERATION The Read Function Register (RDFR) instruction provides access to the Erase/Program suspend register. During the execution of a program, erase or write status register suspend, which can be used to check the suspend status. Figure 30. Read Function Register Sequence 0000 0111 ABSOLUTE MAXIMUM RATINGS (1) Storage Temperature Standard Package Lead-free Package Input Voltage with Respect to Ground on All Pins (2) All Output Voltage with Respect to Ground VCC (2) Surface Mount Lead Soldering Temperature o o -65 C to +150 C o 240 C 3 Seconds o 260 C 3 Seconds -0.5 V to VCC + 0.5 V -0.5 V to VCC + 0.5 V -0.5 V to +4.0 V Notes: 1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. The functional operation of the device conditions that exceed those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condition for extended periods may affect device reliability. 2. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may overshoot VCC by + 2.0 V for a period of time not to exceed 20 ns. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may undershoot GND by -2.0 V for a period of time not to exceed 20 ns. Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 39 IS25WQ080 DC AND AC OPERATING RANGE Part Number IS25WQ080 o o Operating Temperature (Extended Grade) Operating Temperature (Industrial Grade) Operating Temperature (Automotive, A1 Grade) Operating Temperature (Automotive, A2 Grade) Operating Temperature (Automotive, A3 Grade) -40 C to 105 C o o -40 C to 85 C o o -40 C to 85 C o o -40 C to 105 C o o -40 C to 125 C Vcc Power Supply 1.65 V –1.95 V DC CHARACTERISTICS Applicable over recommended operating range from: VCC = 1.65 V to 1.95 V (unless otherwise noted). Symbo Parameter Condition ICC1 ICC2 Vcc Active Read Current Vcc Program/Erase Current VCC = 1.95 V at 33 MHz, SO = Open VCC = 1.95 V at 33 MHz, SO = Open ISB1 ISB2 ILI ILO VIL VIH Vcc Standby Current CMOS Vcc Standby Current TTL Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage VCC = 1.95 V, CE# = VCC VCC = 1.95 V, CE# = VIH to VCC VIN = 0V to VCC o o VIN = 0V to VCC, TAC = 0 C to 130 C VOL VOH Output Low Voltage Output High Voltage 1.65V < VCC < 1.95 V Min -0.5 0.7VCC Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 IOL = 100 A IOH = -100 A Ty p 10 15 Max Units 15 20 mA mA 50 3 1 1 0.3Vcc VCC + 0.4 A mA A A V V 0.2 V V VCC – 0.2 40 IS25WQ080 AC CHARACTERISTICS Applicable over recommended operating range from VCC = 1.65 V to 1.95 V CL = 1 TTL Gate and 30 pF (unless otherwise noted). Symbol Parameter fCT Clock Frequency for fast read mode fC tRI tFI tCKH tCKL tCEH Clock Frequency for read mode Input Rise Time Input Fall Time SCK High Time SCK Low Time CE# High Time tCS tCH tDS tDH tHS tHD CE# Setup Time CE# Hold Time Data In Setup Time Data in Hold Time Hold Setup Time Hold Time tV tOH tLZ tHZ tDIS tPP tVCS Output Valid Output Hold Time Normal Mode Hold to Output Low Z Hold to Output High Z Output Disable Time Sector Erase Time Block Erase Time (32KB) Block Erase Time(64KB) Chip Erase Time (8Mb) Chip Erase Time (16Mb) Page Program Time VCC Set-up Time tres1 tdp tw tsus trs tsrst Release Deep power down Deep power down Write Status Register time Suspend to suspend ready Resume to another suspend Software Reset cover time Tws Suspend time tEC Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 Min Typ Max Units 0 104 MHz 0 33 8 8 4 4 25 MHz ns ns ns ns ns 10 5 2 2 15 15 ns ns ns ns ns ns 8 200 200 100 150 0.5 0.5 5 12 0.7 ns ns ns ns ns ms s s s s ms 10 10 15 20 1 15 ms us ms ms 20 us 0 70 0.12 0.15 2 5 0.6 50 10 41 IS25WQ080 AC CHARACTERISTICS (CONTINUED) SERIAL INPUT/OUTPUT TIMING (1) Note: 1. For SPI Mode 0 (0,0) Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 42 IS25WQ080 AC CHARACTERISTICS (CONTINUED) HOLD TIMING PIN CAPACITANCE (f = 1 MHz, T = 25°C ) CIN COUT Typ Max Units Conditions 4 8 6 12 pF pF VIN = 0 V VOUT = 0 V Note: These parameters are characterized but not 100% tested. OUTPUT TEST LOAD INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL 30pF Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 43 IS25WQ080 POWER-UP AND POWER-DOWN At Power-up and Power-down, the device must not be selected (CE# must follow the voltage applied on Vcc) until Vcc reaches the correct value: 1. Vcc(min) at Power-up, and then for a further delay of tVCE 0 Vss at Power-down Usually a simple pull-up resistor on CE# can be used to insure safe and proper Power-up and Power-down. To avoid data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while Vcc is less than the POR threshold value (Vwi) during power up, the device does not respond to any instruction until a time delay of tPUW has elapsed after the moment that Vcc rised above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, Vcc is still below Vcc(min). No Write Status Register, Program or Erase instructions should be sent until the later of: - tPUW after Vcc passed the VWI threshold - tVCE after Vcc passed the Vcc(min) level At Power-up, the device is in the following state: - The device is in the Standby mode - The Write Enable Latch (WEL) bit is reset At Power-down, when Vcc drops from the operating voltage, to below the Vwi, all write operations are disabled and the device does not respond to any write instruction. Vcc Vcc(max) All Write Commands are Rejected Chip Selection Not Allowed Vcc(min) Reset State tVCE V (write inhibit) Read Access Allowed Device fully accessible tPUW Time Symbol tVCE *1 tPUW *1 Parameter Vcc(min) to CE# Low Power-Up time delay to Write instruction VWI*1 Write Inhibit Voltage Note : *1. These parameters are characterized only. Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 Min. Max. 10 1 2.4 1.3 Unit us 10 ms V 44 IS25WQ080 PROGRAM/ERASE PERFORMANCE Parameter Unit Typ Max Remarks Sector Erase Time Block Erase Time Chip Erase Time (16Mb) Chip Erase Time (8Mb) ms s s s 70 0.15 5 2 150 0.5 12 6 From writing erase command to erase completion From writing erase command to erase completion From writing erase command to erase completion From writing erase command to erase completion Page Programming Time Byte Program Additional Byte program ms us us 0.6 8 2.5 0.7 25 12 From writing program command to program completion First byte After first byte Note: These parameters are characterized and are not 100% tested. RELIABILITY CHARACTERISTICS Parameter Endurance Data Retention ESD – Human Body Model ESD – Machine Model Latch-Up Min 100,000 20 2,000 200 100 + ICC1 Typ Unit Cycles Years Volts Volts mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard 78 Note: These parameters are characterized and are not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 45 IS25WQ080 PACKAGE TYPE INFORMATION JN 8-Pin JEDEC 150mil Broad Small Outline Integrated Circuit (SOIC) Package (measure in millimeters) Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 46 IS25WQ080 PACKAGE TYPE INFORMATION (CONTINUED) JB 8-Pin JEDEC 208mil Broad Small Outline Integrated Circuit (SOIC) Package (measure in millimeters) Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 47 IS25WQ080 PACKAGE TYPE INFORMATION (CONTINUED) JK 8-pin Ulta-Thin Small Outline No-Lead (WSON) Package (measure in millimeters) Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 48 IS25WQ080 PACKAGE TYPE INFORMATION (CONTINUED) JA 8-pin 300mil wide body, Plastic Dual In-Line Package PDIP (measure in millimeters) Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 49 IS25WQ080 PACKAGE TYPE INFORMATION (CONTINUED) JM 16 pin – 16-lead Plastic Small Outline, 300 mils body width, package outline Millimeters 10.65 7.6 10.0 9 7.4 16 10.1 10.5 0.23 0.32 Detail A 1 8 2.25 2.4 2.35 2.65 Detail A 1.27 0.1 0.33 0.51 Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 0.1 0.3 0.4 1.27 00 80 50 IS25WQ080 PACKAGE TYPE INFORMATION (CONTINUED) JV 8-pin VVSOP 150mil Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 51 IS25WQ080 Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 52 IS25WQ080 Appendix1: Safe Guard function Safe Guard function is a security function for customer to protect by sector (4Kbyte). Every sector has one bit register to decide it will under safe guard protect or not. (“0”means protect and “1” means not protect by safe guard.) IS25WQ080 (sector 0~sector 255). IS25WQ016 (sector 0~sector 511) Mapping table for safe guard register Sector0 Sector1 Sector2 Sector3 Sector4 Sector5 Sector6 Sector7 Sector8 Sector9 Sector10 Sector11 Sector12 Sector13 Sector14 Sector15 01Fh 01Fh 01Fh 01Fh 01Fh 01Fh 01Fh 01Fh D7 D6 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 D5 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 D4 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 D3 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 D2 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 D1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 D0 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 …… …… …… …… …… …… …… …… …… …… Sector248 Sector249 Sector250 Sector251 Sector252 Sector253 Sector254 Sector255 Address 000h 000h 000h 000h 000h 000h 000h 000h 001h 001h 001h 001h 001h 001h 001h 001h 1 1 1 1 1 1 1 0 Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 53 IS25WQ080 Read Safe Guard register The READ Safe Guard instruction code is transmitted via the SlO line, followed by three address bytes (A23 – A0) of the first register location to be read. The first byte data (D7 – D0) addressed is then shifted out on the SO line, MSb first. The address is automatically incremented after each byte of data is shifted out. The read operation can be terminated at any time by driving CE# high (VIH) after the data comes out. CS 1 2 7 8 9 10 23 24 25 26 31 32 33 34 39 40 41 42 47 48 SCK SI 2Fh A23-A0 SO 1st byte 2nd byte D7-D0 D7-D0 Fig a. Timing waveform of Read Safe guard register Erase Safe Guard register If we want to erase the safe guard register to let the flash into unprotect status, it needs five continuous instructions. If any instruction is wrong, the erase command will be ignored. Erase wait time follow product erase timing spec. Fig b. shows the complete steps for Erase safe guard register. Program Safe Guard register If we want to erase the safe guard register to let the flash into unprotect status, it needs five continuous instructions. If any instruction is wrong, the program command will be ignored. The Program safe guard instruction allows up to 256 bytes data to be programmed into memory in a single operation. Program wait time follow product program timing spec. Fig c. shows the complete steps for program safe guard register. Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 54 IS25WQ080 Sector Protection Mode Erase CS 1 2 7 8 9 10 31 32 SCK SI 55h A23-A0 CS 1 2 7 8 9 10 31 32 SCK SI AAh A23-A0 CS 1 2 7 8 9 10 31 32 SCK SI 80h A23-A0 CS 1 2 7 8 9 10 31 32 SCK SI AAh A23-A0 CS 1 2 7 8 SCK SI 2Bh Fig b. Erase safe guard register Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 55 IS25WQ080 CS 1 2 7 8 9 10 31 32 SCK SI 55h A23-A0 CS 1 2 7 8 9 10 31 32 SCK SI AAh A23-A0 CS 1 2 7 8 9 10 31 32 SCK SI A0h A23-A0 CS 1 2 7 8 9 10 31 32 SCK SI 55h A23-A0 CS 1 2 7 8 9 10 31 32 33 34 39 40 41 42 47 48 SCK 1st byte SI 23h A23-A0 D7-D0 2nd byte D7-D0 Fig c. program safe guard register Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 56 IS25WQ080 Appendix2: Sector Unlock function Instruction Name Hex Code 26h 24h SECT_UNLOCK SECT_LOCK Operation Command Cycle 4 Bytes 1 Byte Sector unlock Sector lock Maximum Frequency 104 MHz 104 MHz SEC_UNLOCK COMMAND OPERATION The Sector unlock command allows the user to select a specific sector to allow program and erase operations. This instruction is effective when the blocks are designated as write-protected through the BP0, BP1, BP2 and BP3 bits in the status register. Only one sector can be enabled at any time. To enable a different sector, a previously enabled sector must be disabled by executing a Sector Lock command. The instruction code is followed by a 24-bit address specifying the target sector, but A0 through A11 are not decoded. The remaining sectors within the same block remain in read-only mode. Figure d. Sector Unlock Sequence Sector unlock CS 1 2 7 8 1 2 7 8 9 10 15 16 17 18 23 24 25 26 31 32 SCK SI 06h 26h A23-A16 A15-A8 A7-A0 In the sector unlock procedure, [A11:A0] needs equal to “0”, unlock procedure is completed, otherwise chip will regard it as illegal command. Note: 1.If the clock number will not match 8 clocks(command)+ 24 clocks (address), it will be ignored. 2.It must be executed write enable (06h) before sector unlock instructions. Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 57 IS25WQ080 SECT_LOCK COMMAND OPERATION The Sector Lock command reverses the function of the Sector Unlock command. The instruction code does not require an address to be specified, as only one sector can be enabled at a time. The remaining sectors within the same block remain in read-only mode. Figure e. Sector Lock Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 58 IS25WQ080 ORDERING INFORMATION: Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 59 IS25WQ080 Density 8M Frequency (MHz) Order Part Number Package 104 IS25WQ080-JBLE IS25WQ080-JNLE IS25WQ080-JKLE IS25WQ080-JVLE IS25WQ080-JBLA* IS25WQ080-JNLA* IS25WQ080-JKLA* IS25WQ080-JVLA* 8-pin SOIC 208mil 8-pin SOIC 150mil 8-pin WSON (5x6mm) 8-pin VVSOP 150mil 8-pin SOIC 208mil (Call Factory) 8-pin SOIC 150mil (Call Factory) 8-pin WSON (5x6mm) (Call Factory) 8-pin VVSOP 150mil (Call Factory) A* = A1,A2,A3 Automotive Temperature Ranges Integrated Silicon Solution, Inc.- www.issi.com Rev. 0B 02/28/2013 60