IS31FL3296
2-RGB/6-LED LED DRIVER
September 2023
GENERAL DESCRIPTION
FEATURES
The IS31FL3296 is a 6 LED current sink LED driver
with 1MHz I2C compatible programming interface.
Each LED can be dimmed individually with 12-bit
PWM data and color calibrated with 8-bit DC scaling
data, providing 4096 steps of linear PWM dimming
and 256 steps of DC current adjustment levels. All
channels output current can be further globally
adjusted in 64 steps.
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The IS31FL3296 operates from 2.7V to 5.5V and
features a very low operational and shutdown current.
Each channel of IS31FL3296 can operate in “PWM &
Current Level mode” or “Pattern mode” or “Current
Level Mode”. In “PWM & Current Level mode”, the
output current is set by PWM and 8-bits current level
registers. In “Pattern mode”, the timing characteristics
for RGB channels output can be individually adjusted
to maintain a pre-established pattern sequence
without requiring any additional MCU interaction, thus
saving valuable system resources. In “Current Level
mode”, the output current is set by 8-bits current level
register.
IS31FL3296 is available in QFN-20 (3mm×3mm) and
UTQFN-12 (2mm×2mm) packages. It operates from
2.7V to 5.5V over the temperature range of -40°C to
+125°C.
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APPLICATIONS
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Rev. C, 08/09/2023
Supply voltage range: 2.7V to 5.5V
6 current sinks, IOUT= 40mA (Max.)
Ultra-low operational current (200µA Typ. at VCC=
3.6V)
Power-saving mode: 1μA (Typ.) with SDB pulled
high and all LEDs off
Accurate color rendition
- 12-bit/8+4-bit PWM/channel
- 8-bit correction current/channel
- 6-bit global current adjusts
SDB rising edge reset I2C module
1MHz I2C-compatible interface
Auto breath function:
- 3 patterns for auto breath
- Fade IN/ Fade OUT time up to 8s
- Single pulse/Multi pulse/Manual control modes
for auto breath
- 3 colors pre-configure registers for color breath
23kHz PWM frequency (8+4-bit PWM mode)
QFN-20 (3mm×3mm) and UTQFN-12 (2mm×2mm)
packages
RoHS & Halogen-Free Compliance
TSCA Compliance
Hand-held devices for LED display
Gaming device (Mouse, Mouse Pad etc.)
IOT device (AI speaker etc.)
1
IS31FL3296
TYPICAL APPLICATION CIRCUIT
VBattery
VCC
1μF
RGB1
0.1μF
* Note 1
OUT1
VIH
OUT2
OUT3
100kΩ 4.7kΩ 4.7kΩ
SDA
IS31FL3296
RGB2
OUT4
SCL
Micro
Controller
VBattery
CLK/V_BM
SDB
OUT5
OUT6
100kΩ
AD
GND
Figure 1 Typical Application Circuit: 2 RGBs
VBattery
VBattery
VCC
1μF
VCC
0.1μF
AD
RGB1
OUT1
VIH
OUT2
OUT2
OUT3
OUT3
4.7kΩ 4.7kΩ
Micro
Controller
SDA
SCL
SDB
100kΩ
AD
IS31FL3296
OUT4
#1
OUT5
OUT6
VBattery
RGB1
*Note 1
RGB2
1μF
OUT1
0.1μF
SDA
SCL
IS31FL3296
OUT4
#2
SDB
VBattery
RGB2
OUT5
OUT6
CLK/V_BM
GND
GND
CLK/V_BM
Figure 2 Typical Application Circuit (Cascade Mode, for QFN-20 only)
Note 1: VDD is the high-level voltage for IS31FL3296, which is usually same as VCC of Micro Controller, e.g. if VCC of Micro Controller is 3.3V,
VIH= 3.3V. If VCC= 5V and VIH is lower than 2.8V, recommend to add level shift circuit.
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Rev. C, 08/09/2023
2
IS31FL3296
PIN CONFIGURATION
15 NC
NC 2
14 NC
12 SDA
NC 10
11 NC
OUT6 9
OUT3 5
OUT5 8
12 NC
10 AD
OUT2 4
11 SCL
13 SDB
GND 7
OUT1 3
VCC 1
9 SDB
OUT1 3
7 OUT6
OUT2
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Rev. C, 08/09/2023
GND 6
8 OUT5
OUT3 5
OUT4 2
4
UTQFN-12
16 AD
17 NC
18 SCL
VCC 1
OUT4 6
QFN-20
19 SDA
Pin Configuration (Top View)
20 CLK/V_BM
Package
3
IS31FL3296
PIN DESCRIPTION
No.
Pin
Description
1
VCC
Power supply.
2,10,11,12
,14,15,17
-
NC
No connect.
3~6
2~5
OUT1~OUT4
Current sink channels.
7
6
GND
Ground.
8~9
7~8
OUT5~OUT6
Current sink channels.
13
9
SDB
Shutdown the chip when pulled to low.
16
10
AD
I2C address setting.
18
11
SCL
I2C serial clock.
19
12
SDA
I2C serial data.
20
-
CLK/V_BM
CLK input or output for cascade connection.
When breathing mark function is enabled, this
pin is V_BM pin.
Thermal Pad
Connect to GND.
QFN
UTQFN
1
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Rev. C, 08/09/2023
4
IS31FL3296
ORDERING INFORMATION
Industrial Range: -40°C to +125°C
Order Part No.
Package
QTY/Reel
IS31FL3296-QFLS4-TR
IS31FL3296-UTLS4-TR
QFN-20, Lead-free
UTQFN-12, Lead-free
2500
3000
Copyright © 2023 Lumissil Microsystems. All rights reserved. Lumissil Microsystems reserves the right to make changes to this specification and its
products at any time without notice. Lumissil Microsystems assumes no liability arising out of the application or use of any information, products or
services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and
before placing orders for products.
Lumissil Microsystems does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use
in such applications unless Lumissil Microsystems receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assumes all such risks; and
c.) potential liability of Lumissil Microsystems is adequately protected under the circumstances
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Rev. C, 08/09/2023
5
IS31FL3296
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VCC
Voltage at any input pin
Maximum junction temperature, TJMAX
Storage temperature range, TSTG
Operating temperature range, TA=TJ
Package thermal resistance, junction to ambient (4-layer standard test PCB
based on JESD 51-2A), θJA
ESD (HBM)
ESD (CDM)
-0.3V ~+6.0V
-0.3V ~ VCC+0.3V
+150°C
-65°C ~+150°C
-40°C ~ +125°C
56.6°C/W (QFN)
126.1°C/W (UTQFN)
±2kV
±750V
Note 2: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
The following specifications apply for VCC= 5V, TA= 25°C, unless otherwise noted.
Symbol
VCC
ICC
ISD
IOUT
fOUT
Parameter
Conditions
Supply voltage
Quiescent power supply
current
Shutdown current
Constant current of channel
PWM frequency of output
Min.
Typ.
2.7
Max. Unit
5.5
VCC= 3.6V, VSDB= VCC, ALL channels
PWM= 0x00, 12-bit mode,
PFS = 220Hz
0.2
0.24
VCC= 5V, VSDB= VCC, ALL channels
PWM= 0x00, 12-bit mode,
PFS = 220Hz
0.26
0.29
VCC= 3.6V, VSDB= VCC, ALL channels
PWM= 0x00, 8+4-bit mode,
PFS = 23kHz
0.4
0.47
VCC= 5V, VSDB= VCC, ALL channels
PWM= 0x00, 8+4-bit mode,
PFS = 23kHz
0.55
0.6
VCC= 5V, VSDB= 0V
0.4
2
VCC= 3.6V, VSDB= 0V
0.3
1
VSDB= VCC=5V, Configuration Register
written “0000 0000
0.4
2
VSDB= VCC=3.6V, Configuration
Register written “0000 0000
0.3
1
30
32.5
GCC=0x3F, CL=0xFF, IMAX=0
V
mA
27.5
GCC=0x3F, CL=0xFF, IMAX=1
40
μA
mA
mA
OSC= 1.8MHz, PFS= 00, PWM
Resolution= 12-bit
200
220
240
Hz
OSC= 1.8MHz, PFS= 01, PWM
Resolution= 12-bit
400
440
480
Hz
OSC= 6MHz, PFS= 10, PWM
Resolution= 8+4-bit
21
23
25.3
kHz
∆IMAT
Between channels
IOUT= 30mA (Note 3)
-6.5
6.5
%
∆IACC
Between device to device
IOUT= 30mA (Note 4)
-6.5
6.5
%
∆IMAT
Between channels
IOUT=3mA (LCAI=1) (Note 3)
-7
7
%
∆IACC
Between device to device
IOUT=3mA (LCAI=1) (Note 4)
-7
7
%
Current sink headroom voltage
IOUT= 30mA
330
mV
VHR
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Rev. C, 08/09/2023
250
6
IS31FL3296
ELECTRICAL CHARACTERISTICS (CONTINUE)
The following specifications apply for VCC= 5V, TA= 25°C, unless otherwise noted.
Symbol
TSD
TSD_HY
Parameter
Conditions
Min.
Typ.
Max. Unit
Thermal shutdown
(Note 5)
165
°C
Thermal shutdown hysteresis
(Note 5)
18
°C
Logic Electrical Characteristics (SDA, SCL, SDB, AD)
VIL
Logic “0” input voltage
VCC= 2.7V ~ 5.5V
GND
0.4
V
VIH
Logic “1” input voltage
VCC= 2.7V ~ 5.5V
1.4
VCC
V
IIL
Logic “0” input current
VINPUT= 0V (Note 5)
5
nA
IIH
Logic “1” input current
VINPUT= VCC (Note 5)
5
nA
DIGITAL INPUT I2C SWITCHING CHARACTERISTICS (NOTE 5)
Fast Mode
Symbol
Parameter
Min.
Typ. Max.
fSCL
Serial-clock frequency
tBUF
Fast Mode Plus
Min.
Typ.
Max.
Units
-
400
-
1000
kHz
Bus free time between a STOP and a
START condition
1.3
-
0.5
-
μs
tHD, STA
Hold time (repeated) START condition
0.6
-
0.26
-
μs
tSU, STA
Repeated START condition setup time
0.6
-
0.26
-
μs
tSU, STO
STOP condition setup time
0.6
-
0.26
-
μs
tHD, DAT
Data hold time
-
-
-
-
μs
tSU, DAT
Data setup time
100
-
50
-
ns
tLOW
SCL clock low period
1.3
-
0.5
-
μs
tHIGH
SCL clock high period
0.7
-
0.26
-
μs
tR
Rise time of both SDA and SCL signals,
receiving (Note 6)
-
300
-
120
ns
tF
Fall time of both SDA and SCL signals,
receiving (Note 6)
-
300
-
120
ns
Note 3: IOUT mismatch (bit to bit) △IMAT is calculated:
ΔI MAT
I OUTn (n = 1 ~ 6)
=
I OUT1 + I OUT 2 + I OUT 3 + I OUT 4 + I OUT 5 + I OUT 6
6
− 1 × 100%
Note 4: IOUT accuracy (device to device) △IACC is calculated:
ΔI ACC
I OUT1 + I OUT 2 + I OUT 3 + I OUT 4 + I OUT 5 + I OUT 6
− I OUT ( IDEAL) )
(
6
× 100%
=
I OUT ( IDEAL)
Where IOUT(IDEAL)= 30mA or 3mA.
Note 5: Guaranteed by design.
Note 6: Cb = total capacitance of one bus line in pF. ISINK ≤ 6mA. tR and tF measured between 0.3×VCC and 0.7×VCC.
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Rev. C, 08/09/2023
7
IS31FL3296
FUNCTION BLOCK DIAGRAM
VCC
OUT1
CLK/V_BM
OUT6
OSC
Bandgap
Voltage
Ref
Bias
I2C
Interface
Digital
Control
PWM &
Sequence
Control
AD
SDA
SCL
GND
SDB
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Rev. C, 08/09/2023
8
IS31FL3296
DETAILED DESCRIPTION
I2C INTERFACE
IS31FL3296 uses a serial bus, which conforms to
the I2C protocol, to control the chip’s functions with
two wires: SCL and SDA. The IS31FL3296 has a 7bit slave address (A7:A1), followed by the R/W bit,
A0. Set A0 to “0” for a write command and set A0 to
“1” for a read command. The value of bits A1 and A2
are decided by the connection of the AD pin.
Table 1 Slave Address
AD
A7:A3
GND
SCL
SDA
VCC
A2:A1
A0
00
1110 1
01
10
0/1
11
AD connected to GND, A2:A1=00;
AD connected to VCC, A2:A1=11;
AD connected to SCL, A2:A1=01;
AD connected to SDA, A2:A1=10;
The SCL line is uni-directional. The SDA line is bidirectional (open-drain) with a pull-up resistor
(typically 400kHz I2C with 4.7kΩ, 1MHz I2C with
2kΩ). The maximum clock frequency specified by
the I2C standard is 1MHz. In this discussion, the
master is the microcontroller and the slave is the
IS31FL3296.
The timing diagram for the I2C is shown in Figure 3.
The SDA is latched in on the stable high level of the
SCL. When there is no interface activity, the SDA
line should be held high.
pull-up resistor). Then the master sends an SCL
pulse. If the IS31FL3296 has received the address
correctly, then it holds the SDA line low during the
SCL pulse. If the SDA line is not low, then the master
should send a “STOP” signal (discussed later) and
abort the transfer.
Following acknowledge of IS31FL3296, the register
address byte is sent, most significant bit first.
IS31FL3296 must generate another acknowledge
indicating that the register address has been
received.
Then 8-bit of data byte are sent next, most
significant bit first. Each data bit should be valid
while the SCL level is stable high. After the data byte
is sent, the IS31FL3296 must generate another
acknowledge to indicate that the data was received.
The “STOP” signal ends the transfer. To signal
“STOP”, the SDA signal goes high while the SCL
signal is high.
ADDRESS AUTO INCREMENT
To write multiple bytes of data into IS31FL3296, load
the address of the data register that the first data
byte is intended for. During the IS31FL3296
acknowledge of receiving the data byte, the internal
address pointer will increment by one. The next data
byte sent to IS31FL3296 will be placed in the new
address, and so on. The auto increment of the
address will continue as long as data continues to be
written to IS31FL3296 (Figure 6).
READING OPERATION
Most of the registers can be read.
The “START” signal is generated by lowering the
SDA signal while the SCL signal is high. The start
signal will alert all devices attached to the I2C bus to
check the incoming address against their own chip
address.
To read the register, after I2C start condition, the bus
master must send the IS31FL3296 device address
The 8-bit chip address is sent next, most significant
bit first. Each address bit must be stable while the
SCL level is high.
send the IS31FL3296 device address with the R/W
bit set to “1”. Data from the register defined by the
command byte is then sent from the IS31FL3296 to
the master (Figure 7).
After the last bit of the chip address is sent, the
master checks for the IS31FL3296’s acknowledge.
The master releases the SDA line high (through a
____
with the R/W bit set to “0”, followed by the register
address which determines which register is
accessed. Then restart I2C, the bus master should
____
Figure 3 I2C Interface Timing
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Rev. C, 08/09/2023
9
IS31FL3296
Figure 4 I2C Bit Transfer
Figure 5 I2C Writing to IS31FL3296 (Typical)
Figure 6 I2C Writing to IS31FL3296 (Automatic Address Increment)
Figure 7 I2C Reading from IS31FL3296
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Rev. C, 08/09/2023
10
IS31FL3296
Table 2 Registers Definitions
Address
Name
Function
00h
Product ID
For read only, read result is Slave
address
01h
Shutdown Control Register
02h
R/W Table
-
-
Set power down mode and outputs
R/W
shutdown control
3
0000 0000
Output Enable Register 1
Enable output 1~5
R/W
4
0001 1111
03h
Output Enable Register 2
Enable output 6
R/W
5
0000 1111
04h
Operation Configure Register 1
Set output 1~3 operation mode
R/W
6
0000 0000
05h
Operation Configure Register 2
Set output 4~6 operation mode
R/W
7
0000 0000
07h
Global Current Control Register
Set global current
R/W
9
0000 0000
08h
Hold Function Register
Set the hold function of each
Output
R/W
10
0000 0000
09h
V_BM Function Register
Clock and V_BM mark
R/W
11
0000 0000
0Bh
PWM Frequency Adjust Unlock
Register
Unlock the 0Ch
W
-
0000 0000
0Ch
PWM Frequency Adjust Register
Adjust the PWM Frequency
R/W
12
0000 0000
0Dh~0Fh
3 Pattern State Register
For reading the pattern running
state
R
13
0000 0000
10h~15h
OUT1~OUT6 Current Level Register Output current level data register
R/W
14
0000 0000
10h~15h
Color 1 Setting Register of Pattern
Output current level data registerColor 1
R/W
20h~25h
Color 2 Setting Register of Pattern
Output current level data registerColor 2
R/W
30h~35h
Color 3 Setting Register of Pattern
Output current level data registerColor 3
R/W
19/29/39h
Pattern TS &T1 Setting Register
Set the TS~T1 time
R/W
18
0000 0000
1A/2A/3Ah Pattern T2 &T3 Setting Register
Set the T2~T3 time
R/W
19
0000 0000
1B/2B/3Bh Pattern TP &T4 Setting Register
Set the TP~T4 time
R/W
20
0000 0000
1C/2C/3Ch Pattern Color Enable Register
Set the color enable/disable
R/W
21
0000 0001
1D/2D/3Dh Pattern Color Cycle Times Register
Set color repeat time
R/W
22
0000 0000
1E/2E/3Eh Pattern Register
Set next step and Gamma of each
pattern
R/W
23
0000 0000
1F/2F/3Fh Pattern Loop Times Register
Set the loop time of Pattern
R/W
24
0000 0000
40h~4Bh
PWM Register
Set PWM data
R/W
16
0000 0000
52h
Color Update Register
Update color data
R/W
-
0000 0000
53h
PWM Update Register
Update PWM data
R/W
-
0000 0000
Pattern Update Register
Update the time data and start to
run pattern
R/W
-
0000 0000
Reset Register
Reset the registers value to default
W
-
0000 0000
54/55/56h
5Fh
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Rev. C, 08/09/2023
R
Default
0000 0000
15
0000 0000
0000 0000
11
IS31FL3296
Table 4 02h Output Enable Register 1
Table 3 01h Shutdown Control Register
Bit
D7
Bit
D7:D5
Name LCAI IMAX MS SYNC PFS SLE SSD
Name
-
Default
Default
000
0
D6
0
D5
1
D4 D3:D2 D1
0
00
0
D0
0
The Shutdown Control Register sets software
shutdown and sleep modes of IS31FL3296.
When SLE bits are set to “1”, IS31FL3296 puts itself
in Sleep Mode if all OUTx outputs are off for >20s.
MCU command to the IS31FL3296 will wake it up
and disable the sleep mode. In Sleep Mode, all
OUTx are off without any bias. I_SLEEP= 1µA (Typ.).
The PFS bit sets the PWM resolution. PWM mode
can operate at 220Hz (12-bit, 8+4-bit mode), 440Hz
(12-bit, 8+4-bit mode) and 23kHz (8+4-bit mode).
MS and SYNC bit control the CLK pin status. When
MS and SYNC are both set to “1”, the CLK pin will
have a clock output to support cascade connection
between 2 or more IS31FL3296.
SSD
0
1
Software Shutdown Enable
Software shutdown mode
Normal operation
SLE
0
1
Sleep Mode Enable
Sleep mode disable
Sleep mode enable (20s after no output
current)
PFS
00
01
1x
PWM Frequency Select
220Hz (Force 220Hz in Pattern Mode or
PWM mode)
440Hz (12-bit PWM mode)
23kHz (8+4-bit PWM mode, 23kHz)
LCAI
0
1
Low Current Accuracy Improve
Default maximum 30mA
1/3 output current, and improve low current
accuracy
IMAX
0
1
Enable IOUT(MAX)=40mA
Default 30mA
IOUT(MAX)=40mA
MS
0
1
Master Slave
Slave, CLK is input
Master, CLK is clock output or Hi-Z status
SYNC Enable Synchronization Clock
0
Disable, CLK pin is Hi-Z status
1
Enable, CLK is clock output.
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Rev. C, 08/09/2023
D4
D3
D2
D1
D0
EN5 EN4 EN3 EN2 EN1
1
1
1
1
1
Table 5 03h Output Enable Register 2
Bit
D7:D4
D0
Name
-
EN6
Default
0000
1
The Output Enable Register enables/disables the
outputs independently. The ENx is only effective
when SSD= “1”.
ENx
0
1
Output Enable Control
Output disable
Output enable
Table 6 04h Operating Configure Register 1
Bit
D7
D6
D5:D4
D3:D2
D1:D0
Name
-
RGB
MOD3
MOD2
MOD1
Default
0
0
00
00
00
Table 7 05h Operating Configure Register 2
Bit
D7:D6
D5:D4
D3:D2
D1:D0
Name
-
MOD6
MOD5
MOD4
Default
00
00
00
00
The MODx (x=1~6) bits set output operation modes
of IS31FL3296.
When RGB= “1”, RGB Mode enables, OUT1~OUT6
running in RGB Mode, the MODx (x=1~6) bits are
invalid. When RGB= “0”, OUT1~OUT9 are controlled
by the MODx (x=1~6) bits.
RGB
0
1
Enable RGB Mode
Disable
Enable
MODx
00
01
1x
OUT1~OUT6 LED Mode
PWM & Current Level Mode
Pattern Mode
Current Level Mode
When the OUTx works in PWM & Current Level
Mode, it means the output current is controlled by
PWM Registers (40h~4Bh).
When the OUTx works in Pattern Mode, it means the
output current is controlled by Color Setting
Registers.
12
IS31FL3296
When the OUTx works in Current Level Mode,
means the output current is controlled by Current
Level Register.
Table 9 07h Global Current Control Register
Bit
D7:D6
D5:D0
Name
-
GCC
Default
00
11 1111
GCC CL
×
64 256
Breath mark function enable
Disable, CLK/V_BM is clock function
Enable, CLK/V_BM is V_BM function
PAMF Pattern mark function
00
Pattern 1
01
Pattern 2
10
Pattern 3
GCC registers control IOUT as shown in Formula (1).
If GCC= 0x3F, CL= 0xFF, IOUT= IOUT(MAX)
IOUT = 30mA×
BME
0
1
(1)
CMF
00
01
10
Color Mark Function
Color 1
Color 2
Color 3
TMP
00
01
1x
Time point
Start of T2
Start of TP
Start of T4
7
GCC = D[n] ⋅ 2 n
(2)
n=0
When IMAX=”1”, the 30mA will become 40mA.
Table 10 08h Hold Function Register
Bit
D7:D6
Name
-
Default
00
D5
D4
D3
D2
D1
D0
HFE3 HTS3 HFE2 HTS2 HFE1 HTS1
0
0
0
0
0
0
0Bh PWM Frequency Adjust Unlock Register
Write “0xA5” to 0Bh to unlock the PWM Frequency
Adjust Register (0Ch).
Table 12 0Ch PWM Frequency Adjust Register
The Hold Function Register configures hold time for
each output in Pattern Mode.
HTS
0
1
HFE
0
1
Hold Time Selection
Hold at end of T4 when color loop done
(always off)
Hold at end of T2 when color loop done
(always on)
Hold Function Enable
hold function disable
hold function enable
Table 11 09h V_BM Function Register
Bit
D7
D6
D5:D4
D3:D2
D1:D0
Name
VPE
BME
PAMF
CMF
TP
Default
0
0
00
00
00
The V_BM stores the V_BM pin function, the PAMF
selects the pattern and TP selects the T1-T4 to have
interruption.
VPE
0
1
Bit
D7:D3
D2:D0
Name
-
PFA
Default
000
000
Before access to 0Ch, the 0Bh needs to be written
with 0xA5 to unlock it.
The PFA bits adjust the PWM Frequency, for
example, if PWM frequency is 23kHz at 8+4-bit
PWM mode, if PFA is “000”, the PWM frequency is
23kHz, if PFA is “001”, the PWM frequency is
28.08kHz (+22.07%).
PFA
000
001
010
011
100
101
110
111
PWM Frequency Adjust
0%
+22.07%
+36.29%
+57.04%
-51.58%
-44.48%
-30.89%
-15.22%
V_BM Pull high EN
Disable, V_BM is open drain
Enable, V_BM is pull to VCC by 100kΩ
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13
IS31FL3296
Table 13 0Dh~0Fh Pattern State Register (Read
Only)
Bit
D7:D0
Name
Pattern State
Default
0000 0000
The Pattern State Register stores the pattern status.
0Dh register is used for pattern 1, 0Eh for pattern 2,
similarly 0Fh for pattern 3.
Below table shows the pattern running state.
the peak current of the outputs. ILED is the average
current of the outputs.
When IMAX= “1”, the 30mA will become 40mA.
When IS31FL3296 operates in Current Level Mode,
PWM = 4096 in above equation.
For example: in Current Level node only, if D7:D0 =
10110101,
IOUT = 30mA × (27 +25 +24 +22 +20)/256
When IS31FL3296 operates in PWM & Current
Level Mode, the value of CL and PWM will decide
the output current together.
When IS31FL3296 operates in Pattern Mode, PWM
changes to make the auto breathing effect.
Read
Result
D7:D0
Pattern
State
Color
Time
0x90
1001 0000
Running
-
TS
0x91
1001 0001
Running
Color1
T1
0x92
1001 0010
Running
Color1
T2
0x93
1001 0011
Running
Color1
T3
0xA4
1010 0100
Running
Color1
TP
0xA1
1010 0001
Running
Color2
T1
0xA2
1010 0010
Running
Color2
T2
0xA3
1010 0011
Running
Color2
T3
Bit
D7:D0
0xC4
1100 0100
Running
Color2
TP
Name
COL2_Oy
0xC1
1100 0001
Running
Color3
T1
Default
0000 0000
0xC2
1100 0010
Running
Color3
T2
0xC3
1100 0011
Running
Color3
T3
0x94
1001 0100
Running
Color3
TP
Bit
D7:D0
0x95
1001 0101
Running
-
T4
Name
COL3_Oy
0x00
0000 0000
Not
running
-
-
Default
0000 0000
Table 14 10h~15h OUT1~OUT6 Current Level
Register
Bit
D7:D0
Name
CL
Default
0000 0000
The output current may be computed using the
Formula (1):
GCC CL
×
IOUT = 30mA×
64 256
D7:D0
Name
COL1_Oy
Default
0000 0000
Table 15-2 20h~25h Color 2 Setting Register of
Pattern (OUT1~OUT6)
Table 15-3 30h~35h Color 3 Setting Register of
Pattern (OUT1~OUT6)
Color Setting Registers store the color setting for
each output in Pattern Mode. Check Pattern Color
Setting section for more information about the color
setting registers.
When IS31FL3296 operates in Pattern Mode, the
value of Color Registers will decide the output
current of each output in 256 levels.
The output current may be computed using the
Formula (4):
I OUT = 30 mA ×
COLx_Oy
256
COLx_Oy = D[n] ⋅ 2 n
(5)
(6)
n =0
(3)
n =0
I LED = 30mA×
Bit
7
(1)
7
CL = D[ n ] ⋅ 2 n
Table 15-1 10h~15h Color 1 Setting Register of
Pattern (OUT1~OUT6)
GCC CL PWM
×
×
64 256 4096
(4)
Where D[n] stands for the individual bit value, 1 or 0,
in location n, PWM is the value in 40h~4Bh, IOUT is
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Where D[n] stands for the individual bit value, 1 or 0,
in location n.
For example: if D7:D0 = 10110101,
IOUT = 30mA× (27 +25 +24 +22 +20)/256
IOUT is the peak current of the outputs.
Need to write Color Update Register (52h) to update
the data.
14
IS31FL3296
Table 16 40h~4Bh PWM Register
Reg
41h (43h, 45h)
40h (42h, 44h)
Bit
D7:D4
D3:D0
D7:D0
Name
-
PWM_H
PWM_L
Default
0000
0000
0000 0000
The PWM Registers (40h~4Bh) modulate LED
brightness of each channel. When IS31FL3296
operates in PWM & Current Level Mode, each
output has 2 bytes to modulate the PWM duty as
below Table 17 in 4096 steps, in Pattern Mode, the
PWM cannot be accessed.
The value of the PWM Registers decides the
average current of each LED noted ILED.
ILED computed by Formula (1):
I LED = 30mA×
GCC CL PWM
×
×
64 256 4096
(8)
Where IOUT is the peak current of the outputs. ILED is
the average current of the outputs.
11
PWM = D[ n] ⋅ 2 n
n=0
Where D[n] stands for the individual bit value, 1 or 0,
in location n.
For example: if PWM_H = 00001001, PWM_L =
10110101, N=4096, GCC=63, CL=255,
ILED = 30mA×(211 +28 +27 +25 +24 +22 +20)/4096
Table 17 Register of PWM & Current Level Mode
Mode
PWM &
Current
Level
Register
OUT1
OUT2
OUT3
PWM_H
41h
43h
45h
PWM_L
40h
42h
44h
CL
10h
11h
12h
Register
OUT4
OUT5
OUT6
PWM_H
47h
49h
4Bh
PWM_L
46h
48h
4Ah
CL
13h
14h
15h
Table 18 19/29/39h Pattern TS &T1 Setting
Register
Bit
D7:D3
D4:D0
Name
T1
TS
Default
0000
0000
The TS & T1 Setting Registers set the TS and T1
time in Pattern Mode. 19h register is used for pattern
1, 29h for pattern 2, similarly 39h for pattern 3.
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TS
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Pattern Start Time Selection
0.04s
0.16s
0.31s
0.46s
0.61s
0.92s
1.25s
1.92s
2.52s
3.12s
3.72s
5.04s
6.24s
7.44s
8.76s
9.96s
T1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Rise Time Selection
0.04s
0.16s
0.31s
0.46s
0.61s
0.92s
1.25s
1.92s
2.52s
3.12s
3.72s
5.04s
6.24s
7.44s
8.76s
9.96s
Table 19 1A/2A/3Ah Pattern T2 &T3 Setting
Register
Bit
D7:D3
D4:D0
Name
T3
T2
Default
0000
0000
The T2 & T3 Setting Registers set the T2 and T3 time
in Pattern Mode. 1Ah register is used for pattern 1,
2Ah for pattern 2, similarly 3Ah for pattern 3.
T2
0000
0001
0010
Hold Time Selection
0.04s
0.16s
0.31s
15
IS31FL3296
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0.46s
0.61s
0.92s
1.25s
1.92s
2.52s
3.12s
3.72s
5.04s
6.24s
7.44s
8.76s
9.96s
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0.46s
0.61s
0.92s
1.25s
1.92s
2.52s
3.12s
3.72s
5.04s
6.24s
7.44s
8.76s
9.96s
T3
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Fall Time Selection
0.04s
0.16s
0.31s
0.46s
0.61s
0.92s
1.25s
1.92s
2.52s
3.12s
3.72s
5.04s
6.24s
7.44s
8.76s
9.96s
T4
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Off Time Selection
0.04s
0.16s
0.31s
0.46s
0.61s
0.92s
1.25s
1.92s
2.52s
3.12s
3.72s
5.04s
6.24s
7.44s
8.76s
9.96s
Table 20 1B/2B/3Bh Pattern TP &T4 Setting
Register
Table 21 1C/2C/3Ch Pattern Color Enable
Register
Bit
D7:D4
D3:D0
Bit
D7:D3
D2
D1
D0
Name
T4
TP
Name
-
CE3
CE2
CE1
Default
0000
0000
Default
00000
0
0
1
The TP & T4 Setting Registers set the TP and T4
time in Pattern Mode. 1Bh register is used for
pattern 1, 2Bh for pattern 2, similarly 3Bh for pattern
3.
It should be noted that the sleep mode effective time
is 20s, it starts at the end of T3. If T4+TP is too long,
pattern loop will stop. When sleep mode enabled, T4
& TP do no longer than 4.20s.
TP
0000
0001
0010
Color Enable Register enables the color function for
each color in Pattern Mode. 1Ch register is used for
pattern 1, 2Ch for pattern 2, similarly 3Ch for pattern
3.
CEx
0
1
Color Enable Selection
Color x disable
Color x enable
Time between Pulses
0.04s
0.16s
0.31s
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16
IS31FL3296
Table 22 1D/2D/3Dh Pattern Color Cycle Times
Register
Bit
D7:D6
D5:D4
D3:D2
D1:D0
Name
-
CCT3
CCT2
CCT1
Default
00
00
00
00
Pattern Color Cycle Times Register sets Color loop
times for each color. 1Dh register is used for pattern
1, 2Dh for pattern 2, similarly 3Dh for pattern 3.
CCTx
00
01
10
11
Color Cycle Times Selection
Endless
1 time
2 times
3 times
MTPLT2
Multi-Pulse Loop Time
0000 Endless
0001 1 time
…
1111
15 times
NXT2
01
mode)
10
mode)
00/11
Pattern 2 Next
Go to Pattern 1 (Only effective in RGB
Go to Pattern 3 (Only effective in RGB
Just stop
Table 23-3 3Eh Pattern Register
Table 23-1 1Eh Pattern Register
Bit
D7:D4
D3
D2
D1:D0
Name
MTPLT3
GAM3
-
NXT3
0000
0
0
00
Bit
D7:D4
D3
D2
D1:D0
Default
Name
MTPLT1
GAM1
-
NXT1
Default
0000
0
0
00
GAM controls the gamma of pattern. MTPLT controls
the loop of Pattern.
GAM controls the gamma of pattern. MTPLT controls
the loop of Pattern.
GAM1 Gamma Selection
0
Gamma=2.4
1
Linearity
GAM3 Gamma Selection
0
Gamma=2.4
1
Linearity
MTPLT3
Multi-Pulse Loop Time
0000 Endless
0001 1 time
…
1111
15 times
MTPLT1
Multi-Pulse Loop Time
0000 Endless
0001 1 time
…
1111
15 times
NXT3
01
mode)
10
mode)
00/11
NXT1 Pattern 1 Next
01
Go to Pattern 2 (Only effective in RGB
mode)
00/10/11
Just stop
Pattern 3 Next
Go to Pattern 1 (Only effective in RGB
Go to Pattern 2 (Only effective in RGB
Just stop
Table 24 1F/2F/3Fh Pattern Loop Times Register
Table 23-2 2Eh Pattern Register
Bit
D7:D4
D3
D2
D1:D0
NXT2
00
Name
MTPLT2
GAM2
-
Default
0000
0
0
GAM controls the gamma of pattern. MTPLT controls
the loop of Pattern.
GAM2 Gamma Selection
0
Gamma=2.4
1
Linearity
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Bit
D7
D6:D0
Name
PLTx_H
PLTx_L
Default
0
000 0000
Pattern loop Times register sets the loop time of the
pattern. 1Fh register is used for pattern 1, 2Fh for
pattern 2, similarly 3Fh for pattern 3.
If PLT_H(D7)=0, PLT_L!=0
Pattern loop times:
17
IS31FL3296
54/55/56h Pattern time Update Register
6
Looptime = D[ n] × 2 n
(8)
Write “0xC5” to 54/55/56h will update the data of
19h~1Fh/29h~2Fh/39h~3Fh.
n =0
If PLT_H(D7)=0, PLT_L=0, endless
If PLT_H(D7)=1, PLT_L!=0
Pattern loop times:
5Fh Reset Register
6
Looptime = 16 × D[n] × 2
n
(9)
n =0
If PLT_H(D7)=1, PLT_L=0, endless
Once user writes “0xC5” to the Reset Register,
IS31FL3296 will reset all registers to their default
value. On initial power-up, the IS31FL3296 registers
are reset to their default values for a blank display.
52h Color Update Register
Write “0xC5” to 52h will update the data of
10h~15h/20h~25h/30h~35h.
53h PWM Update Register
Write “0xC5” to 53h will update the data of 40~4Bh.
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18
IS31FL3296
TYPICAL APPLICATION INFORMATION
GENERAL DESCRIPTION
CURRENT LEVEL MODE
IS31FL3296 is a 6-channel fun LED driver with auto
breathing mode. It has Pattern Mode and Current
Lever Mode for RGB lighting effects.
The Current Level Registers (10h~15h) are active
and can modulate LED peak current IOUT of each
output with 256 steps independently. For example, if
the data in Current Lever Register is “0000 0100”,
then the current level is the fourth step, with a
current level of 4/256.
CURRENT SETTING
The maximum output current is 30mA. When
IMAX=”1”, the 30mA will become 40mA. The Global
Current Control register GCC can be used to set a
lower current. The 8-bit CL registers (10h~15h)
control the individual currents for each of the outputs.
For example, OUT1, OUT2 and OUT3 drive an RGB
LED, OUT1 is Red LED, OUT2 is Green LED and
OUT 3 is Blue LED. If GCC and CL bits are the
same, then the RGB LED may appear pinkish, or not
so white. The CL bits can be used to adjust the
IOUTx current, so the RGB LED appears closer to a
pure white color. We call this CL bit adjustment by
another name: white balance register.
PWM FREQUENCY SELECT
The IS31FL3296 output channels operate with a
default 12-bit PWM resolution and the PWM
frequency of 220Hz. Because all the OUTx channels
are synchronized, the DC power supply will
experience large instantaneous current surges when
the OUTx channels turn ON. These current surges
will generate an AC ripple on the power supply which
causes stress to the decoupling capacitors. When
the AC ripple is applied to a monolithic ceramic
capacitor chip (MLCC) it will expand and contract
causing the PCB to flex and generate audible hum in
the range of between 20Hz to 20kHz, to avoid this
hum, there are many countermeasures, such as
selecting the capacitor type and value which will not
cause the PCB to flex and contract.
An additional option for avoiding audible hum is to
set the IS31FL3296’s output PWM frequency above
the audible frequency range. The Control Register
(00h) can be used to set the switching frequency to
220Hz/440Hz/23kHz. Combination settings of the
PFS bits will result in different PWM frequency,
select a value higher than 20kHz to avoid the
audible frequency range.
PWM CONTROL
The PWM Registers (40h~4Bh) can modulate LED
brightness of each channel with 4096 steps. For
example, if the data in PWM_H Register is “0000
0000” and in PWM_L Register is “0000 0100”, then
the PWM is 4/4096.
Writing new data continuously to the registers can
modulate the brightness of the LEDs to achieve a
breathing effect.
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In Current Level Mode, user doesn’t need to turn on
the CEx of 1Ch, a new value must be written to the
Current Level registers to change the output current.
Writing new data continuously to the registers can
modulate the brightness of the LEDs to achieve
breathing, blinking, or any other effects that the user
defines.
In Current Level Mode, the output current
(OUT1~OUT6) is configured by the Current Level
Register (10h~15h).
PWM & CURRENT LEVEL MODE
PWM & Current Level Mode is the combination of
PWM and Current Level Mode. In this mode, the
Current Level Registers (10h~15h) adjust the peak
current (IOUT) of the outputs, the PWM Registers
(40h~4Bh) adjust the duty cycle of the output current,
the finial result is the output average current ILED.
Table 17 Register of PWM & Current Level Mode
Mode
PWM &
Current
Level
Register
OUT1
OUT2
OUT3
PWM_H
41h
43h
45h
PWM_L
40h
42h
44h
CL
10h
11h
12h
Register
OUT4
OUT5
OUT6
PWM_H
47h
49h
4Bh
PWM_L
46h
48h
4Ah
CL
13h
14h
15h
RGB MODE
By setting the RGB bits of the Operating Configure
Register 1 (04h) to “1”, the IS31FL3296 will operate
in One Shot Programming mode. In this mode 6
channels (2 groups RGB) can be modulated
breathing cycle independently by TS~TP (Figure 11).
Setting different TS~T4 can achieve RGB breathing
with auto color changing. OUT1~OUT6 running in
Pattern 1 to Pattern 3. The maximum intensity of
each RGB can be adjusted independently by the
Color Setting Registers (10h~15h/20h~25h/30h~35h)
(Table 25).
Note, if IS31FL3296 operates in the One-Shot
Programming mode and then enters the shutdown
mode, an 8-bit data write operation to the Time
19
IS31FL3296
Update Register is required to restart the LED
breathing effect after the IC is re-enabled.
Table 25 Color Register of RGB Mode
Pattern
Color
…
OUT1 OUT2
Mode
Enable
OUT6
Table 26 Color Register of Pattern Mode
Pattern
Color
OUT1
OUT2
OUT3
Mode
Enable
Pattern 1
CE1(1Ch)
10h
11h
12h
CE2(1Ch)
20h
21h
22h
CE3(1Ch)
30h
31h
32h
Color
Enable
OUT4
OUT5
OUT6
CE1(2Ch)
13h
14h
15h
CE2(2Ch)
23h
24h
25h
CE3(2Ch)
33h
34h
35h
CE1(1Ch)
10h
11h
…
15h
Pattern 1 CE2(1Ch)
20h
21h
…
25h
CE3(1Ch)
30h
31h
…
35h
CE1(2Ch)
10h
11h
…
15h
Pattern 2 CE2(2Ch)
20h
21h
…
25h
CE3(2Ch)
30h
31h
…
35h
CE1(3Ch)
10h
11h
…
15h
PATTERN TIME SETTING
Pattern 3 CE2(3Ch)
20h
21h
…
25h
CE3(3Ch)
30h
31h
…
35h
User should configure the related pattern time
setting registers according to actual timing
requirements via I2C interface before starting pattern.
The pattern time includes TS, T1~T4 and TP. And
the pattern has three continue lighting cycle as Color
1~Color 3. Please check the LED OPERATING
MODE section for more about the time setting.
PATTERN MODE
By setting the MOD1~MOD6 bits of the Operating
Configure Register (04h/05h) to “01”, the
corresponding output will operate in Pattern Mode.
In Pattern Mode, the timing characteristics for output
current - current rising (T1), holding (T2), falling (T3)
and off time (TS, TP, T4) (Figure 10), can be
adjusted individually so that each output can
independently maintain a pre-established pattern
achieving mixing color breathing or a single-color
breathing without requiring any additional interface
activity, thus saving valuable system resources.
OUT1~OUT3 running in Pattern 1, OUT4~OUT6
running in Pattern 2.
PATTERN COLOR SETTING
In Pattern Mode, the LED color is defined by
COLx_Oy (x=1, 2, 3, y= 1, 2) bits in Color Setting
Registers (10h~15h/20h~25h/30h~35h). There are 3
RGB current combinations to generate 3 pre-defined
colors for display. More than one of the 3 pre-defined
colors can be chosen by setting CEx bits in Color
Enable Register (1Ch/2Ch/3Ch). When CEx is set,
the color x is allowed to be displayed in current
pattern.
In Pattern Mode, the output current (OUT1~OUT6) is
configured by the Color Setting Register of Pattern
as Table 26.
Pattern
Mode
Pattern 2
GAMMA CORRECTION
In order to perform a better visual LED breathing
effect, the device integrates gamma correction to the
Pattern Mode. The gamma correction causes the
change in intensity to appear more linear to the
human eye.
Gamma correction, also known as gamma
compression or encoding, is used to encode linear
luminance to match the non-linear characteristics of
display. Since the IS31FL3296 can modulate the
brightness of the LEDs with 256 steps, a gamma
correction function can be applied when computing
each subsequent LED intensity setting such that the
change in brightness matches the human eye's
brightness curve.
The IS31FL3296 provides three gamma corrections
which can be set by GAM bits of Pattern Registers
(1Eh/2Eh/3Eh) for each pattern. The gamma
correction is shown as below.
BREATHING MARK FUNCTION
In RGB mode or pattern mode, by setting the BME
bit of the Breathing Mark Register (09h) to “1”, the
breathing mark function is enabled. If the BME bit
sets to “0”, the breathing mark function disabled. The
CLK/V_BM pin is used as CLK. V_BM is an output
pin. The breathing mark function is useful as a signal
to notify the MCU when and where the pattern or
color is running.
After selecting the PAMF (Pattern Mark Function)
and CMF (Color Mark Function),
When you choose start of T2 (TMP=00): At the start
time T2, V_BM will induce a falling edge and hold
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20
IS31FL3296
logic low, at the end of time period T2, V_BM will
induce a rising edge.
When you choose start of TP(TMP=01): At the start
time TP, V_BM will induce a falling edge and hold
logic low, at the end of time period TP, V_BM will
induce a rising edge.
When you choose start of T4(TMP=1x): At the start
time T4, V_BM will induce a falling edge and hold
logic low, at the end of time period T4, V_BM will
induce a rising edge.
The VPE bit of 09h sets the pull up of the V_BM pin,
when VPE= “0”, the V_BM is open drain and it
needs external pull up resistor.
When VPE= “1”, the V_BM is pulled to internal VCC
by 100kΩ.
Color x
T1
T2
T3
TP
SHUTDOWN MODE
Shutdown mode can either be used as a means of
reducing power consumption or generating a
flashing display (repeatedly entering and leaving
shutdown mode). During shutdown mode all
registers retain their data.
Software Shutdown
By setting SSD bit of the Shutdown Register (01h) to
“0”, the IS31FL3296 will operate in software
shutdown mode, wherein it will consume only 0.4μA
(typ.) current. When the IS31FL3296 is in software
shutdown mode, all current sources are switched off.
Hardware Shutdown
The chip enters hardware shutdown mode when the
SDB pin is pulled low, wherein they consume only
0.4μA (Typ.) current. When set SDB high, the rising
edge will reset the I2C module, but the register
information retains.
T4
V_BM, TMP=’00’
V_BM, TMP=’01’
V_BM, TMP=’1x’
Figure 8 V_BM function
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Rev. C, 08/09/2023
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IS31FL3296
LED OPERATING MODE
The IS31FL3296 has three operating modes which can be chosen by the MODx bits of Operating Configure
Register (04h/05h).
Device Operation
PWM & Current
Level Mode
OUT1~
OUT6
4096 Steps PWM
Current Level
Mode
OUT1~
OUT6
256 Steps CL
OUT1
OUT2
OUT3
Run Pattern 1
OUT4
OUT5
OUT6
Run Pattern 2
OUT1~
OUT6
Run Pattern 1
& Pattern 2
& Pattern 3
Pattern
Mode
RGB Mode
Figure 9 Operating Mode Map
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Rev. C, 08/09/2023
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IS31FL3296
Pattern Mode
If MODx= 01 (Pattern Mode), OUT1~OUT3 can operate in Pattern Mode only and run the pattern 1, OUT4~OUT6
run the pattern 2.
Pattern Mode
PLT1
OUT1
OUT2
TS
OUT3
PLT2
OUT4
OUT5
OUT6 TS
Pattern1
T1
T4
T1
Pattern2
T4
STOP
STOP
Pattern2
PLT2
MTPLT2
CCT2
CCT1
Color 2
Color 1
TS
TP
T1
CCT3
T1
Color 3
TP
T1
TP
T4
STOP
Color 1
Gamma 1.0 (Linearity)
Gamma 2.4
T1
T2
T3
TP
CCT1
Figure 10 Pattern Mode
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Rev. C, 08/09/2023
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IS31FL3296
RGB Mode
If RGB= 1 (RGB Mode), OUT1~OUT6 can operate in Pattern Mode only and run pattern 1 and pattern 2 and
pattern 3.
RGB Mode
OUT1
~
OUT6
TS
PLT1
PLT2
PLT3
Pattern1
T1
T4
Pattern2
T1
T4
Pattern3
T1
T4
TS
STOP
TS
STOP
STOP
Pattern3
PLT3
MTPLT3
CCT2
CCT1
Color2
Color1
TS
T1
CCT3
TP
T1
Color3
TP
T1
TP
T4
STOP
Color 3
Gamma 1.0
(Linearity)
Gamma 2.4
T1
T2
T3
TP
CCT3
Figure 11 RGB Mode
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Rev. C, 08/09/2023
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IS31FL3296
CLASSIFICATION REFLOW PROFILES
Profile Feature
Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
150°C
200°C
60-120 seconds
Average ramp-up rate (Tsmax to Tp)
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
217°C
60-150 seconds
Peak package body temperature (Tp)*
Max 260°C
Time (tp)** within 5°C of the specified
classification temperature (Tc)
Max 30 seconds
Average ramp-down rate (Tp to Tsmax)
6°C/second max.
Time 25°C to peak temperature
8 minutes max.
Figure 12 Classification Profile
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Rev. C, 08/09/2023
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IS31FL3296
PACKAGE INFORMATION
QFN-20
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Rev. C, 08/09/2023
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IS31FL3296
UTQFN-12
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Rev. C, 08/09/2023
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IS31FL3296
RECOMMENDED LAND PATTERN
QFN-20
UTQFN-12
Note:
1. Land pattern complies to IPC-7351.
2. All dimensions in MM.
3. This document (including dimensions, notes & specs) is a recommendation based on typical circuit board manufacturing parameters. Since
land pattern design depends on many factors unknown (e.g.. User’s board manufacturing specs), user must determine suitability for use.
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Rev. C, 08/09/2023
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IS31FL3296
REVISION HISTORY
Revision
Detail Information
Date
0A
Initial release
2022.05.23
0B
Update the EC table and add the UTQFN-12 package
2022.09.08
A
Release to mass production
2022.09.19
B
Update Operating Configure Register (04h/05h) address in Patter Mode and LED
Operating Mode section
2023.03.16
C
1. Correct the definition of 0D~0Fh Pattern State Register
2. Correct the definition of (TMP) Time Mark Point in 09h V_BM Function Register
3. Add BREATHING MARK FUNCTION in TYPICAL APPLICATION INFORMATION
2023.08.09
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Rev. C, 08/09/2023
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