IS31IO7325-GRLS4-TR

IS31IO7325 MULTI-FUNCTION I/O DRIVER December 2020 GENERAL DESCRIPTION FEATURES The IS31IO7325 2-wire serial-interfaced peripheral features 16 I/O ports. Ports are divided into eight push pull I/Os and eight open-drain I/Os and transition detection.     Any of the 16 I/O ports can be configured as an input or an output. All I/O ports configured as inputs are continuously monitored for state changes (transition detection). State changes are indicated by the INTB output. The interrupt is latched, allowing detection of transient changes. When the IS31IO7325 is subsequently read through the serial interface, any pending interrupt is cleared. The open-drain outputs are rated to sink 20mA at 0.22V headroom, and are capable of driving LEDs. The RSTB input clears the serial interface, terminating any I2C communication to or from the IS31IO7325. The IS31IO7325 uses two address inputs to allow 4 I2C slave addresses. The slave address also determines the power-up logic state for the I/O ports.     400kHz I2C serial interface 2.4V to 5.5V operation 8 push-pull I/O ports 8 open-drain I/O ports, rated to 20mA sink current at 0.22V headroom Selectable I/O port power-up default logic states INTB output alerts change on inputs Low 0.3μA (Typ.) standby current -40°C ~ +125°C temperature range APPLICATIONS       Cell phones Notebooks SAN/NAS Satellite radio Servers Automotive TYPICAL APPLICATION CIRCUIT Figure 1 Typical Application Circuit Note 1: VBattery must be equal to or greater than VDD. VDD> VBattery is forbidden. VDD should be turned off when system power off because OD ports are open default. Lumissil Microsystems – www.lumissil.com Rev. D, 12/03/2020 1 IS31IO7325 PIN CONFIGURATION Package QFN-24 Pin Configuration (Top View) PP0 1 18 AD0 PP1 2 17 PP7 PP2 3 16 PP6 PP3 4 15 PP5 OD0 5 14 PP4 OD1 6 13 OD7 SOP-24 Lumissil Microsystems – www.lumissil.com Rev. D, 12/03/2020 2 IS31IO7325 PIN DESCRIPTION No. Pin Description 1~4, 14~17 PP0~PP7 CMOS push-pull I/O ports. 5~8, 10~13 OD0~OD7 Open-drain I/O ports. 9 GND Ground. 18 AD0 Address inputs. Select device slave address with AD0 and AD1. 19 SCL I2C-compatible serial-clock input. 20 SDA I2C-compatible serial-data I/O. 21 VCC Positive supply voltage. Bypass VCC to GND with a ceramic capacitor of at least 0.1μF. 22 INTB Interrupt output, active low. This is an open-drain output. 23 RSTB Reset input, active low. Drive RSTB pin low to clear the 2-wire interface. 24 AD1 Address inputs. Select device slave address with AD0 and AD1. Thermal Pad Connect to GND. Lumissil Microsystems – www.lumissil.com Rev. D, 12/03/2020 3 IS31IO7325 ORDERING INFORMATION Industrial Range: -40°C to +125°C Order Part No. Package QTY IS31IO7325-QFLS4-TR QFN-24, Lead-free 2500/Reel IS31IO7325-GRLS4 SOP-24, Lead-free 30/Tube Copyright  ©  2020  Lumissil  Microsystems.  All  rights  reserved.  Lumissil Microsystems reserves  the  right  to  make  changes  to  this  specification  and  its  products  at  any  time  without  notice.  Lumissil  Microsystems  assumes  no  liability  arising  out  of  the  application  or  use  of  any  information,  products  or  services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and  before placing orders for products.  Lumissil Microsystems does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can  reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in  such applications unless Lumissil Microsystems receives written assurance to its satisfaction, that:  a.) the risk of injury or damage has been minimized;  b.) the user assume all such risks; and  c.) potential liability of Lumissil Microsystems is adequately protected under the circumstances Lumissil Microsystems – www.lumissil.com Rev. D, 12/03/2020 4 IS31IO7325 ABSOLUTE MAXIMUM RATINGS Supply voltage, VCC SCL, SDA, AD, RSTB, INTB, OD0~OD7 PP0~PP7 PP source output current PP/OD sink current SDA sink current INTB sink current Maximum junction temperature, TJMAX Storage temperature range, TSTG Operating temperature range, TA ESD (HBM) ESD (CDM) -0.3V ~ +6.0V -0.3V ~ +6.0V -0.3V ~ VCC+0.3V ±100mA 120mA 10mA 10mA 150°C -65°C ~ +150°C -40°C ~ +125°C ±2kV ±1kV Note 2: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS VCC = 2.4V ~ 5.5V, TA = -40°C ~ +125°C, unless otherwise noted. Typical values are VCC = 3.3V, TA = 25°C. (Note 3) Symbol Parameter Condition Min. Typ. Unit 5.5 V VCC Supply voltage VPOR Power-on-reset voltage ISTB Standby current (Interface idle) SCL and SDA and other digital inputs at VCC 0.3 1.9 μA I+ Supply current (Interface running) fSCL = 400kHz, other digital inputs at VCC 8 20 μA VIH Input high-voltage SDA, SCL, AD0, AD1, RSTB, OD0~OD7, PP0~PP7 VIL Input low-voltage SDA, SCL, AD0, AD1, RSTB, OD0~OD7, PP0~PP7 Input leakage current SDA, SCL, AD0, AD1, RSTB, OD0~OD7, PP0~PP7 at VCC or GND CIN Input capacitance SDA, SCL, AD0, AD1, RSTB, OD0~OD7, PP0~PP7 (Note 5) VOL Output low voltage PP0~PP7, OD0~OD7 IIH, IIL VOH Output high voltage PP0~PP7 2.4 Max. VCC falling, TA = -40°C 2.35 VCC falling, TA = -20°C 2.3 1.4 V -0.2 0.4 V +0.2 μA 10 pF VCC = 2.5V, ISINK = 10mA 200 VCC = 3.3V, ISINK = 15mA 240 VCC = 5.0V, ISINK = 20mA 250 VCC = 2.5V, ISOURCE = 5mA 2.2 VCC = 3.3V, ISOURCE = 5mA 3.1 VCC = 5.0V, ISOURCE = 10mA 4.72 V mV V VOLSDA Output low-voltage SDA ISINK = 6mA 180 mV VOLINTB Output low-voltage INTB ISINK = 5mA 180 mV Lumissil Microsystems – www.lumissil.com Rev. D, 12/03/2020 5 IS31IO7325 TIMING CHARACTERISTICS VCC = 2.4V ~ 5.5V, TA = -40°C ~ +125°C, unless otherwise noted. Typical values are VCC = 3.3V, TA = 25°C. (Note 5) Symbol Parameter Condition Min. Typ. Max. Unit 400 kHz fSCL Serial-clock frequency tBUF Bus free time between a STOP and a START condition 1.3 μs tHD, STA Hold time (repeated) START condition 0.6 μs tSU, STA Repeated START condition setup time 0.6 μs tSU, STO STOP condition setup time 0.6 μs tHD, DAT Data hold time tSU, DAT Data setup time 100 ns tLOW SCL clock low period 1.3 μs tHIGH SCL clock high period 0.7 μs (Note 4) 0.9 μs tR Rise time of both SDA and SCL signals, receiving (Note 6) 20 + 0.1Cb 300 ns tF Fall time of both SDA and SCL signals, receiving (Note 6) 20 + 0.1Cb 300 ns Fall time of SDA transmitting (Note 6) 20 + 0.1Cb 250 ns tSP Pulse width of spike suppressed (Note 7) 50 Cb Capacitive load for each bus line tW RSTB pulse width tF, TX tRSTB ns 400 RSTB rising to START condition setup time pF 500 ns 1 μs Port and Interrupt INTB Timing Characteristic VCC = 2.4V ~ 5.5V, TA = -40°C ~ +125°C, unless otherwise noted. Typical values are VCC = 3.3V, TA = 25°C. (Note 5) Parameter Symbol Condition Min. Typ. Max. Unit Port output data valid tPV CL≤ 100pF 4 μs Port input setup time tPSU CL≤ 100pF 0 μs Port input hold time tPH CL≤ 100pF 4 μs INTB input data valid time tIV CL≤ 100pF 4 μs INTB reset delay time from acknowledge tIR CL≤ 100pF 4 μs Note 3: All parameters are tested at TA = 25°C. Specifications over temperature are guaranteed by design. Note 4: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. Note 5: Guaranteed by design. Note 6: Cb = total capacitance of one bus line in pF. ISINK ≤ 6mA. tR and tF measured between 0.3 × VCC and 0.7 × VCC. Note 7: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns. Lumissil Microsystems – www.lumissil.com Rev. D, 12/03/2020 6 IS31IO7325 Table 1 Power Up Default State for I/O Ports Pin Connection Port Power Up Default AD1 AD0 PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0 GND GND 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GND VCC 0 0 0 0 1 1 1 1 0 0 0 0 Hi-Z Hi-Z Hi-Z Hi-Z VCC GND 1 1 1 1 0 0 0 0 Hi-Z Hi-Z Hi-Z Hi-Z 0 0 0 0 VCC VCC 1 1 1 1 1 1 1 1 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Table 2 Command Byte Register Command Byte Address(Hex) Function Power Up Default Protocol 00 Input port A (OD0~OD7) XXXX XXXX R 01 Input port B (PP0~PP7) XXXX XXXX R 02 Output port A Refer to Table 1 R/W 03 Output port B Refer to Table 1 R/W 04 Port A configuration 0000 0000 R/W 05 Port B configuration 0000 0000 R/W 06 Port A interrupt control 0000 0000 R/W 07 Port B interrupt control 0000 0000 R/W Figure 2 2-Wire Serial Interface Timing Details Figure 3 START and STOP Conditions Figure 4 Bit Transfer Lumissil Microsystems – www.lumissil.com Rev. D, 12/03/2020 7 IS31IO7325 FUNCTIONAL BLOCK DIAGRAM VCC Power-on Reset RSTB AD0 AD1 SCL SDA Input Filter I2C Control I/O Ports OD0~OD7 PP0~PP7 INTB GND Lumissil Microsystems – www.lumissil.com Rev. D, 12/03/2020 8 IS31IO7325 APPLICATION INFORMATION FUNCTIONAL OVERVIEW The IS31IO7325 is a Multi-function I/O driver operating from a 2.4V to 5.5V supply with eight push-pull and eight open-drain I/O ports. Each open-drain and push-pull port is rated to sink 20mA at 0.22V headroom, and the entire device is rated to sink 320mA at 0.22V headroom into all ports combined. The outputs drive loads connected to supplies up to +5.5V. The IS31IO7325 is set to four I2C slave addresses using the address select inputs AD0 and AD1, and is accessed over an I2C serial interface up to 400kHz. The RSTB input clears the serial interface in case of a bus lockup, terminating any serial transaction to or from the IS31IO7325. The IS31IO7325 consists of input, output port registers, configuration registers and interrupt control register. All I/O ports offer latching transition detection when configured as inputs. All input ports are continuously monitored for changes. A latching interrupt output, INTB, is programmed to flag logic changes on ports used as inputs. Data changes on any input port forces INTB to a logic-low. Changing the I/O port level through the serial interface does not cause an interrupt. The interrupt output INTB is cleared successfully by reading the corresponding input/output ports. Ports default to logic-high or logic-low on power-up in groups of four (see Table 1). INITIAL POWER-UP On power-up, the transition detection logic is reset, and INTB is reset. The power-up default states of the 16 I/O ports are set according to the I2C slave address selection inputs, AD0 and AD1 (see Table 1). For I/O ports used as inputs, ensure that the default states are logic-high so that the I/O ports power up in the high impedance state. POWER-ON RESET The IS31IO7325 contains an integral power-on-reset (POR) circuit that ensures all registers are reset to a known state on power-up. When VCC rises above VPOR (2.3V max), the POR circuit releases the registers and 2-wire interface for normal operation. When VCC drops to less than VPOR, the IS31IO7325 resets all register contents to the POR defaults. RSTB Input The active-low RSTB input voids any I2C transaction involving the IS31IO7325, forcing the IS31IO7325 into the I2C STOP condition. A reset does not affect the interrupt output. STANDBY MODE automatically enters standby mode, drawing minimal supply current. I/O PORT INPUT TRANSITION DETECTION All I/O ports configured as inputs are monitored for changes since the expander was last accessed through the serial interface. The open-drain interrupt output, INTB, activates when one of the port pins changes states and only when the pin is configured as an input. The interrupt deactivates when the input/output register is read. A pin configured as an output does not cause an interrupt. Each 8-bit port register is read independently; therefore, an interrupt caused by port A (OD0~OD7) is not cleared by a read of port B (PP0~PP7)’s register. Changing an I/O from an output to an input may cause a false interrupt to occur if the state of that I/O does not match the content of output port register. The IS31IO7325 has interrupt control register to avoid false interrupt by setting the interrupt control register bit high firstly, when the I/O state is stable, clear the interrupt control register to enable the input transition detection function. ACCESSING THE IS31IO7325 Serial Addressing The IS31IO7325 operates as a slave that sends and receives data through a 2-wire interface. The interface uses a serial data line (SDA) and a serial clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master, typically a microcontroller, initiates all data transfers to and from the IS31IO7325, and generates the SCL clock that synchronizes the data transfer (see Figure 2). SDA operates as both an input and an open-drain output. A pull up resistor, typically 4.7kΩ, is required on SDA. SCL operates only as an input. A pull up resistor, typically 4.7kΩ, is required on SCL if there are multiple masters on the 2-wire interface, or if the master in a single-master system has an open-drain SCL output. Each transmission consists of a START condition sent by a master, followed by the IS31IO7325’s 7-bit slave addresses plus R/W bits, 1 or more data bytes, and finally a STOP condition (see Figure 3). START and STOP Conditions Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, the master issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission (see Figure 3) When the serial interface is idle, the IS31IO7325 Lumissil Microsystems – www.lumissil.com Rev. D, 12/03/2020 9 IS31IO7325 Bit Transfer One data bit is transferred during each clock pulse. The data on SDA must remain stable while SCL is high (Figure 4). Figure 5 Acknowledge Figure 6 Figure 7 Writing to the IS31IO7325 Reading I/O Ports of IS31IO7325 Slave Address The IS31IO7325 has a 7-bit slave address. The 8th bit ____ following the 7-bit slave address is the R/W bit. Set this bit low for a write command and high for a read command. The complete slave address is: A6:A2 A1 A0 R/W 10110 AD1 AD0 0/1 Data Bus Transaction The command byte is the first byte to follow the 8-bit device slave address during a write transmission (see Table 2). The command byte is used to determine which of the following registers are written or read. Lumissil Microsystems – www.lumissil.com Rev. D, 12/03/2020 Acknowledge The acknowledge bit is a clocked 9th bit the recipient uses to acknowledge receipt of each byte of data (see Figure 5). Each byte transferred effectively requires 9bits. The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse, such that the SDA line is stable low during the high period of the clock pulse. When the master is transmitting to the IS31IO7325, the device generates the acknowledge bit because the IS31IO7325 is the recipient. When the IS31IO7325 is transmitting to the master, the master generates the acknowledge bit because the master is the recipient. 10 IS31IO7325 Configuration Registers Port Output Signal-Level Translation The configuration registers configure the directions of the I/O pins. Set the bit in the respective configuration register to enable the corresponding port as an input. Clear the bit in the configuration register to enable the corresponding port as an output. The open-drain output architecture allows for level translation to higher or lower voltages than the IS31IO7325’s supply. Each of the push-pull output ports has protection diodes to V+ and GND. When a port output is driven to a voltage higher than V+ or lower than GND, the appropriate protection diode clamps the output to a diode drop above V+ or below GND. When the IS31IO7325 is powered down (V+ = 0V), every output port’s protection diodes to V+ and GND continue to appear as a diode clamp from each output to GND (Figure 8). Each of the I/O ports OD0~OD7 has a protection diode to GND (Figure 9). When a port is driven to a voltage lower than GND, the protection diode clamps the port to a diode drop below GND. To obtain a high voltage, Open-drain I/O Ports should connect a resistance to VCC (Figure 9). Interrupt Control Registers The interrupt control registers control the interrupt function of I/O ports when the I/O port used as input. Set the bit in the respective interrupt control register to disable the corresponding port’s interrupt function. Clear the bit in the interrupt control register to enable the corresponding port’s interrupt function. Writing to Port Registers Transmit data to the IS31IO7325 by sending the device slave address and setting the LSB to a logic zero. The command byte is sent after the address and determines which registers receive the data following the command byte. A write to either output port groups of the IS31IO7325 starts with the master transmitting the group’s slave ____ address with the R/W bit set low. The master can now transmit the command byte and data byte. In the case of LED load at OD outputs, the voltage at OD is between VCC and GND when OD is intended high to turn off the LED, causing ICC leakage current. A 100K pull-up resistor will force OD high at VCC and eliminate the leakage current. PP outputs can be set high at VCC with LED load, resulting in no leakage current without any pull-up resistor. Reading Port Registers To read the device data, the bus master must first send ____ the IS31IO7325 address with the R/W bit set to zero, followed by the command byte, which determines which register is accessed. After a restart, the bus master must then send the IS31IO7325 address with ____ the R/W bit set to 1. Data from the register defined by the command byte is then sent from the IS31IO7325 to the master. The IS31IO7325 acknowledges the slave address, and samples the ports during the acknowledge bit. INTB desserts during the slave address acknowledge. When the master reads one byte from the I/O ports of the IS31IO7325 and subsequently issues a STOP condition (Figure 7), the IS31IO7325 transmits the current port data, clears the change flags, and resets the transition detection. INTB desserts during the slave acknowledge. The new snapshot data is the current port data transmitted to the master, and therefore, port changes occurring during the transmission are detected. Figure 8 Figure 9 Lumissil Microsystems – www.lumissil.com Rev. D, 12/03/2020 IS31IO7325 Push-Pull I/O Ports Structure IS31IO7325 Open-Drain I/O Ports Structure 11 IS31IO7325 CLASSIFICATION REFLOW PROFILES Profile Feature Pb-Free Assembly Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) 150°C 200°C 60-120 seconds Average ramp-up rate (Tsmax to Tp) 3°C/second max. Liquidous temperature (TL) Time at liquidous (tL) 217°C 60-150 seconds Peak package body temperature (Tp)* Max 260°C Time (tp)** within 5°C of the specified classification temperature (Tc) Max 30 seconds Average ramp-down rate (Tp to Tsmax) 6°C/second max. Time 25°C to peak temperature 8 minutes max. Figure 10 Classification Profile Lumissil Microsystems – www.lumissil.com Rev. D, 12/03/2020 12 IS31IO7325 PACKAGE INFORMATION QFN-24 Lumissil Microsystems – www.lumissil.com Rev. D, 12/03/2020 13 IS31IO7325 SOP-24 Lumissil Microsystems – www.lumissil.com Rev. D, 12/03/2020 14 IS31IO7325 RECOMMENDED LAND PATTERN QFN-24 SOP-24 Note: 1. Land pattern complies to IPC-7351. 2. All dimensions in MM. 3. This document (including dimensions, notes & specs) is a recommendation based on typical circuit board manufacturing parameters. Since land pattern design depends on many factors unknown (eg. user’s board manufacturing specs), user must determine suitability for use. Lumissil Microsystems – www.lumissil.com Rev. D, 12/03/2020 15 IS31IO7325 REVISION HISTORY Revision Detail Information Date A Initial release 2011.12.31 B 1. ORDERING INFORMATION, SOP-24 packing QTY change from 1000pcs/reel to 30pcs/tube 2. P.14 remove the JCET words 2012.07.30 C 1.P.5 Add ESD(HBM/CDM)value 2.P.8 Add functional block 2014.01.02 D 1. Update Note 1 in first page 2. Update POD and add land pattern 2020.12.03 Lumissil Microsystems – www.lumissil.com Rev. D, 12/03/2020 16