IS41C16256C-35TLI-TR

IS41C16256C IS41LV16256C 256Kx16 4Mb DRAM WITH EDO PAGE MODE JANUARY 2013 FEATURES DESCRIPTION • TTL compatible inputs and outputs; tri-state I/O • Refresh Interval: 512 cycles/8 ms • Refresh Mode : RAS-Only, CAS-before-RAS (CBR), and Hidden • JEDEC standard pinout • Single power supply: 5V ± 10% (IS41C16256C) 3.3V ± 10% (IS41LV16256C) • Byte Write and Byte Read operation via two CAS • Industrial Temperature Range -40°C to +85°C The IS41C16256C and IS41LV16256C are 262,144 x 16-bit high-performance CMOS Dynamic Random Access Memories.  Both products offer accelerated cycle access EDO Page Mode. EDO Page Mode allows 512 random accesses within a single row with access cycle time as short as 14ns per 16-bit word. It is asynchronous, as it does not require a clock signal input to synchronize commands and I/O. These features make the IS41C/LV16256C ideally suited for high band-width graphics, digital signal processing, highperformance computing systems, and peripheral applications that run without a clock to synchronize with the DRAM. The IS41C/LV16256C is packaged in 40-pin TSOP (Type II). KEY TIMING PARAMETERS Parameter Max. RAS Access Time (trac) Max. CAS Access Time (tcac) Max. Column Address Access Time (taa) Min. EDO Page Mode Cycle Time (tpc) Min. Read/Write Cycle Time (trc) -35 Unit 35 ns 13 ns 18 ns 14 ns 60 ns Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. 1 Rev. A 1/31/2013 IS41C16256C IS41LV16256C PIN CONFIGURATIONS 40-Pin TSOP (Type II) VDD 1 40 GND I/O0 2 39 I/O15 I/O1 3 38 I/O14 I/O2 4 37 I/O13 I/O3 5 36 I/O12 VDD 6 35 GND I/O4 7 34 I/O11 I/O5 8 33 I/O10 I/O6 9 32 I/O9 I/O7 10 31 I/O8 NC 11 30 NC NC 12 29 LCAS WE 13 28 UCAS RAS 14 27 OE NC 15 26 A8 A0 16 25 A7 A1 17 24 A6 A2 18 23 A5 A3 19 22 A4 VDD 20 21 GND PIN DESCRIPTIONS A0-A8 Address Inputs I/O0-15 Data Inputs/Outputs WE Write Enable OE Output Enable RAS Row Address Strobe UCAS Upper Column Address Strobe LCAS Lower Column Address Strobe Vdd Power GND Ground NC No Connection 2 Integrated Silicon Solution, Inc. Rev. A 1/31/2013 IS41C16256C IS41LV16256C FUNCTIONAL BLOCK DIAGRAM OE WE LCAS UCAS CAS CLOCK GENERATOR WE CONTROL LOGICS CAS WE OE CONTROL LOGIC OE DATA I/O BUS COLUMN DECODERS SENSE AMPLIFIERS A0-A8 ADDRESS BUFFERS ROW DECODER REFRESH COUNTER MEMORY ARRAY 262,144 x 16 DATA I/O BUFFERS RAS CLOCK GENERATOR RAS RAS I/O0-I/O15 Integrated Silicon Solution, Inc. 3 Rev. A 1/31/2013 IS41C16256C IS41LV16256C TRUTH TABLE(5) Function RAS LCAS UCAS WE OE Address tr/tc I/O Standby H X X X X X High-Z Read: Word L L L H L ROW/COL Dout Read: Lower Byte L L H H L ROW/COL Lower Byte, Dout Upper Byte, High-Z Read: Upper Byte L H L H L ROW/COL Lower Byte, High-Z Upper Byte, Dout Write: Word (Early Write) L L L L X ROW/COL Din Write: Lower Byte (Early Write) L L H L X ROW/COL Lower Byte, Din Upper Byte, High-Z Write: Upper Byte (Early Write) L H L L X ROW/COL Lower Byte, High-Z Upper Byte, Din (1,2) Read-Write L L L H→L L→H ROW/COL Dout, Din EDO Page-Mode Read(2) 1st Cycle: L 2nd Cycle: L Any Cycle: L EDO Page-Mode Write(1) 1st Cycle: L 2nd Cycle: L EDO Page-Mode 1st Cycle: L Read-Write(1,2) 2nd Cycle: L Hidden Refresh Read(2)  L→H→L Write(1,3)  L→H→L RAS-Only Refresh L (4) CBR Refresh H→L H→L H→L L→H H→L H→L H→L H→L L L H L H→L H→L L→H H→L H→L H→L H→L L L H L H H H L L H→L H→L H L X H L L L X X L→H L→H L X X X ROW/COL NA/COL NA/NA ROW/COL NA/COL ROW/COL NA/COL ROW/COL ROW/COL ROW/NA X Dout Dout Dout Din Din Dout, Din Dout, Din Dout Dout High-Z High-Z Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. Early write only. 4. At least one of the two CAS signals must be active (LCAS or UCAS). 5. Commands valid only after proper intialization. 4 Integrated Silicon Solution, Inc. Rev. A 1/31/2013 IS41C16256C IS41LV16256C Functional Description The IS41C/LV16256C is a CMOS DRAM optimized for high-speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 18 address bits. These are entered nine bits (A0-A8) at a time. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first nine bits and CAS is used the latter nine bits. The IS41C/LV16256C has two CAS controls, LCAS and UCAS. The LCAS and UCAS inputs internally generates a CAS signal functioning in an identical manner to the single CAS input on the other 256K x 16 DRAMs. The key difference is that each CAS controls its corresponding I/O tristate logic (in conjunction with OE and WE and RAS). LCAS controls I/O0 through I/O7 and UCAS controls I/O8 through I/O15. The IS41C/LV16256C CAS function is determined by the first CAS (LCAS or UCAS) transitioning LOW and the last transitioning back HIGH. The two CAS controls give the IS41C/LV16256C both BYTE READ and BYTE WRITE cycle capabilities. Memory Cycle A memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tras time has expired. A new cycle must not be initiated until the minimum precharge time trp, tcp has elapsed. Read Cycle A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tar. Data Out becomes valid only when trac, taa, tcac and toea are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters. Write Cycle A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs last. Integrated Silicon Solution, Inc. Rev. A 1/31/2013 Refresh Cycle To retain data, 512 refresh cycles are required in each 8 ms period. There are two ways to refresh the memory. 1. By clocking each of the 512 row addresses (A0 through A8) with RAS at least once every 8 ms. Any read, write, read-modify-write or RAS-only cycle refreshes the addressed row. 2. Using a CAS-before-RAS refresh cycle. CAS-beforeRAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 9-bit counter provides the row addresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. Extended Data Out Page Mode EDO page mode operation permits all 512 columns within a selected row to be randomly accessed at a high data rate. In EDO page mode read cycle, the data-out is held to the next CAS cycle’s falling edge, instead of the rising edge. For this reason, the valid data output time in EDO page mode is extended compared with the fast page mode. In the fast page mode, the valid data output time becomes shorter as the CAS cycle time becomes shorter. Therefore, in EDO page mode, the timing margin in read cycle is larger than that of the fast page mode even if the CAS cycle time becomes shorter. In EDO page mode, due to the extended data function, the CAS cycle time can be shorter than in the fast page mode if the timing margin is the same. The EDO page mode allows both read and write operations during one RAS cycle, but the performance is equivalent to that of the fast page mode in that case. Power-On During Power-on, RAS, CAS, UCAS, LCAS, and WE must all track with Vdd (HIGH) to avoid current surges, and allow initialization to continue. An inital pause of 200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal). 5 IS41C16256C IS41LV16256C ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameters Vt Voltage on Any Pin Relative to GND 5V 3.3V Vdd Supply Voltage 5V 3.3V Iout Output Current Pd Power Dissipation Ta Operation Temperature Tstg Storage Temperature Rating Unit -1.0 to +7.0 V -0.5 to +4.6 V -1.0 to +7.0 V -0.5 to +4.6 V 50 mA 1 W -40 to +85 °C –55 to +125 °C Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.) Symbol Parameter Test Conditions Vdd Supply Voltage 5V 3.3V Vih Input High Voltage 5V 3.3V Vil Input Low Voltage 5V 3.3V Iil Input Leakage Current Any input 0V ≤ Vin ≤ Vdd Other inputs not under test = 0V Iio Output Leakage Current Output is disabled (Hi-Z) 0V ≤ Vout ≤ Vdd Voh Output High Voltage Level Ioh = –5.0 mA 5V Ioh = –2.0 mA 3.3V Vol Output Low Voltage Level Iol = +4.2 mA 5V Iol = +2.0 mA 3.3V Min. Typ. Max. Unit 4.5 5.0 5.5 V 3.0 3.3 3.6 V 2.4 — Vdd + 1.0 V 2.0 — Vdd + 0.3 V –1.0 — 0.8 V –0.3 — 0.8 V -5 5 µA -5 5 µA 2.4 2.4 — — — — 0.4 0.4 V V CAPACITANCE(1,2) Symbol Cin1 Cin2 Cio Parameter Input Capacitance: A0-A8 Input Capacitance: RAS, UCAS, LCAS, WE, OE Data Input/Output Capacitance: I/O0-I/O15 Max. 5 7 7 Unit pF pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, 6 Integrated Silicon Solution, Inc. Rev. A 1/31/2013 IS41C16256C IS41LV16256C ELECTRICAL CHARACTERISTICS(1) (Recommended Operation Conditions unless otherwise noted.) Symbol Idd1 Idd2 Idd3 Idd4 Idd5 Idd6 Parameter Test Condition Vdd Stand-by Current: TTL RAS, LCAS, UCAS ≥ Vih 5V 3.3V Stand-by Current: CMOS RAS, LCAS, UCAS ≥ Vdd – 0.2V 5V 3.3V Operating Current: RAS, LCAS, UCAS, 5V Random Read/Write(2,3,4) Address Cycling, trc = trc (min.) 3.3V Average Power Supply Current Operating Current: RAS = Vil, LCAS, UCAS, 5V EDO Page Mode(2,3,4) Cycling tpc = tpc (min.) 3.3V Average Power Supply Current Refresh Current: RAS Cycling, LCAS, UCAS ≥ Vih 5V RAS-Only(2,3) trc = trc (min.) 3.3V Average Power Supply Current Refresh Current: RAS, LCAS, UCAS Cycling 5V CBR(2,3,5) trc = trc (min.) 3.3V Average Power Supply Current Max. Unit 2 mA 2 mA 1 mA 1 mA 150 mA 90 mA 60 30 mA mA 90 60 mA mA 90 60 mA mA Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tref refresh requirement is exceeded. 2. Dependent on cycle rates. 3. Specified values are obtained with minimum cycle time and the output open. 4. Column-address is changed once each EDO page cycle. 5. Enables on-chip refresh and address counters. Integrated Silicon Solution, Inc. Rev. A 1/31/2013 7 IS41C16256C IS41LV16256C AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -35 Symbol Parameter Min. Max. Units trc Random READ or WRITE Cycle Time 70 — ns (6, 7) trac Access Time from RAS 35 — ns (6, 8, 15) tcac Access Time from CAS — 13 ns taa Access Time from Column-Address(6) — 18 ns tras RAS Pulse Width 35 10K ns trp RAS Precharge Time 25 — ns (26) tcas CAS Pulse Width 6 10K ns tcp CAS Precharge Time(9, 25) 6 — ns (21) tcsh CAS Hold Time 35 — ns trcd tasr trah tasc tcah tar trad tral trpc trsh trhcp tclz tcrp tod toe / toea toehc toep toes trcs trrh trch twch twcr 8 RAS to CAS Delay Time(10, 20) Row-Address Setup Time Row-Address Hold Time Column-Address Setup Time(20) Column-Address Hold Time(20) Column-Address Hold Time (referenced to RAS) RAS to Column-Address Delay Time(11) Column-Address to RAS Lead Time RAS to CAS Precharge Time RAS Hold Time(27) RAS Hold Time from CAS Precharge CAS to Output in Low-Z(15, 29) CAS to RAS Precharge Time(21) Output Disable Time(19, 28, 29) Output Enable Time(15, 16) OE HIGH Hold Time from CAS HIGH OE HIGH Pulse Width OE LOW to CAS HIGH Setup Time Read Command Setup Time(17, 20) Read Command Hold Time (referenced to RAS)(12) Read Command Hold Time (referenced to CAS)(12, 17, 21) Write Command Hold Time(17, 27) Write Command Hold Time (referenced to RAS)(17) 13 0 6 0 6 30 22 — —­ — — — ns ns ns ns ns ns 10 20 18 — 0 — 10 — 35 — 3 — 5 — 3 15 0 13 8 — 8 — 5 — 0 — 0 — ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0 — ns 5 30 — — ns ns Integrated Silicon Solution, Inc. Rev. A 1/31/2013 IS41C16256C IS41LV16256C AC CHARACTERISTICS (Continued)(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -35 Symbol Parameter Min. Max. Units (17) twp Write Command Pulse Width 5 — ns twpz WE Pulse Widths to Disable Outputs 10 — ns (17) trwl Write Command to RAS Lead Time 10 — ns tcwl Write Command to CAS Lead Time(17, 21) 8 — ns twcs Write Command Setup Time(14, 17, 20) 0 — ns tdhr Data-in Hold Time (referenced to RAS) 30 — ns tach Column-Address Setup Time to CAS 15 — ns Precharge during WRITE Cycle toeh OE Hold Time from WE during 8 — ns READ-MODIFY-WRITE cycle(18) tds tdh trwc trwd tcwd tawd tpc trasp tcpa tprwc tcoh / tdoh toff twhz tclch tcsr tchr tord twrp twrh tref tt Data-In Setup Time(15, 22) Data-In Hold Time(15, 22) READ-MODIFY-WRITE Cycle Time RAS to WE Delay Time during READ-MODIFY-WRITE Cycle(14) CAS to WE Delay Time(14, 20) Column-Address to WE Delay Time(14) EDO Page Mode READ or WRITE Cycle Time(24) RAS Pulse Width in EDO Page Mode Access Time from CAS Precharge(15) EDO Page Mode READ-WRITE Cycle Time(24) Data Output Hold after CAS LOW Output Buffer Turn-Off Delay from CAS or RAS(13,15,19, 29) Output Disable Delay from WE Last CAS going LOW to First CAS returning HIGH(23) CAS Setup Time (CBR REFRESH)(30, 20) CAS Hold Time (CBR REFRESH)(30, 21) OE Setup Time prior to RAS during HIDDEN REFRESH Cycle WE Setup Time (CBR Refresh) WE Hold Time (CBR Refresh) Refresh Period (512 Cycles) Transition Time (Rise or Fall)(2, 3) 0 6 80 46 — — — — ns ns ns ns 25 30 14 — — — ns ns ns 35 — 45 100K 20 — ns ns ns 5 3 — 10 ns ns 3 10 10 — ns ns 8 8 0 — — — ns ns ns 5 8 — 2 — — 8 50 ns ns ns ns Integrated Silicon Solution, Inc. 9 Rev. A 1/31/2013 IS41C16256C IS41LV16256C AC TEST CONDITIONS Output load: Two TTL Loads and 100 pF (Vdd = 5.0V ±10%) One TTL Load and 50 pF (Vdd = 3.3V ±10%) Input timing reference levels: Vih = 2.4V, Vil = 0.8V (Vdd = 5.0V ±10%); Vih = 2.0V, Vil = 0.8V (Vdd = 3.3V ±10%) Output timing reference levels: Voh = 2.4V, Vol = 0.4V (Vdd = 5V ±10%, 3.3V ±10%) Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tref refresh requirement is exceeded. 2. Vih (MIN) and Vil (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between Vih and Vil (or between Vil and Vih) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between Vih and Vil (or between Vil and Vih) in a monotonic manner. 4. If CAS and RAS = Vih, data output is High-Z. 5. If CAS = Vil, data output may contain data from the last valid READ cycle. 6. Measured with a load equivalent to one TTL gate and 50 pF. 7. Assumes that trcd < trcd (MAX). If trcd is greater than the maximum recommended value shown in this table, trac will increase by the amount that trcd exceeds the value shown. 8. Assumes that trcd ≥ trcd (MAX). 9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for tcp. 10. Operation with the trcd (MAX) limit ensures that trac (MAX) can be met. trcd (MAX) is specified as a reference point only; if trcd is greater than the specified trcd (MAX) limit, access time is controlled exclusively by tcac. 11. Operation within the trad (MAX) limit ensures that trcd (MAX) can be met. trad (MAX) is specified as a reference point only; if trad is greater than the specified trad (MAX) limit, access time is controlled exclusively by taa. 12. Either trch or trrh must be satisfied for a READ cycle. 13. toff (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to Voh or Vol. 14. twcs, trwd, tawd and tcwd are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If twcs ≥ twcs (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If trwd ≥ trwd (MIN), tawd ≥ tawd (MIN) and tcwd ≥ tcwd (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to Vih) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle. 15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS. 16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE WRITE or READ-MODIFY-WRITE is not possible. 17. Write command is defined as WE going low. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tod and toeh met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after toeh is met. 19. The I/Os are in open during READ cycles once tod or toff occur. 20. The first χCAS edge to transition LOW. 21. The last χCAS edge to transition HIGH. 22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 23. Last falling χCAS edge to first rising χCAS edge. 24. Last rising χCAS edge to next cycle’s last rising χCAS edge. 25. Last rising χCAS edge to first falling χCAS edge. 26. Each χCAS must meet minimum pulse width. 27. Last χCAS to go LOW. 28. I/Os controlled, regardless UCAS and LCAS. 29. The 3 ns minimum is a parameter guaranteed by design. 30. Enables on-chip refresh and address counters. 10 Integrated Silicon Solution, Inc. Rev. A 1/31/2013 IS41C16256C IS41LV16256C READ CYCLE tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD tRRH UCAS/LCAS tAR tRAD tASR ADDRESS tRAH tRAL tCAH tASC Row Column Row tRCS tRCH WE tAA tRAC tCAC tCLC I/O tOFF(1) Open Open Valid Data tOE tOD OE tOES Don't Care Note: 1. toff is referenced from rising edge of RAS or CAS, whichever occurs last. Integrated Silicon Solution, Inc. 11 Rev. A 1/31/2013 IS41C16256C IS41LV16256C EARLY WRITE CYCLE (OE = DON'T CARE) tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD UCAS/LCAS tAR tRAD tASR ADDRESS tRAH tRAL tCAH tACH tASC Row Column Row tCWL tRWL tWCR tWCS tWCH tWP WE tDHR tDS I/O tDH Valid Data Don't Care 12 Integrated Silicon Solution, Inc. Rev. A 1/31/2013 IS41C16256C IS41LV16256C READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) tRWC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD UCAS/LCAS tAR tRAD tASR tRAH tRAL tCAH tASC tACH ADDRESS Row Column Row tRWD tCWL tRWL tCWD tAWD tRCS tWP WE tAA tRAC tCAC tCLZ I/O tDS Open Valid DOUT tOE tOD tDH Valid DIN Open tOEH OE Don't Care Integrated Silicon Solution, Inc. 13 Rev. A 1/31/2013 IS41C16256C IS41LV16256C EDO-PAGE-MODE READ CYCLE tRASP tRP RAS tCSH tCRP tCAS, tCLCH tRCD tPC(1) tCAS, tCP tCLCH tRSH tCAS, tCLCH tCP tCP UCAS/LCAS tAR tRAD tASR ADDRESS tASC tCAH tASC Row Column tRAL tCAH tCAH tASC Column Column Row tRAH tRRH tRCS tRCH WE tAA tRAC tCAC tCLZ I/O Open tAA tCPA tCAC tCOH Valid Data tOE tOES tAA tCPA tCAC tCLZ tOFF Valid Data tOEHC Valid Data Open tOE tOD tOES tOD OE tOEP Don't Care Note: 1. tpc can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the tpc­specifications. 14 Integrated Silicon Solution, Inc. Rev. A 1/31/2013 IS41C16256C IS41LV16256C EDO-PAGE-MODE EARLY-WRITE CYCLE tRASP tRP RAS tCSH tCRP tPC tCAS, tCLCH tRCD tCP tCAS, tCLCH tCP tRSH tCAS, tCLCH tCP UCAS/LCAS tAR tACH tCAH tASC tRAD tASR ADDRESS tASC Row Column tRAH tACH tRAL tCAH tACH tCAH tASC Column tCWL tWCS Column tCWL tWCS tWCH tCWL tWCS tWCH tWCH tWP tWP Row tWP WE tWCR tDHR tRWL tDS tDS tDH I/O Valid Data tDS tDH Valid Data tDH Valid Data OE Don't Care Integrated Silicon Solution, Inc. Rev. A 1/31/2013 15 IS41C16256C IS41LV16256C EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles) tRASP tRP RAS tCSH tCRP tCAS, tCLCH tRCD tCP tPC / tPRWC(1) tCAS, tCLCH tRSH tCAS, tCLCH tCP tCP UCAS/LCAS tASR tRAH ADDRESS tAR tRAD tASC tCAH Row tASC tCAH Column tRWD tRCS tRAL tCAH tASC Column tCWL tWP Column tRWL tCWL tWP tCWL tWP tAWD tCWD Row tAWD tCWD tAWD tCWD WE tAA tRAC tCAC tCLZ I/O Open tAA tCPA tDH tDS DOUT tCAC tCLZ DIN DOUT tOD tOE tAA tCPA tDH tDS tCAC tCLZ DIN DOUT tOD tOE tDH tDS Open DIN tOD tOE tOEH OE Don't Care Note: 1. tpc can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the tpc specifications. 16 Integrated Silicon Solution, Inc. Rev. A 1/31/2013 IS41C16256C IS41LV16256C EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY WRITE) tRASP tRP RAS tCSH tPC tPC tCRP tCAS tRCD tCAS tCP tRSH tCAS tCP tCP UCAS/LCAS tASR tRAH ADDRESS tAR tRAD tASC Row tCAH tASC tCAH Column (A) tASC Column (B) tRCS tACH tRAL tCAH Column (N) Row tRCH tWCS tWCH WE tRAC tCAC I/O tAA Open tCPA tCAC tAA tWHZ tCOH Valid Data (A) tDS Valid Data (B) tDH DIN Open tOE OE Don't Care Integrated Silicon Solution, Inc. Rev. A 1/31/2013 17 IS41C16256C IS41LV16256C AC WAVEFORMS READ CYCLE (With WE-Controlled Disable) RAS tCSH tCRP tRCD tCP tCAS UCAS/LCAS tAR tRAD tASR ADDRESS tRAH tCAH tASC Row tASC Column Column tRCS tRCH tRCS tWPZ WE tAA tRAC tCAC tCLZ tWHZ Open I/O tCLZ Valid Data tOE Open tOD OE Don't Care RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE) tRC tRAS tRP RAS tCRP tRPC UCAS/LCAS tASR ADDRESS I/O tRAH Row Row Open Don't Care 18 Integrated Silicon Solution, Inc. Rev. A 1/31/2013 IS41C16256C IS41LV16256C CBR REFRESH CYCLE (Addresses; OE = DON'T CARE) tRP tRAS tRP tRAS RAS tCHR tRPC tCP tCHR tRPC tCSR tCSR UCAS/LCAS Open I/O WE tWRP tWRH tWRP tWRH HIDDEN REFRESH CYCLE (WE = HIGH; OE = LOW)(1) tRAS tRP tRAS RAS tCRP tRCD tASR tRAD tRAH tASC tRSH tCHR UCAS/LCAS tAR ADDRESS Row tRAL tCAH Column tAA tRAC tOFF(2) tCAC tCLZ I/O Open Open Valid Data tOE tOD tORD OE Don't Care Notes: 1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH. 2. toff is referenced from rising edge of RAS or CAS, whichever occurs last. Integrated Silicon Solution, Inc. 19 Rev. A 1/31/2013 IS41C16256C IS41LV16256C ORDERING INFORMATION : 3.3V Industrial Range: -40oC to +85oC peed (ns) S 35 Order Part No. IS41LV16256C-35TI IS41LV16256C-35TLI Package 400-mil TSOP (Type II) 400-mil TSOP (Type II), Lead-free ORDERING INFORMATION : 5V Industrial Range: -40oC to +85oC Speed (ns) Order Part No. Package IS41C16256C-35TI IS41C16256C-35TLI 400-mil TSOP (Type II) 400-mil TSOP (Type II), Lead-free 35 Note: The -35 speed option supports 35ns and 60ns timing specifications. 20 Integrated Silicon Solution, Inc. Rev. A 1/31/2013 IS41C16256C IS41LV16256C Integrated Silicon Solution, Inc. 21 Rev. A 1/31/2013