IS41LV16105D-50TLI

IS41LV16105D 1Mx16  16Mb DRAM WITH FAST PAGE MODE MARCH 2020 FEATURES DESCRIPTION • TTL compatible inputs and outputs; tristate I/O The ISSI IS41LV16105D is a 1,048,576 x 16-bit high-performance CMOS Dynamic Random Access Memories. Fast Page Mode allows 1,024 random accesses within a single row with access cycle time as short as 20 ns per 16-bit word. It is asynchronous, as it does not require a clock signal input to synchronize commands and I/O. • Refresh Interval: — 1,024 cycles/16 ms • Refresh Mode: ­— RAS-Only, CAS-before-RAS (CBR), and Hidden • JEDEC standard pinout • Single power supply: — 3.3V ± 10% • Byte Write and Byte Read operation via two CAS • Industrial Temperature Range -40oC to 85oC These features make the IS41LV16105D ideally suited for high-bandwidth graphics, digital signal processing, highperformance computing systems, and peripheral applications that run without a clock to synchronize with the DRAM. The IS41LV16105D is packaged in a 400-mil 50/44-pin TSOP (Type II). KEY TIMING PARAMETERS Parameter -50 Max. RAS Access Time (trac) 50 ns Max. CAS Access Time (tcac) 13 ns Max. Column Address Access Time (taa) 25 Unit ns Min. Fast Page Mode Cycle Time (tpc) 20 ns Min. Read/Write Cycle Time (trc) 84 ns Copyright © 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. 1 Rev. B 03/06/2020 IS41LV16105D PIN CONFIGURATIONS 44(50)-Pin TSOP (Type II) VDD 1 44 GND I/O0 2 43 I/O15 I/O1 3 42 I/O14 I/O2 4 41 I/O13 I/O3 5 40 I/O12 VDD 6 39 GND I/O4 7 38 I/O11 I/O5 8 37 I/O10 I/O6 9 36 I/O9 I/O7 10 35 I/O8 NC 11 34 NC NC 12 33 NC NC 13 32 LCAS WE 14 31 UCAS RAS 15 30 OE NC 16 29 A9 NC 17 28 A8 A0 18 27 A7 A1 19 26 A6 A2 20 25 A5 A3 21 24 A4 VDD 22 23 GND PIN DESCRIPTIONS A0-A9 Address Inputs I/O0-15 Data Inputs/Outputs WE Write Enable OE Output Enable RAS Row Address Strobe UCAS Upper Column Address Strobe LCAS Lower Column Address Strobe Vdd Power GND Ground NC 2 No Connection Integrated Silicon Solution, Inc. Rev. B 03/06/2020 IS41LV16105D FUNCTIONAL BLOCK DIAGRAM OE WE LCAS UCAS CAS CLOCK GENERATOR WE CONTROL LOGICS CAS WE OE CONTROL LOGIC OE DATA I/O BUS COLUMN DECODERS SENSE AMPLIFIERS A0-A9 ADDRESS BUFFERS ROW DECODER REFRESH COUNTER MEMORY ARRAY 1,048,576 x 16 DATA I/O BUFFERS RAS CLOCK GENERATOR RAS RAS I/O0-I/O15 Integrated Silicon Solution, Inc. 3 Rev. B 03/06/2020 IS41LV16105D TRUTH TABLE(5) Function RAS LCAS UCAS WE OE Address tr/tc I/O Standby H X X X X X High-Z Read: Word L L L H L ROW/COL Dout Read: Lower Byte L L H H L ROW/COL Lower Byte, Dout Upper Byte, High-Z Read: Upper Byte L H L H L ROW/COL Lower Byte, High-Z Upper Byte, Dout Write: Word (Early Write) L L L L X ROW/COL Din Write: Lower Byte (Early Write) L L H L X ROW/COL Lower Byte, Din Upper Byte, High-Z Write: Upper Byte (Early Write) L H L L X ROW/COL Lower Byte, High-Z Upper Byte, Din Read-Write(1,2) L L L H→L L→H ROW/COL Dout, Din (2) Hidden Refresh Read   L→H→L L L H L ROW/COL Dout Write(1,3)  L→H→L L L L X ROW/COL Dout RAS-Only Refresh CBR Refresh(4) L H H X X ROW/NA High-Z H→L L L H X X High-Z Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. EARLY WRITE only. 4. At least one of the two CAS signals must be active (LCAS or UCAS). 5. Commands valid only after initialization. 4 Integrated Silicon Solution, Inc. Rev. B 03/06/2020 IS41LV16105D Functional Description Write Cycle The IS41LV16105D is a CMOS DRAM optimized for highspeed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 16 address bits. These are entered ten bits (A0-A9) at a time. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first nine bits and CAS is used the latter nine bits. A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs last. The IS41LV16105D has two CAS controls, LCAS and UCAS. The LCAS and UCAS inputs internally generates a CAS signal functioning in an identical manner to the single CAS input on the other 1M x 16 DRAMs. The key difference is that each CAS controls its corresponding I/O tristate logic (in conjunction with OE and WE and RAS). LCAS controls I/O0 through I/O7 and UCAS controls I/ O8 through I/O15. 1. By clocking each of the 1,024 row addresses (A0 through A9) with RAS at least once every tref max. Any read, write, read-modify-write or RAS-only cycle refreshes the addressed row. The IS41LV16105D CAS function is determined by the first CAS (LCAS or UCAS) transitioning LOW and the last transitioning back HIGH. The two CAS controls give the IS41LV16105D both BYTE READ and BYTE WRITE cycle capabilities. Refresh Cycle To retain data, 1,024 refresh cycles are required in each 16 ms period. There are two ways to refresh the memory. 2. Using a CAS-before-RAS refresh cycle. CAS-beforeRAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 9-bit counter provides the row addresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. Memory Cycle Power-On A memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tras time has expired. A new cycle must not be initiated until the minimum precharge time trp, tcp has elapsed. During Power-On, RAS, UCAS, LCAS, and WE must all track with Vdd (HIGH) to avoid current surges, and allow initialization to continue. An initial pause of 200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal). Read Cycle A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tar. Data Out becomes valid only when trac, taa, tcac and toea are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters. Integrated Silicon Solution, Inc. 5 Rev. B 03/06/2020 IS41LV16105D ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameters Rating Unit Vt Voltage on Any Pin Relative to GND –0.5 to +4.6 V Vdd Supply Voltage –0.5 to +4.6 V Iout Output Current 50 mA Pd Power Dissipation 1 W Ta Industrial Temperature –40 to +85 °C Tstg Storage Temperature –55 to +125 °C Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.) Symbol Parameter Vdd Test Condition Min. Typ. Max. Unit Supply Voltage 3.0 3.3 3.6 V Vih Input High Voltage 2.0 — Vdd + 0.3 V Vil Input Low Voltage –0.3 — 0.8 V Iil Input Leakage Current –5 5 µA –5 5 µA Any input 0V < Vin < Vdd Other inputs not under test = 0V Iio Output Leakage Current Output is disabled (Hi-Z) 0V < Vout < Vdd Voh Output High Voltage Level Ioh = –2.0 mA 2.4 — V Vol Output Low Voltage Level — 0.4 V Iol = 2.0 mA CAPACITANCE(1,2) Symbol Cin1 Cin2 Cio Parameter Input Capacitance: A0-A9 Input Capacitance: RAS, UCAS, LCAS, WE, OE Data Input/Output Capacitance: I/O0-I/O15 Max. 5 7 7 Unit pF pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, 6 Integrated Silicon Solution, Inc. Rev. B 03/06/2020 IS41LV16105D ELECTRICAL CHARACTERISTICS(1) (Recommended Operation Conditions unless otherwise noted.) Symbol Parameter Test Condition Max. Unit Idd1 Stand-by Current: TTL RAS, LCAS, UCAS ≥ Vih 2 mA Idd2 Stand-by Current: CMOS RAS, LCAS, UCAS ≥ Vdd – 0.2V 1 mA Idd3 Operating Current: RAS, LCAS, UCAS, 90 mA 30 mA Refresh Current: RAS Cycling, LCAS, UCAS ≥ Vih 60 mA RAS-Only trc = trc (min.) Random Read/Write (2,3,4) Address Cycling, trc = trc (min.) Average Power Supply Current Idd4 Operating Current: RAS = Vil, LCAS, UCAS, Fast Page Mode(2,3,4) Cycling tpc = tpc (min.) Average Power Supply Current Idd5 (2,3) Average Power Supply Current Idd6 Refresh Current: RAS, LCAS, UCAS Cycling CBR(2,3,5) trc = trc (min.) 60 mA Average Power Supply Current Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tref refresh requirement is exceeded. 2. Dependent on cycle rates. 3. Specified values are obtained with minimum cycle time and the output open. 4. Column-address is changed once each EDO page cycle. 5. Enables on-chip refresh and address counters. Integrated Silicon Solution, Inc. 7 Rev. B 03/06/2020 IS41LV16105D AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -50 -60 Symbol Parameter Min. Max. Min. Max. trc Random READ or WRITE Cycle Time 84 — 104 — (6, 7) trac Access Time from RAS — 50 — 60 (6, 8, 15) tcac Access Time from CAS — 13 — 15 taa Access Time from Column-Address(6) — 25 — 30 tras RAS Pulse Width 50 10K 60 10K trp RAS Precharge Time 30 — 40 — (26) tcas CAS Pulse Width 8 10K 10 10K tcp CAS Precharge Time(9, 25) 9 — 9 — (21) tcsh CAS Hold Time 38 — 40 — (10, 20) trcd RAS to CAS Delay Time 12 37 14 45 tasr trah tasc tcah tar trad tral trpc trsh trhcp tclz tcrp tod toe toed toehc toep toes trcs trrh trch twch 8 Row-Address Setup Time 0 — 0 — Row-Address Hold Time 8 —­ 10 — Column-Address Setup Time(20) 0 — 0 — (20) Column-Address Hold Time 8 — 10 — Column-Address Hold Time 30 — 40 — (referenced to RAS) RAS to Column-Address Delay Time(11) 10 25 12 30 Column-Address to RAS Lead Time 25 — 30 — RAS to CAS Precharge Time 5 — 5 — (27) RAS Hold Time 8 — 10 — RAS Hold Time from CAS Precharge 37 — 37 — CAS to Output in Low-Z(15, 29) 0 — 0 — (21) CAS to RAS Precharge Time 5 — 5 — (19, 28, 29) Output Disable Time 3 15 3 15 Output Enable Time(15, 16) — 13 — 15 Output Enable Data Delay (Write) 20 — 20 — OE HIGH Hold Time from CAS HIGH 5 — 5 — OE HIGH Pulse Width 10 — 10 — OE LOW to CAS HIGH Setup Time 5 — 5 — (17, 20) Read Command Setup Time 0 — 0 — Read Command Hold Time 0 — 0 — (referenced to RAS)(12) Read Command Hold Time 0 — 0 — (referenced to CAS)(12, 17, 21) Write Command Hold Time(17, 27) 8 — 10 — Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Integrated Silicon Solution, Inc. Rev. B 03/06/2020 IS41LV16105D AC CHARACTERISTICS (Continued)(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -50 -60 Symbol Parameter Min. Max. Min. Max. twcr Write Command Hold Time 40 — 50 — (referenced to RAS)(17) twp Write Command Pulse Width(17) 8 — 10 — twpz WE Pulse Widths to Disable Outputs 10 — 10 — (17) trwl Write Command to RAS Lead Time 13 — 15 — tcwl Write Command to CAS Lead Time(17, 21) 8 — 10 — twcs Write Command Setup Time(14, 17, 20) 0 — 0 — tdhr Data-in Hold Time (referenced to RAS) 39 — 39 — tach Column-Address Setup Time to CAS 15 — 15 — Precharge during WRITE Cycle toeh OE Hold Time from WE during 8 — 10 — READ-MODIFY-WRITE cycle(18) tds Data-In Setup Time(15, 22) tdh Data-In Hold Time(15, 22) trwc READ-MODIFY-WRITE Cycle Time trwd RAS to WE Delay Time during READ-MODIFY-WRITE Cycle(14) tcwd CAS to WE Delay Time(14, 20) tawd Column-Address to WE Delay Time(14) tpc Fast Page Mode READ or WRITE Cycle Time(24) trasp RAS Pulse Width tcpa Access Time from CAS Precharge(15) tprwc READ-WRITE Cycle Time(24) tcoh Data Output Hold after CAS LOW toff Output Buffer Turn-Off Delay from CAS or RAS(13,15,19, 29) twhz Output Disable Delay from WE tclch Last CAS going LOW to First CAS returning HIGH(23) tcsr CAS Setup Time (CBR REFRESH)(30, 20) tchr CAS Hold Time (CBR REFRESH)(30, 21) tord OE Setup Time prior to RAS during HIDDEN REFRESH Cycle twrp WE Setup Time (CBR Refresh) twrh WE Hold Time (CBR Refresh) tref Auto Refresh Period (1,024 Cycles) tt Transition Time (Rise or Fall)(2, 3) Units ns ns ns ns ns ns ns ns ns 0 — 8 — 108 — 64 — 0 — 10 — 133 — 77 — ns ns ns ns 26 — 39 — 20 — 32 — 47 — 25 — ns ns ns 50 100K — 30 56 — 5 — 1.6 12 60 100K — 35 68 — 5 — 1.6 15 ns ns ns ns ns 3 10 10 — 3 10 10 — ns ns 5 — 8 — 0 — 5 — 10 — 0 — ns ns ns 5 — 8 — — 16 1 50 5 — 10 — — 16 1 50 ns ns ms ns Note: The -60 timing parameters are shown for reference only. The -50 speed option supports 50ns and 60ns timing specifications. Integrated Silicon Solution, Inc. 9 Rev. B 03/06/2020 IS41LV16105D AC TEST CONDITIONS Output load: One TTL Load and 50 pF Input timing reference levels: Vih = 2.0V, Vil = 0.8V Output timing reference levels: Voh = 2.4V, Vol = 0.4V Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tref refresh requirement is exceeded. 2. Vih (MIN) and Vil (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between Vih and Vil (or between Vil and Vih) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between Vih and Vil (or between Vil and Vih) in a monotonic manner. 4. If CAS and RAS = Vih, data output is High-Z. 5. If CAS = Vil, data output may contain data from the last valid READ cycle. 6. Measured with a load equivalent to one TTL gate and 50 pF. 7. Assumes that trcd ­trcd (MAX). If trcd is greater than the maximum recommended value shown in this table, trac will increase by the amount that trcd exceeds the value shown. 8. Assumes that trcd ž trcd (MAX). 9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for tcp. 10. Operation with the trcd (MAX) limit ensures that trac (MAX) can be met. trcd (MAX) is specified as a reference point only; if trcd is greater than the specified trcd (MAX) limit, access time is controlled exclusively by tcac. 11. Operation within the trad (MAX) limit ensures that trcd (MAX) can be met. trad (MAX) is specified as a reference point only; if trad is greater than the specified trad (MAX) limit, access time is controlled exclusively by taa. 12. Either trch or trrh must be satisfied for a READ cycle. 13. toff (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to Voh or Vol. 14. twcs, trwd, tawd and tcwd are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If twcs ž twcs (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If trwd ž trwd (MIN), tawd ž tawd (MIN) and tcwd ž tcwd (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to Vih) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle. 15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS. 16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE WRITE or READ-MODIFY-WRITE is not possible. 17. Write command is defined as WE going low. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tod and toeh met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after toeh is met. 19. The I/Os are in open during READ cycles once tod or toff occur. 20. The first χCAS edge to transition LOW. 21. The last χCAS edge to transition HIGH. 22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 23. Last falling χCAS edge to first rising χCAS edge. 24. Last rising χCAS edge to next cycle’s last rising χCAS edge. 25. Last rising χCAS edge to first falling χCAS edge. 26. Each χCAS must meet minimum pulse width. 27. Last χCAS to go LOW. 28. I/Os controlled, regardless UCAS and LCAS. 29. The 3 ns minimum is a parameter guaranteed by design. 30. Enables on-chip refresh and address counters. 10 Integrated Silicon Solution, Inc. Rev. B 03/06/2020 IS41LV16105D FAST-PAGE-MODE READ CYCLE tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD tRRH UCAS/LCAS tAR tRAD tASR ADDRESS tRAH tRAL tCAH tASC Row Column Row tRCS tRCH WE tAA tRAC tCAC tCLC I/O tOFF(1) Open Open Valid Data tOE tOD OE tOES Don’t Care Note: 1. toff is referenced from rising edge of RAS or CAS, whichever occurs last. Integrated Silicon Solution, Inc. 11 Rev. B 03/06/2020 IS41LV16105D FAST PAGE MODE READ-MODIFY-WRITE CYCLE tRASP tRP RAS tPRWC tCAS tCSH tCRP tCAS tRCD tRSH tCAS tCP tCRP tCP UCAS/LCAS tAR tRAH tRAD tASC tASR ADDRESS tCPWD tRAL tCAH tCPWD Row tCAH tAR Column tASC Column tCWL tRWD tAWD tCWD tRCS tCAH tASC Column tCWL tRWL tCWL tAWD tCWD tWP tAWD tCWD tWP tWP WE tAA tAA tCAC tCAC tOEA OE tCAC tOEA tOEZ tOED tRAC OUT IN tOEA tOEZ tOED tDH tDS tCLZ tCLZ I/O0-I/O15 tAA tDS OUT IN tDH tOEZ tOED tCLZ OUT tDS tDH IN Don’t Care 12 Integrated Silicon Solution, Inc. Rev. B 03/06/2020 IS41LV16105D FAST-PAGE-MODE EARLY WRITE CYCLE (OE = DON'T CARE) tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD UCAS/LCAS tAR tRAD tASR ADDRESS tRAH tRAL tCAH tACH tASC Row Column Row tCWL tRWL tWCR tWCS tWCH tWP WE tDHR tDS I/O tDH Valid Data Don’t Care Integrated Silicon Solution, Inc. 13 Rev. B 03/06/2020 IS41LV16105D FAST-PAGE-MODE READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) tRWC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD UCAS/LCAS tAR tRAD tASR tRAH tRAL tCAH tASC tACH ADDRESS Row Column Row tRWD tCWL tRWL tCWD tRCS tAWD tWP WE tAA tRAC tCAC tCLZ I/O tDS Open Valid DOUT tOE tOD tDH Valid DIN Open tOEH OE Don’t Care 14 Integrated Silicon Solution, Inc. Rev. B 03/06/2020 IS41LV16105D FAST PAGE MODE EARLY WRITE CYCLE tRASP tRP RAS tCRP tCAS tRCD tRHCP tRSH tCAS tPC tCAS tCSH tCP tCP tCRP UCAS/LCAS tAR tRAH tRAD tASC tASR ADDRESS Row tCAH tASC tAR Column tWCH tASC Column tCWL tWCS tRAL tCAH Column tCWL tCWL tWCH tWCS tWCS tWP tCAH tWP tWCH tWP WE tWCR OE tDHR tDS I/O0-I/O15 tDH Valid DIN tDS tDH Valid DIN tDS tDH Valid DIN Don’t Care Integrated Silicon Solution, Inc. 15 Rev. B 03/06/2020 IS41LV16105D AC WAVEFORMS READ CYCLE (With WE-Controlled Disable) RAS tCSH tCRP tRCD tCP tCAS UCAS/LCAS tAR tRAD tASR ADDRESS tRAH tCAH tASC Row tASC Column Column tRCS tRCH tRCS tWPZ WE tAA tRAC tCAC tCLZ Open I/O tWHZ tCLZ Valid Data Open tOE tOD OE Don’t Care RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE) tRC tRAS tRP RAS tCRP tRPC UCAS/LCAS tASR ADDRESS I/O tRAH Row Row Open Don’t Care 16 Integrated Silicon Solution, Inc. Rev. B 03/06/2020 IS41LV16105D CBR REFRESH CYCLE (Addresses; OE = DON'T CARE) tRP tRAS tRP tRAS RAS tCHR tRPC tCP tCHR tRPC tCSR tCSR UCAS/LCAS Open I/O WE tWRP tWRP tWRH tWRH HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW) tRAS tRP tRAS RAS tCRP tRCD tRSH tCHR UCAS/LCAS tAR tRAD tRAH tASC tASR ADDRESS Row tRAL tCAH Column tAA tRAC tOFF(2) tCAC tCLZ I/O Open Valid Data tOE Open tOD tORD OE Don’t Care Notes: 1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH. 2. toff is referenced from rising edge of RAS or CAS, whichever occurs last. Integrated Silicon Solution, Inc. 17 Rev. B 03/06/2020 IS41LV16105D ORDERING INFORMATION : Industrial Range: -40oC to +85oC Speed (ns) Order Part No. Package 50 IS41LV16105D-50TLI 400-mil TSOP (Type II), Lead-free Note: The -50 speed option supports 50ns and 60ns timing specifications. 18 Integrated Silicon Solution, Inc. Rev. B 03/06/2020 IS41LV16105D Integrated Silicon Solution, Inc. 19 Rev. B 03/06/2020