IS42RM32800D-75TLI

IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D 32Mx8, 16Mx16, 8Mx32 256Mb Mobile Synchronous DRAM FEATURES OCTOBER 2009 • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access and precharge • Programmable CAS latency: 2, 3 • Programmable Burst Length: 1, 2, 4, 8, and Full Page • Programmable Burst Sequence: • Sequential and Interleave • Auto Refresh (CBR) • TCSR (Temperature Compensated Self Refresh) • PASR (Partial Arrays Self Refresh): 1/16, 1/8, 1/4, 1/2, and Full • Deep Power Down Mode (DPD) • Driver Strength Control (DS): 1/4, 1/2, and Full OPTIONS • Configurations: - 32M x 8 - 16M x 16 - 8M x 32 • Power Supply IS42SMxxx – Vdd/Vddq = 3.3 V IS42RMxxx – Vdd/Vddq = 2.5 V • Packages: x8 / x16 –TSOP II (54), BGA (54) [x16 only] x32 – TSOP II (86), BGA (90) • Temperature Range: Commercial (0°C to +70°C) Industrial (–40 ºC to 85 ºC) DESCRIPTION ISSI's 256Mb Mobile Synchronous DRAM achieves highspeed data transfer using pipeline architecture. All input and output signals refer to the rising edge of the clock input. Both write and read accesses to the SDRAM are burst oriented. The 256Mb Mobile Synchronous DRAM is designed to minimize current consumption making it ideal for low-power applications. Both TSOP and BGA packages are offered, including industrial grade products. KEY TIMING PARAMETERS Parameter -71 -752 -10 Unit CAS Latency = 3 7 7.5 10 ns CAS Latency = 2 9.6 9.6 12 ns CAS Latency = 3 143 133 100 Mhz CAS Latency = 2 104 104 83 Mhz CAS Latency = 3 5.4 5.4 8 ns CAS Latency = 2 8 8 9 ns CLK Cycle Time CLK Frequency Access Time from CLK 1. Available for x8/x16 only 2. Available for x32 only ADDRESSING TABLE Parameter 32M x 8 16M x 16 8M x 32 Configuration 8M x 8 x 4 banks 4M x 16 x 4 banks 2M x 32 x 4 banks Refresh Count 8K/64ms 8K/64ms 4K/64ms Row Addressing A0-A12 A0-A12 A0-A11 Column Addressing A0-A9 A0-A8 A0-A8 BA0, BA1 BA0, BA1 BA0, BA1 A10 A10 A10 Bank Addressing Precharge Addressing Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 1 IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D General Description ISSI’s 256Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V – 2.5V VDD and 3.3V – 2.5V VDDQ memory systems containing 268,435,456 bits. Internally configured as a quad-bank DRAM with a synchronous interface. The 256Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL (VDD = 3.3V) or LVCMOS (VDD = 2.5V) compatible. The 256Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an Active command begins accesses, followed by a Read or Write command. The ACTIVE command in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 (x8 and x16) and A0-A11 (x32) select the row). The READ or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations, or full page, with a burst terminate option. FUNCTIONAL BLOCK DIAGRAM (For 16Mx16 Banks SHOWN) 16 16 REFRESH CONTROLLER MODE REGISTER 13 2 SELF REFRESH A10 A12 CONTROLLER 16 DQ 0-15 VDD/VDDQ DATA OUT BUFFER Vss/VssQ 16 REFRESH COUNTER 13 MULTIPLEXER A11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0 BA1 DQML DQMH DATA IN BUFFER COMMAND DECODER & CLOCK GENERATOR ROW ADDRESS LATCH 13 13 COLUMN ADDRESS LATCH ROW ADDRESS BUFFER ROW DECODER CLK CKE CS RAS CAS WE 8192 8192 8192 8192 MEMORY CELL ARRAY BANK 0 SENSE AMP I/O GATE 512 (x 16) BANK CONTROL LOGIC 9 BURST COUNTER COLUMN ADDRESS BUFFER 2 COLUMN DECODER 9 Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D PIN CONFIGURATIONS 54 pin TSOP – Type II for x8 VDD 1 54 VSS DQ0 2 53 DQ7 VDDQ 3 52 VSSQ NC 4 51 NC DQ1 5 50 DQ6 VSSQ 6 49 VDDQ NC 7 48 NC DQ2 8 47 DQ5 VDDQ 9 46 VSSQ NC 10 45 NC DQ3 11 44 DQ4 VSSQ 12 43 VDDQ NC 13 42 NC VDD 14 41 VSS NC 15 40 NC WE 16 39 DQM CAS 17 38 CLK RAS 18 37 CKE CS 19 36 A12 BA0 20 35 A11 BA1 21 34 A9 A10 22 33 A8 A0 23 32 A7 A1 24 31 A6 A2 25 30 A5 A3 26 29 A4 VDD 27 28 VSS PIN DESCRIPTIONS 32M x 8 Pin Name 32M x 8 Pin Name A0–A12 Row Address Input CAS Column Address Strobe Command A0–A9 Column Address Input WE Write Enable BA0, BA1 Bank Select Address DQM Data Input/Output Mask DQ0–DQ7 Data Input/Output VDD Power CLK System Clock Input VSS Ground CKE Clock Enable VDDQ Power Supply for I/O Pin CS Chip Select VSSQ Ground for I/O Pin RAS Row Address Strobe Command NC No Connection Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 3 IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D PIN CONFIGURATIONS 54 pin TSOP – Type II for x16 VDD 1 54 VSS DQ0 2 53 DQ15 VDDQ 3 52 VSSQ DQ1 4 51 DQ14 DQ2 5 50 DQ13 VSSQ 6 49 VDDQ DQ3 7 48 DQ12 DQ4 8 47 DQ11 VDDQ 9 46 VSSQ DQ5 10 45 DQ10 DQ6 11 44 DQ9 VSSQ 12 43 VDDQ DQ7 13 42 DQ8 VDD 14 41 VSS DQML 15 40 NC WE 16 39 DQMH CAS 17 38 CLK RAS 18 37 CKE CS 19 36 A12 BA0 20 35 A11 BA1 21 34 A9 A10 22 33 A8 A0 23 32 A7 A1 24 31 A6 A2 25 30 A5 A3 26 29 A4 VDD 27 28 VSS PIN DESCRIPTIONS 16M x16 Pin Name 16M x16 Pin Name A0–A12 Row Address Input WE Write Enable A0–A8 Column Address Input DQML / DQMH Data Input/Output Mask BA0, BA1 Bank Select Address VDD Power DQ0–DQ15 Data Input/Output VSS Ground CLK System Clock Input VDDQ Power Supply for I/O Pin CKE Clock Enable VSSQ Ground for I/O Pin CS Chip Select NC No Connection RAS Row Address Strobe Command CAS Column Address Strobe Command 4 Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D PIN CONFIGURATIONS 54-ball TF-BGA for x16 (Top View) (8.00mm x 13.00mm Body, 0.8mm Ball Pitch) 1 A B C D E F G H J 2 3 4 5 6 7 8 9 VSS DQ15 VSSQ VDDQ DQ0 VDD DQ14 DQ13 VDDQ VSSQ DQ2 DQ1 DQ12 DQ11 VSSQ VDDQ DQ4 DQ3 DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 DQ8 NC VSS VDD DQML DQ7 DQMH CLK CKE CAS RAS WE A12 A11 A9 BA0 BA1 CS A8 A7 A6 A0 A1 A10 VSS A5 A4 A3 A2 VDD PIN DESCRIPTIONS 16M x16 Pin Name 16M x16 Pin Name A0–A12 Row Address Input CAS Column Address Strobe Command A0–A8 Column Address Input WE Write Enable BA0, BA1 Bank Select Address Data Input/Output Mask DQ0–DQ15 Data Input/Output DQML / DQMH CLK System Clock Input VDD Power CKE Clock Enable VSS Ground CS Chip Select VDDQ Power Supply for I/O Pin RAS Row Address Strobe Command VSSQ Ground for I/O Pin NC No Connection Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 5 IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D PIN CONFIGURATIONS 86 pin TSOP – Type II for x32 VDD 1 86 VSS DQ0 2 85 DQ15 VDDQ 3 84 VSSQ DQ1 4 83 DQ14 DQ2 5 82 DQ13 VSSQ 6 81 VDDQ DQ3 7 80 DQ12 DQ4 8 79 DQ11 VDDQ 9 78 VSSQ DQ5 10 77 DQ10 DQ6 11 76 DQ9 VSSQ 12 75 VDDQ DQ7 13 74 DQ8 NC 14 73 NC VDD 15 72 VSS DQM0 16 71 DQM1 WE 17 70 NC CAS 18 69 NC RAS 19 68 CLK CS 20 67 CKE A11 21 66 A9 BA0 22 65 A8 BA1 23 64 A7 A10 24 63 A6 A0 25 62 A5 A1 26 61 A4 A2 27 60 A3 DQM2 28 59 DQM3 VDD 29 58 VSS NC 30 57 NC DQ16 31 56 DQ31 VSSQ 32 55 VDDQ DQ17 33 54 DQ30 DQ18 34 53 DQ29 VDDQ 35 52 VSSQ DQ19 36 51 DQ28 DQ20 37 50 DQ27 VSSQ 38 49 VDDQ DQ21 39 48 DQ26 DQ22 40 47 DQ25 VDDQ 41 46 VSSQ DQ23 42 45 DQ24 VDD 43 44 VSS PIN DESCRIPTIONS 8M x32 Pin Name 8M x32 Pin Name A0–A11 Row Address Input WE Write Enable A0–A8 Column Address Input DQM0 - DQM3 Data Input/Output Mask BA0, BA1 Bank Select Address VDD Power DQ0–DQ31 Data Input/Output VSS Ground CLK System Clock Input VDDQ Power Supply for I/O Pin CKE Clock Enable VSSQ Ground for I/O Pin CS Chip Select NC No Connection RAS Row Address Strobe Command CAS Column Address Strobe Command 6 Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D PIN CONFIGURATIONS 90-ball TF-BGA for x32 (Top View) (8.00mm x 13.00mm Body, 0.8mm Ball Pitch) 1 2 3 4 5 6 7 8 9 A B C D E F G H J K L M N P R DQ26 DQ24 VSS VDD DQ23 DQ21 DQ28 VDDQ VSSQ VDDQ VSSQ DQ19 VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ VDDQ DQ31 NC NC DQ16 VSSQ VSS DQM3 A3 A2 DQM2 VDD A4 A5 A6 A10 A0 A1 A7 A8 NC NC BA1 A11 CLK CKE A9 BA0 CS RAS DQM1 NC NC CAS WE DQM0 VDDQ DQ8 VSS VDD DQ7 VSSQ VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ DQ11 VDDQ VSSQ DQ13 DQ15 VDDQ VSSQ DQ4 VSS VDD DQ0 DQ2 PIN DESCRIPTIONS 8M x32 Pin Name 8M x32 Pin Name A0–A11 Row Address Input WE Write Enable A0–A8 Column Address Input DQM0 - DQM3 Data Input/Output Mask BA0, BA1 Bank Select Address VDD Power DQ0–DQ31 Data Input/Output VSS Ground CLK System Clock Input VDDQ Power Supply for I/O Pin CKE Clock Enable VSSQ Ground for I/O Pin CS Chip Select NC No Connection RAS Row Address Strobe Command CAS Column Address Strobe Command Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 7 IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D Mobile SDRAM Functionality ISSI’s 256Mb Mobile SDRAMs are pin compatible and have similar functionality with ISSI’s standard SDRAMs, but offer lower operating voltages and power saving features. For detailed descriptions of pin functions, command truth tables, functional truth tables, device operation as well as timing diagrams please refer to ISSI document “Mobile Synchronous DRAM Device Operations & Timing Diagrams” listed at www.issi.com REGISTER DEFINITION Mode Register (MR) & Extended Mode Register (EMR) There are two mode registers in the Mobile SDRAM; Mode Register (MR) and Extended Mode Register (EMR). The Mode Register is discussed below, followed by the Extended Mode Register. The Mode Register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of burst length, a burst type, CAS Latency, operating mode, and a write burst mode. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. The EMR controls the functions beyond those controlled by the MR. These additional functions are special features of the Mobile SDRAM. They include temperature-compensated self refresh (TCSR) control, partial-array self refresh (PASR), and output drive strength. The EMR is programmed via the MODE REGISTER SET command with BA1 = 1 and BA0 = 0 and retains the stored information until it is programmed again or the device loses power. Not programming the extended mode register upon initialization will result in default settings for the low-power features. The extended mode will default with the temperature sensor enabled, full drive strength, and full array (all 4 banks) refresh. Mode Register Definition The MR is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure MODE REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode register bits M0 - M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4 M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the WRITE burst mode, and M10, M11, and M12 are reserved for future use. The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. 8 Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D MODE REGISTER DEFINITION BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus (Ax) Mode Register (Mx) Burst Length (1) Reserved M2 M1 M0 M3=0 M3=1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 2 4 8 Reserved Reserved Reserved Full Page 1 2 4 8 Reserved Reserved Reserved Reserved Burst Type M3 Type 0 1 Sequential Interleaved Latency Mode M6 M5 M4 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved Operating Mode M8 M7 M6-M0 Mode 0 0 — — Defined — Standard Operation All Other States Reserved Write Burst Mode BA1 BA0 0 0 Mode Register Definition Program Mode Register 0 1 Reserved 1 1 0 1 Program Extended Mode Register Reserved M9 0 1 Mode Programmed Burst Length Single Location Access 1. Note: A12 x8 and x16, A11 x32 2. To ensure compatibility with future devices, should program A12, A11, A10 = "0" Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A8 (x32), A1-A8 (x16) or A1-A9 (x8) when the burst length is set to two; by A2-A8 (x32), A2-A8 (x16) or A2-A9 (x8) when the burst length is set to four; and by A3-A8 (x32), A3-A8 (x16) or A3-A9 (x8) when the burst length is set to eight. The remaining (least significant) address bit(s) are used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 9 IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in BURST DEFINITION table. Burst Definition Burst Starting Column Order of Accesses Within a Burst Length Address Type = Sequential Type = Interleaved A0 2 0 0-1 0-1 1 1-0 1-0 A1 A0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 A2 A1 A0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 Full n = A0-A8 (x16, x32) Cn, Cn + 1, Cn + 2 Not Supported Page n = A0-A9 (x8) Cn + 3, Cn + 4... (y) (location 0-y) …Cn - 1, Cn… CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in CAS Latency diagrams. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. 10 Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. CAS Latency T0 T1 T2 T3 READ NOP NOP CLK COMMAND tAC DOUT DQ tOH tLZ CAS Latency - 2 T0 T1 T2 T3 T4 READ NOP NOP NOP CLK COMMAND tAC DOUT DQ tLZ tOH CAS Latency - 3 DON'T CARE UNDEFINED Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 11 IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D Extended Mode Register Definition BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus (Ax) Ext. Mode Reg. (Ex) PASR E2 E1 E0 Partial Array Self Refresh Coverage 0 0 0 Fully array (4 banks) - (Default) 0 0 1 Half array (banks 0, 1) 0 1 0 Quarter array (bank 0) 0 1 1 Reserved 1 0 0 Reserved 1 0 1 One-eighth array (1/2 bank 0) 1 1 0 One-sixteenth array (1/4 bank 0) 1 1 1 Reserved TCSR E4 0 0 1 1 DS E6 0 0 1 1 set to "0" E12 E11 E10 E9 0 0 0 0 – – – – E8 0 – E7 0 – E5 0 1 0 1 E3 0 1 0 1 Max. Case Temp. 70oC 45oC 15oC 85oC (Default) Driver Strength Full strength driver (Default) Half strength driver Quarter strength driver Reserved E6-E0 Valid Normal operation – All other states reserved BA1 BA0 Mode Register Definition 0 0 Program Mode Register 0 1 Reserved 1 0 Program Extended mode Register 1 1 Reserved The extended mode register is programmed via the MODE REGISTER SET command (BA1 = 1, BA0 = 0) and retains the stored information until it is programmed again or the device loses power. The extended mode register must be programmed with E7 through E11 (or E12 for x8 & x16) set to “0.” The extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements results in unspecified operation. The extended mode register must be programmed to ensure proper operation. Temperature-Compensated Self Refresh (TCSR) TCSR allows the controller to program the refresh interval during self refresh mode, according to the case temperature of the mobile device. This allows great power savings during self refresh during most operating temperature ranges. Only during extreme temperatures would the controller have to select a higher TCSR level that will guarantee data during self refresh. 12 Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often. Historically, during self refresh, the refresh rate has been set to accommodate the worst case, or highest temperature range, expected. Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high because the refresh rate was set to accommodate the higher temperatures. Setting E4 and E3 allows the DRAM to accommodate more specific temperature regions during self refresh. The default for ISSI 256Mb Mobile SDRAM is TCSR = 85°C to guarantee refresh operation. This mode of operation has a higher current consumption because the self refresh oscillator is set to refresh the SDRAM cells more often than needed. By using an external temperature sensor to determine the operating temperature the Mobile SDRAM can be programmed for lower temperature and refresh rates, effectively reducing current consumption by a significant amount. There are four temperature settings, which will vary the self refresh current according to the selected temperature. This selectable refresh rate will save power when the Mobile DRAM is operating at normal temperatures. Partial-Array Self Refresh (PASR) For further power savings during self refresh, the PASR feature allows the controller to select the amount of memory that will be refreshed during self refresh. The refresh options are all banks (banks 0, 1, 2, and 3); two banks (banks 0 and 1); and one bank (bank 0). In addition partial amounts of bank 0 (half or quarter of the bank) may be selected. WRITE and READ commands occur to any bank selected during standard operation, but only the selected banks in PASR will be refreshed during self refresh. It’s important to note that data in banks 2 and 3 will be lost when the twobank option is used. Data will be lost in banks 1, 2, and 3 when the one-bank option is used. Driver Strength (DS) Bits E5 and E6 of the EMR can be used to select the driver strength of the DQ outputs. This value should be set according to the application’s requirements. The default is Full Driver Strength. Deep Power Down (DPD) Deep power down mode is for maximum power savings and is achieved by shutting down power to the entire memory array of the mobile device. Data will be lost once deep power down mode is executed. DPD mode is entered by having all banks idle, CS and WE held low, with RAS and CAS HIGH at the rising edge of the clock, while CKE is LOW. CKE must be held LOW during DPD mode. To exit DPD mode, CKE must be asserted HIGH. Upon exit from DPD mode, at least 200ms of valid clocks with either NOP or COMMAND INHIBIT commands are applied to the command bus, followed by a full Mobile SDRAM initialization sequence, is required. Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 13 IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D Electrical Specifications ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameters Vdd max Maximum Supply Voltage Vddq max Maximum Supply Voltage for Output Buffer Vin Input Voltage Vout Output Voltage Pd max Allowable Power Dissipation Ics Output Shorted Current Topr Operating Temperature Com. Ind. Tstg Storage Temperature Rating –0.5 to +4.6 –0.5 to +4.6 –0.5 to Vddq + 0.5 –1.0 to Vddq + 0.5 1 50 0 to +70 –40 to +85 –65 to +150 Unit V V V V W mA °C °C °C Notes: 1.  Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2.  All voltages are referenced to Vss. Capacitance Characteristics - x8, x16 Symbol Cin1 Cin2 Ci/o Parameters Input Capacitance: CLK Input Capacitance: All Other Input Pins Data Input/Output Capacitance: I/Os Min. 2.5 2.5 4.0 Max. 3.5 3.8 6.0 Unit pF pF pF Min. 2.5 2.5 4.0 Max. 3.5 3.8 6.5 Unit pF pF pF Capacitance Characteristics - x32 Symbol Cin1 Cin2 Ci/o 14 Parameters Input Capacitance: CLK Input Capacitance: All Other Input Pins Data Input/Output Capacitance: I/Os Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D DC RECOMMENDED OPERATING CONDITIONS IS42SMxxx - 3.3V Operation Symbol Vdd Vddq Vih(1) Vil(2) Iil Iol Voh Vol Parameters Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current (0V ≤ Vin ≤ Vdd) Output Leakage Current (Output disabled, 0V ≤ Vout ≤ Vdd) Output High Voltage Current (Ioh = -2mA) Output Low Voltage Current (Iol = 2mA) Min. 3.0 3.0 2.0 -0.3 -5 -5 2.4 – Typ. 3.3 3.3 – – – – – – Max. 3.6 3.6 Vddq+0.3 0.8 +5 +5 – 0.4 Unit V V V V µA µA V V Max. 2.7 2.7 Vdd+0.3 0.55 +5 +5 0.2 Unit V V V V µA µA V V IS42RMxxx - 2.5V Operation Symbol Vdd Vddq Vih(1) Vil(2) Iil Iol Voh Vol Parameters Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current (0V ≤ Vin ≤ Vdd) Output Leakage Current (Output disabled, 0V ≤ Vout ≤ Vdd) Output High Voltage Current (Ioh = -2mA) Output Low Voltage Current (Iol = 2mA) Min. 2.3 2.3 2.0 -0.3 -5 -5 Vdd-0.2 - Typ. 2.5 2.5 – – – – Notes: 1. Vih (overshoot): Vih (max) = Vddq +1.2V (pulse width < 3ns). 2. Vil (undershoot): Vih (min) = -1.2V (pulse width < 3ns). 3. All voltages are referenced to Vss. Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 15 IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D DC ELECTRICAL CHARACTERISTICS VDD = 3.3V/2.5V (x8 and x16) Symbol Parameter Test Condition –7 –10 Unit Idd1 Operating Current One Bank Active, CL = 3, BL = 1, 85 75 mA 1 1 mA 1 1 mA 35 35 mA 20 20 mA 2 2 mA 2 2 mA 40 40 mA 25 25 mA 110 80 mA tRC = tRC(min), tCLK = tCLK(min) 160 120 mA 1.2 1.2 mA (1) tCLK = tCLK(min), tRC = tRC(min) Idd2p (4) Idd2ps (4) Precharge Standby Current CKE ≤ Vil (max), tCK = 15ns (In Power-Down Mode) CS ≥ Vdd - 0.2V Precharge Standby Current CKE ≤ Vil (max), CLK ≤ Vil (max) With Clock Stop CS ≥ Vdd - 0.2V (In Power-Down Mode) Idd2n (2) Idd2ns Precharge Standby Current CS ≥ Vdd - 0.2V, CKE ≥ Vih (min) (In Non Power-Down Mode) tCK = 15 ns Precharge Standby Current CS ≥ Vdd - 0.2V, CKE ≥ Vih (min) With Clock Stop All Inputs Stable (In Non-Power Down Mode) Idd3p(2) Idd3ps Active Standby Current CKE ≤ Vil (max), CS ≥ Vdd - 0.2V (In Power-Down Mode) tCK = 15 ns Active Standby Current CKE ≤ Vil (max), CLK ≤ Vil (max) With Clock Stop CS ≥ Vdd - 0.2V (In Power-Down Mode) Idd3n (2) Idd3ns Active Standby Current CS ≥ Vdd - 0.2V, CKE ≥ Vih (min) (In Non Power-Down Mode) tCK = 15 ns Active Standby Current CS ≥ Vdd - 0.2V, CKE ≥ Vih (min) With Clock Stop All Inputs Stable (In Non Power-Down Mode) Idd4 Operating Current All Banks Active, BL = FULL, CL = 3 tCK = tCK(min) Idd5 Auto-Refresh Current Idd6 Self-Refresh Current CKE ≤ 0.2V Idd7 Self-Refresh: CKE = LOW; tck = tck (MIN); Address, Control, and Data bus inputs are stable Full Array, 85oC Full Array, 45oC Half Array, 85oC Half Array, 45oC 1/4th Array, 85oC 1/4th Array, 45oC 1/8th Array, 85oC 1/8th Array, 45oC 1/16th Array, 85oC 1/16th Array, 45oC Izz(3,4) Deep Power Down Current CKE ≤ 0.2V mA 1200 800 1000 670 800 540 700 470 600 400 20 20 mA Notes: 1. Idd (max) is specified at the output open condition. 2. Input signals are changed one time during 30ns. 3. Izz values shown are nominal at 25oC. Izz is not tested. 4. Tested after 500ms delay 16 Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D DC ELECTRICAL CHARACTERISTICS VDD = 3.3V/2.5V (x32) Symbol Parameter Test Condition –75 –10 Unit Idd1 Operating Current One Bank Active, CL = 3, BL = 1, 130 110 mA 1 1 mA 1 1 mA 45 45 mA 30 30 mA 4 4 mA 3 3 mA 55 55 mA 30 30 mA 160 120 mA (1) tCLK = tCLK(min), tRC = tRC(min) Idd2p (4) Idd2ps (4) Precharge Standby Current CKE ≤ Vil (max), tCK = 15ns (In Power-Down Mode) CS ≥ Vdd - 0.2V Precharge Standby Current CKE ≤ Vil (max), CLK ≤ Vil (max) With Clock Stop CS ≥ Vdd - 0.2V (In Power-Down Mode) Idd2n (2) Idd2ns Precharge Standby Current CS ≥ Vdd - 0.2V, CKE ≥ Vih (min) (In Non Power-Down Mode) tCK = 15 ns Precharge Standby Current CS ≥ Vdd - 0.2V, CKE ≥ Vih (min) With Clock Stop All Inputs Stable (In Non-Power Down Mode) Idd3p (2) Idd3ps Active Standby Current CKE ≤ Vil (max), CS ≥ Vdd - 0.2V (In Power-Down Mode) tCK = 15 ns Active Standby Current CKE ≤ Vil (max), CLK ≤ Vil (max) With Clock Stop CS ≥ Vdd - 0.2V (In Power-Down Mode) Idd3n(2) Idd3ns Active Standby Current CS ≥ Vdd - 0.2V, CKE ≥ Vih (min) (In Non Power-Down Mode) tCK = 15 ns Active Standby Current CS ≥ Vdd - 0.2V, CKE ≥ Vih (min) With Clock Stop All Inputs Stable (In Non Power-Down Mode) Idd4 Operating Current All Banks Active, BL = FULL, CL = 3 tCK = tCK(min) Idd5 Auto-Refresh Current tRC = tRC(min), tCLK = tCLK(min) 280 240 mA Idd6 Self-Refresh Current CKE ≤ 0.2V 1.2 1.2 mA Idd7 Self-Refresh: CKE = LOW; tck = tck (MIN); Address, Control, and Data bus inputs are stable Full Array, 85 C Full Array, 45oC Half Array, 85oC Half Array, 45oC 1/4th Array, 85oC 1/4th Array, 45oC 1/8th Array, 85oC 1/8th Array, 45oC 1/16th Array, 85oC 1/16th Array, 45oC Izz (3,4) Deep Power Down Current CKE ≤ 0.2V mA 1200 800 1000 670 800 540 700 470 600 400 o 20 20 mA Notes: 1. Idd (max) is specified at the output open condition. 2. Input signals are changed one time during 30ns. 3. Izz values shown are nominal at 25oC. Izz is not tested. 4. Tested after 500ms delay Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 17 IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D AC ELECTRICAL CHARACTERISTICS (1, 2, 3) Symbol Parameter tCK3 Clock Cycle Time CAS Latency = 3 -7 (x8/x16 only) Min. Max. 7 – tCK2 tAC3 CAS Latency = 2 CAS Latency = 3 9.6 – – 5.4 9.6 – CAS Latency = 2 – 2.5 2.5 2.7 8.0 – – – 2.7 0 2.7 tAC2 tCHI tCL tOH3 tOH2 tLZ tHZ3 tHZ2 tDS tDH tAS tAH tCKS tCKH tCS Access Time From CLK CLK HIGH Level Width CLK LOW Level Width Output Data Hold Time CAS Latency = 2 Output LOW Impedance Time Output HIGH Impedance Time CAS Latency = 3 CAS Latency = 2 tMRD tDDE tSRX tT Input Data Setup Time (2) Input Data Hold Time (2) Address Setup Time (2) Address Hold Time (2) CKE Setup Time (2) CKE Hold Time (2) Command Setup Time (CS, RAS, CAS, WE, DQM)(2) Command Hold Time (CS, RAS, CAS, WE, DQM)(2) Command Period (REF to REF / ACT to ACT) Command Period (ACT to PRE) Command Period (PRE to ACT) Active Command to Read/ Write Command Delay Time Command Period (ACT [0] to ACT [1]) Input Data to Precharge Command Delay Time Input Data to Active/Refresh Command Delay Time (During Auto-Precharge) Mode Register Program Time Power Down Exit Setup Time Self-Refresh Exit Time Transition Time tREF Refresh Cycle Time tCH tRC tRAS tRP tRCD tRRD tDPL tDAL CAS Latency = 3 8K times (x8/x16) 4K times (x32) -75 (x32 only) Min. Max. 7.5 – -10 Min. 10 Max. – Unit ns – 5.4 12 – – 8.0 ns ns – 2.5 2.5 2.7 8.0 – – – – 2.5 2.5 2.7 9.0 – – – ns ns ns ns – – 5.4 2.7 0 2.7 – – 5.4 2.7 0 2.7 – – 8.0 ns ns ns 2.7 1.5 1.0 1.5 1.0 1.5 1.0 1.5 8.0 – – – – – – – 2.7 1.5 1.0 1.5 1.0 1.5 1.0 1.5 8.0 – – – – – – – 2.7 1.5 1.0 1.5 1.0 1.5 1.0 1.5 9.0 – – – – – – – ns ns ns ns ns ns ns 1.0 – 1.0 – 1.0 – ns 67.5 – 67.5 – 90 – ns 45 100K 45 100K 60 100K ns 19 – 19 – 24 – ns 19 – 19 – 24 – ns 14 – 15 – 20 – ns 14 – 15 – 20 – ns 35 – 37.5 – 48 – ns 14 7 80 0.3 – – – – – 1.2 64 – 15 7.5 80 0.3 – – – – – 1.2 – 64 20 10 80 0.3 – – – – – 1.2 64 64 ns ns ns ns ms ms Notes: 1. The power-on sequence must be executed before starting memory operation. 2. Measured with tT = 1 ns. If clock rising time is longer than 1ns, (tR /2 - 0.5) ns should be added to the parameter. 3. The reference level is 1.4V when measuring input signal timing. Rise and fall times are measured between Vih(min.) and Vil (max). 18 Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D OPERATING FREQUENCY / LATENCY RELATIONSHIPS Symbol Parameter -7 -75 -10 Units — Clock Cycle Time 7 7.5 10 ns — Operating Frequency 143 133 100 MHz tcac CAS Latency 3 3 3 cycle trcd Active Command To Read/Write Command Delay Time 3 3 3 cycle trac RAS Latency (trcd + tcac) 6 6 6 cycle trc Command Period (REF to REF / ACT to ACT) 10 9 9 cycle tras Command Period (ACT to PRE) 7 6 6 cycle trp Command Period (PRE to ACT) 3 3 3 cycle trrd Command Period (ACT[0] to ACT [1]) 2 2 2 cycle tccd Column Command Delay Time (READ, READA, WRIT, WRITA) 1 1 1 cycle tdpl Input Data To Precharge Command Delay Time 2 2 2 cycle tdal Input Data To Active/Refresh Command Delay Time (During Auto-Precharge) 5 5 5 cycle trbd Burst Stop Command To Output in HIGH-Z Delay Time (Write) 3 3 3 cycle twbd Burst Stop Command To Input in Invalid Delay Time (Write) 0 0 0 cycle trql Precharge Command To Output in HIGH-Z Delay Time (Read) 3 3 3 cycle twdl Precharge Command To Input in Invalid Delay Time (Write) 0 0 0 cycle tpql Last Output To Auto-Precharge Start Time (Read) -2 -2 -2 cycle tqmd DQM To Output Delay Time (Read) 2 2 2 cycle tdmd DQM To Input Delay Time (Write) 0 0 0 cycle tmrd Mode Register Set To Command Delay Time 2 2 2 cycle Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 CAS Latency = 3 CAS Latency = 3 CAS Latency = 3 CAS Latency = 3 19 IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D Ordering Information – Vdd = 3.3V Commercial Range: (0°C to +70°C) Configuration 16Mx16 8Mx32 Frequency (MHz) 143 133 Speed (ns) 7 7.5 Order Part No. IS42SM16160D-7BL IS42SM32800D-75BL Package 54-Ball BGA, Lead-free 90-Ball BGA, Lead-free Order Part No. IS42SM83200D-7TLI IS42SM16160D-7TLI IS42SM16160D-7BLI IS42SM16160D-10TLI IS42SM16160D-10BLI IS42SM32800D-75TLI IS42SM32800D-75BLI IS42SM32800D-10TLI IS42SM32800D-10BLI Package 54-pin TSOP II, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA, Lead-free 86-pin TSOP II, Lead-free 90-Ball BGA, Lead-free 86-pin TSOP II, Lead-free 90-Ball BGA, Lead-free Industrial Range: (–40ºC to 85ºC) Configuration 32Mx8 16Mx16 8Mx32 20 Frequency (MHz) 143 143 Speed (ns) 7 7 100 10 133 7.5 100 10 Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D Ordering Information – Vdd = 2.5V Commercial Range: (0°C to +70°C) Configuration 16Mx16 8Mx32 Frequency (MHz) 143 133 Speed (ns) 7 7.5 Order Part No. IS42RM16160D-7BL IS42RM32800D-75BL Package 54-Ball BGA, Lead-free 90-Ball BGA, Lead-free Order Part No. IS42RM83200D-7TLI IS42RM16160D-7TLI IS42RM16160D-7BLI IS42RM16160D-10TLI IS42RM16160D-10BLI IS42RM32800D-75TLI IS42RM32800D-75BLI IS42RM32800D-10TLI IS42RM32800D-10BLI Package 54-pin TSOP II, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA, Lead-free 86-pin TSOP II, Lead-free 90-Ball BGA, Lead-free 86-pin TSOP II, Lead-free 90-Ball BGA, Lead-free Industrial Range: (–40ºC to 85ºC) Configuration 32Mx8 16Mx16 8Mx32 Frequency (MHz) 143 143 Speed (ns) 7 7 100 10 133 7.5 100 10 Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 21 22 Θ Package Outline 09/01/2006 4. Formed leads shall be planar with respect to one another within 0.1mm at the seating plane after final test. 3. Dimension b does not include dambar protrusion/intrusion. 2. Dimension D and E1 do not include mold protrusion . 1. Controlling dimension : mm NOTE : Θ IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 Package Outline 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MS-207 NOTE : 08/29/2008 IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D 23 24 Θ Package Outline 09/26/2006 4. Formed leads shall be planar with respect to one another within 0.1mm at the seating plane after final test. 3. Dimension b does not include dambar protrusion/intrusion. 2. Dimension D and E1 do not include mold protrusion . 1. Controlling dimension : mm NOTE : Θ IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 08/14/2008 0.80 Package Outline 0.45 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 NOTE : IS42SM83200D / IS42SM16160D / IS42SM32800D IS42RM83200D / IS42RM16160D / IS42RM32800D D1 Integrated Silicon Solution, Inc. - www.issi.com Rev.  A 10/22/09 25